From 1155d8d853ff8639062651a903ae3062f483dc70 Mon Sep 17 00:00:00 2001 From: Rotariu Marian-Cristian Date: Mon, 19 May 2014 10:59:52 +0300 Subject: net/fm: call fm_port_to_index() with proper checks Some of the fm_port_to_index() callers did not check for -1 return value and used -1 as an array index. Signed-off-by: Marian Rotariu Reviewed-by: York Sun --- drivers/net/fm/fm.h | 3 ++- drivers/net/fm/init.c | 6 ++++++ 2 files changed, 8 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h index 43de114b52..316e06e17e 100644 --- a/drivers/net/fm/fm.h +++ b/drivers/net/fm/fm.h @@ -143,6 +143,7 @@ struct fm_eth { #define MAX_RXBUF_LOG2 11 #define MAX_RXBUF_LEN (1 << MAX_RXBUF_LOG2) -#define PORT_IS_ENABLED(port) fm_info[fm_port_to_index(port)].enabled +#define PORT_IS_ENABLED(port) (fm_port_to_index(port) == -1 ? \ + 0 : fm_info[fm_port_to_index(port)].enabled) #endif /* __FM_H__ */ diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c index cd787f4eed..ff04695c32 100644 --- a/drivers/net/fm/init.c +++ b/drivers/net/fm/init.c @@ -147,6 +147,9 @@ void fm_disable_port(enum fm_port port) { int i = fm_port_to_index(port); + if (i == -1) + return; + fm_info[i].enabled = 0; fman_disable_port(port); } @@ -155,6 +158,9 @@ void fm_enable_port(enum fm_port port) { int i = fm_port_to_index(port); + if (i == -1) + return; + fm_info[i].enabled = 1; fman_enable_port(port); } -- cgit v1.2.1 From 38d67a4e552ac991f21c2d3e442a38fb0098fda6 Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Tue, 3 Jun 2014 16:27:07 +0800 Subject: qe: move immap_qe.h from arch directory into common directory ls1021 is arm-core and supports qe too. Move immap_qe.h into common directory for both arm and powerpc. Signed-off-by: Zhao Qiang Reviewed-by: York Sun --- drivers/bootcount/bootcount.c | 2 +- drivers/qe/qe.c | 2 +- drivers/qe/uccf.c | 2 +- drivers/qe/uccf.h | 2 +- drivers/qe/uec.c | 2 +- drivers/qe/uec_phy.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/bootcount/bootcount.c b/drivers/bootcount/bootcount.c index 3ad441393e..e0343f71d7 100644 --- a/drivers/bootcount/bootcount.c +++ b/drivers/bootcount/bootcount.c @@ -36,7 +36,7 @@ #endif /* defined(CONFIG_MPC8260) */ #if defined(CONFIG_QE) -#include +#include #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + 0x110000 + \ QE_MURAM_SIZE - 2 * sizeof(u32)) diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 9c5fbd1d69..be09a17297 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -11,7 +11,7 @@ #include #include "asm/errno.h" #include "asm/io.h" -#include "asm/immap_qe.h" +#include "linux/immap_qe.h" #include "qe.h" #define MPC85xx_DEVDISR_QE_DISABLE 0x1 diff --git a/drivers/qe/uccf.c b/drivers/qe/uccf.c index 593d96d1a2..85386bfc70 100644 --- a/drivers/qe/uccf.c +++ b/drivers/qe/uccf.c @@ -11,7 +11,7 @@ #include "malloc.h" #include "asm/errno.h" #include "asm/io.h" -#include "asm/immap_qe.h" +#include "linux/immap_qe.h" #include "qe.h" #include "uccf.h" diff --git a/drivers/qe/uccf.h b/drivers/qe/uccf.h index 0b57e2f422..55941e4601 100644 --- a/drivers/qe/uccf.h +++ b/drivers/qe/uccf.h @@ -12,7 +12,7 @@ #include "common.h" #include "qe.h" -#include "asm/immap_qe.h" +#include "linux/immap_qe.h" /* Fast or Giga ethernet */ diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 68045733b8..c91f084a7c 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -11,7 +11,7 @@ #include "malloc.h" #include "asm/errno.h" #include "asm/io.h" -#include "asm/immap_qe.h" +#include "linux/immap_qe.h" #include "qe.h" #include "uccf.h" #include "uec.h" diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index 5dc4641bf6..e701787c41 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -14,7 +14,7 @@ #include "net.h" #include "malloc.h" #include "asm/errno.h" -#include "asm/immap_qe.h" +#include "linux/immap_qe.h" #include "asm/io.h" #include "qe.h" #include "uccf.h" -- cgit v1.2.1 From 3bab3d8324874604501ff9154e68732fb986057a Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Thu, 12 Jun 2014 09:13:08 +0530 Subject: driver/nand:Define MAX_BANKS same as SoC defined for IFC The number of chip select used by IFC controller vary from one SoC to other. For eg. P1010 has 4, T4240 has 8. Update MAX_BANKS same as SoC defined Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- drivers/mtd/nand/fsl_ifc_nand.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index be5a16a1ba..27f5177d71 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -19,8 +19,12 @@ #include #include +#ifndef CONFIG_SYS_FSL_IFC_BANK_COUNT +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 +#endif + #define FSL_IFC_V1_1_0 0x01010000 -#define MAX_BANKS 4 +#define MAX_BANKS CONFIG_SYS_FSL_IFC_BANK_COUNT #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ #define IFC_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for IFC -- cgit v1.2.1 From 04818bbdc34cb02b2590af8e5f77118ed8a8d755 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Thu, 12 Jun 2014 12:14:00 +0530 Subject: driver/nand: Update SRAM initialize logic for IFC. IFC controller v1.1.0 requires internal SRAM initialize by reading NAND flash. Higher controller versions have provided "SRAM init" bit in NCFGR register space. update SRAM initialize logic to reflect the same. Also print error message in case of Page read error. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- drivers/mtd/nand/fsl_ifc_nand.c | 35 +++++++++++++++++++++++++++++++---- 1 file changed, 31 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 27f5177d71..280e14e24a 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -806,12 +806,30 @@ static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip) { } -static void fsl_ifc_sram_init(void) +static int fsl_ifc_sram_init(uint32_t ver) { struct fsl_ifc *ifc = ifc_ctrl->regs; uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0; + uint32_t ncfgr = 0; long long end_tick; + if (ver > FSL_IFC_V1_1_0) { + ncfgr = ifc_in32(&ifc->ifc_nand.ncfgr); + ifc_out32(&ifc->ifc_nand.ncfgr, ncfgr | IFC_NAND_SRAM_INIT_EN); + + /* wait for SRAM_INIT bit to be clear or timeout */ + end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks(); + while (end_tick > get_ticks()) { + ifc_ctrl->status = + ifc_in32(&ifc->ifc_nand.nand_evter_stat); + + if (!(ifc_ctrl->status & IFC_NAND_SRAM_INIT_EN)) + return 0; + } + printf("fsl-ifc: Failed to Initialise SRAM\n"); + return 1; + } + cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT; /* Save CSOR and CSOR_ext */ @@ -854,11 +872,18 @@ static void fsl_ifc_sram_init(void) break; } + if (ifc_ctrl->status != IFC_NAND_EVTER_STAT_OPC) { + printf("fsl-ifc: Failed to Initialise SRAM\n"); + return 1; + } + ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status); /* Restore CSOR and CSOR_ext */ ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor); ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext); + + return 0; } static int fsl_ifc_chip_init(int devnum, u8 *addr) @@ -868,7 +893,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) struct fsl_ifc_mtd *priv; struct nand_ecclayout *layout; uint32_t cspr = 0, csor = 0, ver = 0; - int ret; + int ret = 0; if (!ifc_ctrl) { fsl_ifc_ctrl_init(); @@ -1010,8 +1035,10 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) } ver = ifc_in32(&ifc_ctrl->regs->ifc_rev); - if (ver == FSL_IFC_V1_1_0) - fsl_ifc_sram_init(); + if (ver >= FSL_IFC_V1_1_0) + ret = fsl_ifc_sram_init(ver); + if (ret) + return ret; ret = nand_scan_ident(mtd, 1, NULL); if (ret) -- cgit v1.2.1 From 32514d259bf37cc92872aeb0624b75f600e7fb3a Mon Sep 17 00:00:00 2001 From: Zang Roy-R61911 Date: Thu, 12 Jun 2014 14:49:23 -0500 Subject: fsl/pcie: Change 'no link' to 'undetermined' for pcie endpoint Even u-boot boots up, the pcie link may not setup correctly when Freescale SOC acts as endpoint. So change the link status from 'no link' to 'undetermined' to reduce the confusion. The link status can check from host side eventually. Signed-off-by: Roy Zang Reviewed-by: York Sun --- drivers/pci/fsl_pci_init.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 3a41b0ec17..231b07573f 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -504,8 +504,14 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) } #endif if (!enabled) { - /* Let the user know there's no PCIe link */ - printf("no link, regs @ 0x%lx\n", pci_info->regs); + /* Let the user know there's no PCIe link for root + * complex. for endpoint, the link may not setup, so + * print undetermined. + */ + if (fsl_is_pci_agent(hose)) + printf("undetermined, regs @ 0x%lx\n", pci_info->regs); + else + printf("no link, regs @ 0x%lx\n", pci_info->regs); hose->last_busno = hose->first_busno; return; } -- cgit v1.2.1 From 591dd192307d81cf8f8705b06854e973c53d4c4d Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Sat, 14 Jun 2014 08:48:19 +0530 Subject: driver/nand: Add support of 16K SRAM for IFC 2.0 Internal SRAM has been incresed from 8KB to 16KB for IFC cotroller ver 2.0. Update the page offset calculation logic to support the same. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- drivers/mtd/nand/fsl_ifc_nand.c | 4 +++- drivers/mtd/nand/fsl_ifc_spl.c | 6 +++++- 2 files changed, 8 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 280e14e24a..8b453cb383 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -23,7 +23,6 @@ #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #endif -#define FSL_IFC_V1_1_0 0x01010000 #define MAX_BANKS CONFIG_SYS_FSL_IFC_BANK_COUNT #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ @@ -1040,6 +1039,9 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) if (ret) return ret; + if (ver >= FSL_IFC_V2_0_0) + priv->bufnum_mask = (priv->bufnum_mask * 2) + 1; + ret = nand_scan_ident(mtd, 1, NULL); if (ret) return ret; diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c index 510077282c..e336cb1c94 100644 --- a/drivers/mtd/nand/fsl_ifc_spl.c +++ b/drivers/mtd/nand/fsl_ifc_spl.c @@ -97,7 +97,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) int pages_per_blk; int blk_size; int bad_marker = 0; - int bufnum_mask, bufnum; + int bufnum_mask, bufnum, ver = 0; int csor, cspr; int pos = 0; @@ -130,6 +130,10 @@ int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) bad_marker = 5; } + ver = ifc_in32(&ifc->ifc_rev); + if (ver >= FSL_IFC_V2_0_0) + bufnum_mask = (bufnum_mask * 2) + 1; + pages_per_blk = 32 << ((csor & CSOR_NAND_PB_MASK) >> CSOR_NAND_PB_SHIFT); -- cgit v1.2.1 From 8340e7ac86ad3c59956e8f0bd627b741e5209439 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 23 Jun 2014 15:36:44 -0700 Subject: driver/ddr: Fix DDR4 driver for ARM Previously the driver was only tested on Power SoCs. Different barrier instructions are needed for ARM SoCs. Signed-off-by: York Sun --- drivers/ddr/fsl/fsl_ddr_gen4.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 7cd878aeec..bfc76b3485 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) @@ -183,12 +184,14 @@ step2: * we choose the max, that is 500 us for all of case. */ udelay(500); - asm volatile("sync;isync"); + mb(); + isb(); /* Let the controller go */ temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); - asm volatile("sync;isync"); + mb(); + isb(); total_gb_size_per_controller = 0; for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { -- cgit v1.2.1 From 3d75ec95f57224995210db5c5dea8d458cf862fb Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 26 Jun 2014 11:14:44 -0700 Subject: driver/ddr: Fix DDR register timing_cfg_8 The field wrtord_bg should add 2 clocks if on the fly chop is enabled, according to DDR controller manual for DDR4. Signed-off-by: York Sun --- drivers/ddr/fsl/ctrl_regs.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index dcf6287f66..04e4178b15 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -1857,6 +1857,9 @@ static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr, acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps); wrtord_bg = max(4, picos_to_mclk(7500)); + if (popts->otf_burst_chop_en) + wrtord_bg += 2; + pre_all_rec = 0; ddr->timing_cfg_8 = (0 -- cgit v1.2.1