From 5dc626f836190fa2ef27f34e263b53641c14087c Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 11 Sep 2015 20:17:32 +0900 Subject: pinctrl: uniphier: add UniPhier pinctrl core support The core support for the pinctrl drivers for all the UniPhier SoCs. Signed-off-by: Masahiro Yamada Reviewed-by: Simon Glass --- drivers/pinctrl/Kconfig | 2 + drivers/pinctrl/Makefile | 2 + drivers/pinctrl/uniphier/Kconfig | 6 + drivers/pinctrl/uniphier/Makefile | 1 + drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 154 +++++++++++++++++++++++ drivers/pinctrl/uniphier/pinctrl-uniphier.h | 113 +++++++++++++++++ 6 files changed, 278 insertions(+) create mode 100644 drivers/pinctrl/uniphier/Kconfig create mode 100644 drivers/pinctrl/uniphier/Makefile create mode 100644 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c create mode 100644 drivers/pinctrl/uniphier/pinctrl-uniphier.h (limited to 'drivers') diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index b8146df99b..3b6e3b7060 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -124,4 +124,6 @@ config PINCTRL_SANDBOX endif +source "drivers/pinctrl/uniphier/Kconfig" + endmenu diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index f537df4e88..e56a17f966 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -3,3 +3,5 @@ obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC) += pinctrl-generic.o obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o + +obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/ diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig new file mode 100644 index 0000000000..29a623dfc1 --- /dev/null +++ b/drivers/pinctrl/uniphier/Kconfig @@ -0,0 +1,6 @@ +if ARCH_UNIPHIER + +config PINCTRL_UNIPHIER_CORE + bool + +endif diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile new file mode 100644 index 0000000000..748aa1b4e4 --- /dev/null +++ b/drivers/pinctrl/uniphier/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_PINCTRL_UNIPHIER_CORE) += pinctrl-uniphier-core.o diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c new file mode 100644 index 0000000000..37a920ca8b --- /dev/null +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c @@ -0,0 +1,154 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#include "pinctrl-uniphier.h" + +DECLARE_GLOBAL_DATA_PTR; + +static int uniphier_pinctrl_get_groups_count(struct udevice *dev) +{ + struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->socdata->groups_count; +} + +static const char *uniphier_pinctrl_get_group_name(struct udevice *dev, + unsigned selector) +{ + struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->socdata->groups[selector].name; +} + +static int uniphier_pinmux_get_functions_count(struct udevice *dev) +{ + struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->socdata->functions_count; +} + +static const char *uniphier_pinmux_get_function_name(struct udevice *dev, + unsigned selector) +{ + struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->socdata->functions[selector]; +} + +static void uniphier_pinconf_input_enable(struct udevice *dev, unsigned pin) +{ + struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); + int pins_count = priv->socdata->pins_count; + const struct uniphier_pinctrl_pin *pins = priv->socdata->pins; + int i; + + for (i = 0; i < pins_count; i++) { + if (pins[i].number == pin) { + unsigned int iectrl; + u32 tmp; + + iectrl = uniphier_pin_get_iectrl(pins[i].data); + tmp = readl(priv->base + UNIPHIER_PINCTRL_IECTRL); + tmp |= 1 << iectrl; + writel(tmp, priv->base + UNIPHIER_PINCTRL_IECTRL); + } + } +} + +static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin, + unsigned muxval) +{ + struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); + unsigned mux_bits = priv->socdata->mux_bits; + unsigned reg_stride = priv->socdata->reg_stride; + unsigned reg, reg_end, shift, mask; + u32 tmp; + + reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride; + reg_end = reg + reg_stride; + shift = pin * mux_bits % 32; + mask = (1U << mux_bits) - 1; + + /* + * If reg_stride is greater than 4, the MSB of each pinsel shall be + * stored in the offset+4. + */ + for (; reg < reg_end; reg += 4) { + tmp = readl(priv->base + reg); + tmp &= ~(mask << shift); + tmp |= (mask & muxval) << shift; + writel(tmp, priv->base + reg); + + muxval >>= mux_bits; + } + + if (priv->socdata->load_pinctrl) + writel(1, priv->base + UNIPHIER_PINCTRL_LOAD_PINMUX); + + /* some pins need input-enabling */ + uniphier_pinconf_input_enable(dev, pin); +} + +static int uniphier_pinmux_group_set(struct udevice *dev, + unsigned group_selector, + unsigned func_selector) +{ + struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); + const struct uniphier_pinctrl_group *grp = + &priv->socdata->groups[group_selector]; + int i; + + for (i = 0; i < grp->num_pins; i++) + uniphier_pinmux_set_one(dev, grp->pins[i], grp->muxvals[i]); + + return 0; +} + +const struct pinctrl_ops uniphier_pinctrl_ops = { + .get_groups_count = uniphier_pinctrl_get_groups_count, + .get_group_name = uniphier_pinctrl_get_group_name, + .get_functions_count = uniphier_pinmux_get_functions_count, + .get_function_name = uniphier_pinmux_get_function_name, + .pinmux_group_set = uniphier_pinmux_group_set, + .set_state = pinctrl_generic_set_state, +}; + +int uniphier_pinctrl_probe(struct udevice *dev, + struct uniphier_pinctrl_socdata *socdata) +{ + struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + fdt_size_t size; + + addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", + &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->base = map_sysmem(addr, size); + if (!priv->base) + return -ENOMEM; + + priv->socdata = socdata; + + return 0; +} + +int uniphier_pinctrl_remove(struct udevice *dev) +{ + struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); + + unmap_sysmem(priv->base); + + return 0; +} diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h new file mode 100644 index 0000000000..7eaec6a702 --- /dev/null +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h @@ -0,0 +1,113 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PINCTRL_UNIPHIER_H__ +#define __PINCTRL_UNIPHIER_H__ + +/* TODO: move this to include/linux/bug.h */ +#define BUILD_BUG_ON_ZERO(e) (sizeof(struct { int:-!!(e); })) + +#include +#include + +#define UNIPHIER_PINCTRL_PINMUX_BASE 0x0 +#define UNIPHIER_PINCTRL_LOAD_PINMUX 0x700 +#define UNIPHIER_PINCTRL_IECTRL 0xd00 + +#define UNIPHIER_PIN_ATTR_PACKED(iectrl) (iectrl) + +static inline unsigned int uniphier_pin_get_iectrl(unsigned long data) +{ + return data; +} + +/** + * struct uniphier_pinctrl_pin - pin data for UniPhier SoC + * + * @number: pin number + * @data: additional per-pin data + */ +struct uniphier_pinctrl_pin { + unsigned number; + unsigned long data; +}; + +/** + * struct uniphier_pinctrl_group - pin group data for UniPhier SoC + * + * @name: pin group name + * @pins: array of pins that belong to the group + * @num_pins: number of pins in the group + * @muxvals: array of values to be set to pinmux registers + */ +struct uniphier_pinctrl_group { + const char *name; + const unsigned *pins; + unsigned num_pins; + const unsigned *muxvals; +}; + +/** + * struct uniphier_pinctrl_socdata - SoC data for UniPhier pin controller + * + * @pins: array of pin data + * @pins_count: number of pin data + * @groups: array of pin group data + * @groups_count: number of pin group data + * @functions: array of pinmux function names + * @functions_count: number of pinmux functions + * @mux_bits: bit width of each pinmux register + * @reg_stride: stride of pinmux register address + * @load_pinctrl: if true, LOAD_PINMUX register must be set to one for new + * values in pinmux registers to become really effective + */ +struct uniphier_pinctrl_socdata { + const struct uniphier_pinctrl_pin *pins; + int pins_count; + const struct uniphier_pinctrl_group *groups; + int groups_count; + const char * const *functions; + int functions_count; + unsigned mux_bits; + unsigned reg_stride; + bool load_pinctrl; +}; + +#define UNIPHIER_PINCTRL_PIN(a, b) \ +{ \ + .number = a, \ + .data = UNIPHIER_PIN_ATTR_PACKED(b), \ +} + +#define UNIPHIER_PINCTRL_GROUP(grp) \ + { \ + .name = #grp, \ + .pins = grp##_pins, \ + .num_pins = ARRAY_SIZE(grp##_pins), \ + .muxvals = grp##_muxvals + \ + BUILD_BUG_ON_ZERO(ARRAY_SIZE(grp##_pins) != \ + ARRAY_SIZE(grp##_muxvals)), \ + } + +/** + * struct uniphier_pinctrl_priv - private data for UniPhier pinctrl driver + * + * @base: base address of the pinctrl device + * @socdata: SoC specific data + */ +struct uniphier_pinctrl_priv { + void __iomem *base; + struct uniphier_pinctrl_socdata *socdata; +}; + +extern const struct pinctrl_ops uniphier_pinctrl_ops; + +int uniphier_pinctrl_probe(struct udevice *dev, + struct uniphier_pinctrl_socdata *socdata); + +int uniphier_pinctrl_remove(struct udevice *dev); + +#endif /* __PINCTRL_UNIPHIER_H__ */ -- cgit v1.2.1 From e4410e820756891129f7c15f701c51956013804b Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 11 Sep 2015 20:17:33 +0900 Subject: pinctrl: uniphier: add UniPhier PH1-LD4 pinctrl driver Add pin configuration and pinmux support for UniPhier PH1-LD4 SoC. Signed-off-by: Masahiro Yamada --- drivers/pinctrl/uniphier/Kconfig | 6 ++ drivers/pinctrl/uniphier/Makefile | 2 + drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c | 133 +++++++++++++++++++++++++++++ 3 files changed, 141 insertions(+) create mode 100644 drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c (limited to 'drivers') diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig index 29a623dfc1..03593cdd8b 100644 --- a/drivers/pinctrl/uniphier/Kconfig +++ b/drivers/pinctrl/uniphier/Kconfig @@ -3,4 +3,10 @@ if ARCH_UNIPHIER config PINCTRL_UNIPHIER_CORE bool +config PINCTRL_UNIPHIER_PH1_LD4 + bool "UniPhier PH1-LD4 SoC pinctrl driver" + depends on MACH_PH1_LD4 + default y + select PINCTRL_UNIPHIER_CORE + endif diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile index 748aa1b4e4..b4bd042ac4 100644 --- a/drivers/pinctrl/uniphier/Makefile +++ b/drivers/pinctrl/uniphier/Makefile @@ -1 +1,3 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_CORE) += pinctrl-uniphier-core.o + +obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c b/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c new file mode 100644 index 0000000000..b3d47f0915 --- /dev/null +++ b/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include "pinctrl-uniphier.h" + +static const struct uniphier_pinctrl_pin ph1_ld4_pins[] = { + UNIPHIER_PINCTRL_PIN(53, 0), + UNIPHIER_PINCTRL_PIN(54, 0), + UNIPHIER_PINCTRL_PIN(55, 0), + UNIPHIER_PINCTRL_PIN(56, 0), + UNIPHIER_PINCTRL_PIN(67, 0), + UNIPHIER_PINCTRL_PIN(68, 0), + UNIPHIER_PINCTRL_PIN(69, 0), + UNIPHIER_PINCTRL_PIN(70, 0), + UNIPHIER_PINCTRL_PIN(85, 0), + UNIPHIER_PINCTRL_PIN(88, 0), + UNIPHIER_PINCTRL_PIN(156, 0), +}; + +static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27}; +static const unsigned emmc_muxvals[] = {0, 1, 1, 1, 1, 1, 1}; +static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31}; +static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1}; +static const unsigned i2c0_pins[] = {102, 103}; +static const unsigned i2c0_muxvals[] = {0, 0}; +static const unsigned i2c1_pins[] = {104, 105}; +static const unsigned i2c1_muxvals[] = {0, 0}; +static const unsigned i2c2_pins[] = {108, 109}; +static const unsigned i2c2_muxvals[] = {2, 2}; +static const unsigned i2c3_pins[] = {108, 109}; +static const unsigned i2c3_muxvals[] = {3, 3}; +static const unsigned nand_pins[] = {24, 25, 26, 27, 28, 29, 30, 31, 158, 159, + 160, 161, 162, 163, 164}; +static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}; +static const unsigned nand_cs1_pins[] = {22, 23}; +static const unsigned nand_cs1_muxvals[] = {0, 0}; +static const unsigned sd_pins[] = {44, 45, 46, 47, 48, 49, 50, 51, 52}; +static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned uart0_pins[] = {85, 88}; +static const unsigned uart0_muxvals[] = {1, 1}; +static const unsigned uart1_pins[] = {155, 156}; +static const unsigned uart1_muxvals[] = {13, 13}; +static const unsigned uart1b_pins[] = {69, 70}; +static const unsigned uart1b_muxvals[] = {23, 23}; +static const unsigned uart2_pins[] = {128, 129}; +static const unsigned uart2_muxvals[] = {13, 13}; +static const unsigned uart3_pins[] = {110, 111}; +static const unsigned uart3_muxvals[] = {1, 1}; +static const unsigned usb0_pins[] = {53, 54}; +static const unsigned usb0_muxvals[] = {0, 0}; +static const unsigned usb1_pins[] = {55, 56}; +static const unsigned usb1_muxvals[] = {0, 0}; +static const unsigned usb2_pins[] = {155, 156}; +static const unsigned usb2_muxvals[] = {4, 4}; +static const unsigned usb2b_pins[] = {67, 68}; +static const unsigned usb2b_muxvals[] = {23, 23}; + +static const struct uniphier_pinctrl_group ph1_ld4_groups[] = { + UNIPHIER_PINCTRL_GROUP(emmc), + UNIPHIER_PINCTRL_GROUP(emmc_dat8), + UNIPHIER_PINCTRL_GROUP(i2c0), + UNIPHIER_PINCTRL_GROUP(i2c1), + UNIPHIER_PINCTRL_GROUP(i2c2), + UNIPHIER_PINCTRL_GROUP(i2c3), + UNIPHIER_PINCTRL_GROUP(nand), + UNIPHIER_PINCTRL_GROUP(nand_cs1), + UNIPHIER_PINCTRL_GROUP(sd), + UNIPHIER_PINCTRL_GROUP(uart0), + UNIPHIER_PINCTRL_GROUP(uart1), + UNIPHIER_PINCTRL_GROUP(uart1b), + UNIPHIER_PINCTRL_GROUP(uart2), + UNIPHIER_PINCTRL_GROUP(uart3), + UNIPHIER_PINCTRL_GROUP(usb0), + UNIPHIER_PINCTRL_GROUP(usb1), + UNIPHIER_PINCTRL_GROUP(usb2), + UNIPHIER_PINCTRL_GROUP(usb2b), +}; + +static const char * const ph1_ld4_functions[] = { + "emmc", + "i2c0", + "i2c1", + "i2c2", + "i2c3", + "nand", + "sd", + "uart0", + "uart1", + "uart2", + "uart3", + "usb0", + "usb1", + "usb2", +}; + +static struct uniphier_pinctrl_socdata ph1_ld4_pinctrl_socdata = { + .pins = ph1_ld4_pins, + .pins_count = ARRAY_SIZE(ph1_ld4_pins), + .groups = ph1_ld4_groups, + .groups_count = ARRAY_SIZE(ph1_ld4_groups), + .functions = ph1_ld4_functions, + .functions_count = ARRAY_SIZE(ph1_ld4_functions), + .mux_bits = 8, + .reg_stride = 4, + .load_pinctrl = false, +}; + +static int ph1_ld4_pinctrl_probe(struct udevice *dev) +{ + return uniphier_pinctrl_probe(dev, &ph1_ld4_pinctrl_socdata); +} + +static const struct udevice_id ph1_ld4_pinctrl_match[] = { + { .compatible = "socionext,ph1-ld4-pinctrl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(ph1_ld4_pinctrl) = { + .name = "ph1-ld4-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(ph1_ld4_pinctrl_match), + .probe = ph1_ld4_pinctrl_probe, + .remove = uniphier_pinctrl_remove, + .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), + .ops = &uniphier_pinctrl_ops, +}; -- cgit v1.2.1 From a343812461d40dfe72622176c6581a9e2f673ea2 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 11 Sep 2015 20:17:34 +0900 Subject: pinctrl: uniphier: add UniPhier PH1-Pro4 pinctrl driver Add pin configuration and pinmux support for UniPhier PH1-Pro4 SoC. Signed-off-by: Masahiro Yamada --- drivers/pinctrl/uniphier/Kconfig | 6 ++ drivers/pinctrl/uniphier/Makefile | 1 + drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c | 130 ++++++++++++++++++++++++++++ 3 files changed, 137 insertions(+) create mode 100644 drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c (limited to 'drivers') diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig index 03593cdd8b..c417a9f4ea 100644 --- a/drivers/pinctrl/uniphier/Kconfig +++ b/drivers/pinctrl/uniphier/Kconfig @@ -9,4 +9,10 @@ config PINCTRL_UNIPHIER_PH1_LD4 default y select PINCTRL_UNIPHIER_CORE +config PINCTRL_UNIPHIER_PH1_PRO4 + bool "UniPhier PH1-Pro4 SoC pinctrl driver" + depends on MACH_PH1_PRO4 + default y + select PINCTRL_UNIPHIER_CORE + endif diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile index b4bd042ac4..b1b597e0dc 100644 --- a/drivers/pinctrl/uniphier/Makefile +++ b/drivers/pinctrl/uniphier/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_CORE) += pinctrl-uniphier-core.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o +obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c b/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c new file mode 100644 index 0000000000..b3eaf138f7 --- /dev/null +++ b/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include "pinctrl-uniphier.h" + +static const struct uniphier_pinctrl_pin ph1_pro4_pins[] = { +}; + +static const unsigned emmc_pins[] = {40, 41, 42, 43, 51, 52, 53}; +static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1}; +static const unsigned emmc_dat8_pins[] = {44, 45, 46, 47}; +static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1}; +static const unsigned i2c0_pins[] = {142, 143}; +static const unsigned i2c0_muxvals[] = {0, 0}; +static const unsigned i2c1_pins[] = {144, 145}; +static const unsigned i2c1_muxvals[] = {0, 0}; +static const unsigned i2c2_pins[] = {146, 147}; +static const unsigned i2c2_muxvals[] = {0, 0}; +static const unsigned i2c3_pins[] = {148, 149}; +static const unsigned i2c3_muxvals[] = {0, 0}; +static const unsigned i2c6_pins[] = {308, 309}; +static const unsigned i2c6_muxvals[] = {6, 6}; +static const unsigned nand_pins[] = {40, 41, 42, 43, 44, 45, 46, 47, 48, 49, + 50, 51, 52, 53, 54}; +static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}; +static const unsigned nand_cs1_pins[] = {131, 132}; +static const unsigned nand_cs1_muxvals[] = {1, 1}; +static const unsigned sd_pins[] = {150, 151, 152, 153, 154, 155, 156, 157, 158}; +static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned sd1_pins[] = {319, 320, 321, 322, 323, 324, 325, 326, + 327}; +static const unsigned sd1_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned uart0_pins[] = {127, 128}; +static const unsigned uart0_muxvals[] = {0, 0}; +static const unsigned uart1_pins[] = {129, 130}; +static const unsigned uart1_muxvals[] = {0, 0}; +static const unsigned uart2_pins[] = {131, 132}; +static const unsigned uart2_muxvals[] = {0, 0}; +static const unsigned uart3_pins[] = {88, 89}; +static const unsigned uart3_muxvals[] = {2, 2}; +static const unsigned usb0_pins[] = {180, 181}; +static const unsigned usb0_muxvals[] = {0, 0}; +static const unsigned usb1_pins[] = {182, 183}; +static const unsigned usb1_muxvals[] = {0, 0}; +static const unsigned usb2_pins[] = {184, 185}; +static const unsigned usb2_muxvals[] = {0, 0}; +static const unsigned usb3_pins[] = {186, 187}; +static const unsigned usb3_muxvals[] = {0, 0}; + +static const struct uniphier_pinctrl_group ph1_pro4_groups[] = { + UNIPHIER_PINCTRL_GROUP(emmc), + UNIPHIER_PINCTRL_GROUP(emmc_dat8), + UNIPHIER_PINCTRL_GROUP(i2c0), + UNIPHIER_PINCTRL_GROUP(i2c1), + UNIPHIER_PINCTRL_GROUP(i2c2), + UNIPHIER_PINCTRL_GROUP(i2c3), + UNIPHIER_PINCTRL_GROUP(i2c6), + UNIPHIER_PINCTRL_GROUP(nand), + UNIPHIER_PINCTRL_GROUP(nand_cs1), + UNIPHIER_PINCTRL_GROUP(sd), + UNIPHIER_PINCTRL_GROUP(sd1), + UNIPHIER_PINCTRL_GROUP(uart0), + UNIPHIER_PINCTRL_GROUP(uart1), + UNIPHIER_PINCTRL_GROUP(uart2), + UNIPHIER_PINCTRL_GROUP(uart3), + UNIPHIER_PINCTRL_GROUP(usb0), + UNIPHIER_PINCTRL_GROUP(usb1), + UNIPHIER_PINCTRL_GROUP(usb2), + UNIPHIER_PINCTRL_GROUP(usb3), +}; + +static const char * const ph1_pro4_functions[] = { + "emmc", + "i2c0", + "i2c1", + "i2c2", + "i2c3", + "i2c6", + "nand", + "sd", + "sd1", + "uart0", + "uart1", + "uart2", + "uart3", + "usb0", + "usb1", + "usb2", + "usb3", +}; + +static struct uniphier_pinctrl_socdata ph1_pro4_pinctrl_socdata = { + .pins = ph1_pro4_pins, + .pins_count = ARRAY_SIZE(ph1_pro4_pins), + .groups = ph1_pro4_groups, + .groups_count = ARRAY_SIZE(ph1_pro4_groups), + .functions = ph1_pro4_functions, + .functions_count = ARRAY_SIZE(ph1_pro4_functions), + .mux_bits = 4, + .reg_stride = 8, + .load_pinctrl = true, +}; + +static int ph1_pro4_pinctrl_probe(struct udevice *dev) +{ + return uniphier_pinctrl_probe(dev, &ph1_pro4_pinctrl_socdata); +} + +static const struct udevice_id ph1_pro4_pinctrl_match[] = { + { .compatible = "socionext,ph1-pro4-pinctrl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(ph1_pro4_pinctrl) = { + .name = "ph1-pro4-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(ph1_pro4_pinctrl_match), + .probe = ph1_pro4_pinctrl_probe, + .remove = uniphier_pinctrl_remove, + .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), + .ops = &uniphier_pinctrl_ops, + .flags = DM_FLAG_PRE_RELOC, +}; -- cgit v1.2.1 From 06b2ae5890fad1531965ae8ad844336e67fc9bb0 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 11 Sep 2015 20:17:35 +0900 Subject: pinctrl: uniphier: add UniPhier PH1-sLD8 pinctrl driver Add pin configuration and pinmux support for UniPhier PH1-sLD8 SoC. Signed-off-by: Masahiro Yamada --- drivers/pinctrl/uniphier/Kconfig | 6 ++ drivers/pinctrl/uniphier/Makefile | 1 + drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c | 141 ++++++++++++++++++++++++++++ 3 files changed, 148 insertions(+) create mode 100644 drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c (limited to 'drivers') diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig index c417a9f4ea..a156a28c28 100644 --- a/drivers/pinctrl/uniphier/Kconfig +++ b/drivers/pinctrl/uniphier/Kconfig @@ -15,4 +15,10 @@ config PINCTRL_UNIPHIER_PH1_PRO4 default y select PINCTRL_UNIPHIER_CORE +config PINCTRL_UNIPHIER_PH1_SLD8 + bool "UniPhier PH1-sLD8 SoC pinctrl driver" + depends on MACH_PH1_SLD8 + default y + select PINCTRL_UNIPHIER_CORE + endif diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile index b1b597e0dc..3349fff80a 100644 --- a/drivers/pinctrl/uniphier/Makefile +++ b/drivers/pinctrl/uniphier/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_CORE) += pinctrl-uniphier-core.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o +obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_SLD8) += pinctrl-ph1-sld8.o diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c b/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c new file mode 100644 index 0000000000..5fafdb6100 --- /dev/null +++ b/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include "pinctrl-uniphier.h" + +static const struct uniphier_pinctrl_pin ph1_sld8_pins[] = { + UNIPHIER_PINCTRL_PIN(32, 8), + UNIPHIER_PINCTRL_PIN(33, 8), + UNIPHIER_PINCTRL_PIN(34, 8), + UNIPHIER_PINCTRL_PIN(35, 8), + UNIPHIER_PINCTRL_PIN(36, 8), + UNIPHIER_PINCTRL_PIN(37, 8), + UNIPHIER_PINCTRL_PIN(38, 8), + UNIPHIER_PINCTRL_PIN(39, 8), + UNIPHIER_PINCTRL_PIN(40, 9), + UNIPHIER_PINCTRL_PIN(41, 0), + UNIPHIER_PINCTRL_PIN(42, 0), + UNIPHIER_PINCTRL_PIN(43, 0), + UNIPHIER_PINCTRL_PIN(44, 0), + UNIPHIER_PINCTRL_PIN(70, 0), + UNIPHIER_PINCTRL_PIN(71, 0), + UNIPHIER_PINCTRL_PIN(102, 10), + UNIPHIER_PINCTRL_PIN(103, 10), + UNIPHIER_PINCTRL_PIN(104, 11), + UNIPHIER_PINCTRL_PIN(105, 11), + UNIPHIER_PINCTRL_PIN(108, 13), + UNIPHIER_PINCTRL_PIN(109, 13), + UNIPHIER_PINCTRL_PIN(112, 0), + UNIPHIER_PINCTRL_PIN(113, 0), + UNIPHIER_PINCTRL_PIN(114, 0), + UNIPHIER_PINCTRL_PIN(115, 0), +}; + +static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27}; +static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1}; +static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31}; +static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1}; +static const unsigned i2c0_pins[] = {102, 103}; +static const unsigned i2c0_muxvals[] = {0, 0}; +static const unsigned i2c1_pins[] = {104, 105}; +static const unsigned i2c1_muxvals[] = {0, 0}; +static const unsigned i2c2_pins[] = {108, 109}; +static const unsigned i2c2_muxvals[] = {2, 2}; +static const unsigned i2c3_pins[] = {108, 109}; +static const unsigned i2c3_muxvals[] = {3, 3}; +static const unsigned nand_pins[] = {15, 16, 17, 18, 19, 20, 21, 24, 25, 26, + 27, 28, 29, 30, 31}; +static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}; +static const unsigned nand_cs1_pins[] = {22, 23}; +static const unsigned nand_cs1_muxvals[] = {0, 0}; +static const unsigned sd_pins[] = {32, 33, 34, 35, 36, 37, 38, 39, 40}; +static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned uart0_pins[] = {70, 71}; +static const unsigned uart0_muxvals[] = {3, 3}; +static const unsigned uart1_pins[] = {114, 115}; +static const unsigned uart1_muxvals[] = {0, 0}; +static const unsigned uart2_pins[] = {112, 113}; +static const unsigned uart2_muxvals[] = {1, 1}; +static const unsigned uart3_pins[] = {110, 111}; +static const unsigned uart3_muxvals[] = {1, 1}; +static const unsigned usb0_pins[] = {41, 42}; +static const unsigned usb0_muxvals[] = {0, 0}; +static const unsigned usb1_pins[] = {43, 44}; +static const unsigned usb1_muxvals[] = {0, 0}; +static const unsigned usb2_pins[] = {114, 115}; +static const unsigned usb2_muxvals[] = {1, 1}; + +static const struct uniphier_pinctrl_group ph1_sld8_groups[] = { + UNIPHIER_PINCTRL_GROUP(emmc), + UNIPHIER_PINCTRL_GROUP(emmc_dat8), + UNIPHIER_PINCTRL_GROUP(i2c0), + UNIPHIER_PINCTRL_GROUP(i2c1), + UNIPHIER_PINCTRL_GROUP(i2c2), + UNIPHIER_PINCTRL_GROUP(i2c3), + UNIPHIER_PINCTRL_GROUP(nand), + UNIPHIER_PINCTRL_GROUP(nand_cs1), + UNIPHIER_PINCTRL_GROUP(sd), + UNIPHIER_PINCTRL_GROUP(uart0), + UNIPHIER_PINCTRL_GROUP(uart1), + UNIPHIER_PINCTRL_GROUP(uart2), + UNIPHIER_PINCTRL_GROUP(uart3), + UNIPHIER_PINCTRL_GROUP(usb0), + UNIPHIER_PINCTRL_GROUP(usb1), + UNIPHIER_PINCTRL_GROUP(usb2), +}; + +static const char * const ph1_sld8_functions[] = { + "emmc", + "i2c0", + "i2c1", + "i2c2", + "i2c3", + "nand", + "sd", + "uart0", + "uart1", + "uart2", + "uart3", + "usb0", + "usb1", + "usb2", +}; + +static struct uniphier_pinctrl_socdata ph1_sld8_pinctrl_socdata = { + .pins = ph1_sld8_pins, + .pins_count = ARRAY_SIZE(ph1_sld8_pins), + .groups = ph1_sld8_groups, + .groups_count = ARRAY_SIZE(ph1_sld8_groups), + .functions = ph1_sld8_functions, + .functions_count = ARRAY_SIZE(ph1_sld8_functions), + .mux_bits = 8, + .reg_stride = 4, + .load_pinctrl = false, +}; + +static int ph1_sld8_pinctrl_probe(struct udevice *dev) +{ + return uniphier_pinctrl_probe(dev, &ph1_sld8_pinctrl_socdata); +} + +static const struct udevice_id ph1_sld8_pinctrl_match[] = { + { .compatible = "socionext,ph1-sld8-pinctrl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(ph1_sld8_pinctrl) = { + .name = "ph1-sld8-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(ph1_sld8_pinctrl_match), + .probe = ph1_sld8_pinctrl_probe, + .remove = uniphier_pinctrl_remove, + .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), + .ops = &uniphier_pinctrl_ops, +}; -- cgit v1.2.1 From b82ca82ed23759150f2e00e5299ce1583ba97dd6 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 11 Sep 2015 20:17:36 +0900 Subject: pinctrl: uniphier: add UniPhier PH1-Pro5 pinctrl driver Add pin configuration and pinmux support for UniPhier PH1-Pro5 SoC. Signed-off-by: Masahiro Yamada --- drivers/pinctrl/uniphier/Kconfig | 6 ++ drivers/pinctrl/uniphier/Makefile | 1 + drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c | 144 ++++++++++++++++++++++++++++ 3 files changed, 151 insertions(+) create mode 100644 drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c (limited to 'drivers') diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig index a156a28c28..9d3065db30 100644 --- a/drivers/pinctrl/uniphier/Kconfig +++ b/drivers/pinctrl/uniphier/Kconfig @@ -21,4 +21,10 @@ config PINCTRL_UNIPHIER_PH1_SLD8 default y select PINCTRL_UNIPHIER_CORE +config PINCTRL_UNIPHIER_PH1_PRO5 + bool "UniPhier PH1-Pro5 SoC pinctrl driver" + depends on MACH_PH1_PRO5 + default y + select PINCTRL_UNIPHIER_CORE + endif diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile index 3349fff80a..b0cd3e86bc 100644 --- a/drivers/pinctrl/uniphier/Makefile +++ b/drivers/pinctrl/uniphier/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_CORE) += pinctrl-uniphier-core.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_SLD8) += pinctrl-ph1-sld8.o +obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO5) += pinctrl-ph1-pro5.o diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c b/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c new file mode 100644 index 0000000000..3749250066 --- /dev/null +++ b/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include "pinctrl-uniphier.h" + +static const struct uniphier_pinctrl_pin ph1_pro5_pins[] = { + UNIPHIER_PINCTRL_PIN(47, 0), + UNIPHIER_PINCTRL_PIN(48, 0), + UNIPHIER_PINCTRL_PIN(49, 0), + UNIPHIER_PINCTRL_PIN(50, 0), + UNIPHIER_PINCTRL_PIN(53, 0), + UNIPHIER_PINCTRL_PIN(54, 0), + UNIPHIER_PINCTRL_PIN(87, 0), + UNIPHIER_PINCTRL_PIN(88, 0), + UNIPHIER_PINCTRL_PIN(101, 0), + UNIPHIER_PINCTRL_PIN(102, 0), +}; + +static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42}; +static const unsigned emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0}; +static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46}; +static const unsigned emmc_dat8_muxvals[] = {0, 0, 0, 0}; +static const unsigned i2c0_pins[] = {112, 113}; +static const unsigned i2c0_muxvals[] = {0, 0}; +static const unsigned i2c1_pins[] = {114, 115}; +static const unsigned i2c1_muxvals[] = {0, 0}; +static const unsigned i2c2_pins[] = {116, 117}; +static const unsigned i2c2_muxvals[] = {0, 0}; +static const unsigned i2c3_pins[] = {118, 119}; +static const unsigned i2c3_muxvals[] = {0, 0}; +static const unsigned i2c5_pins[] = {87, 88}; +static const unsigned i2c5_muxvals[] = {2, 2}; +static const unsigned i2c5b_pins[] = {196, 197}; +static const unsigned i2c5b_muxvals[] = {2, 2}; +static const unsigned i2c5c_pins[] = {215, 216}; +static const unsigned i2c5c_muxvals[] = {2, 2}; +static const unsigned i2c6_pins[] = {101, 102}; +static const unsigned i2c6_muxvals[] = {2, 2}; +static const unsigned nand_pins[] = {19, 20, 21, 22, 23, 24, 25, 28, 29, 30, + 31, 32, 33, 34, 35}; +static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}; +static const unsigned nand_cs1_pins[] = {26, 27}; +static const unsigned nand_cs1_muxvals[] = {0, 0}; +static const unsigned sd_pins[] = {250, 251, 252, 253, 254, 255, 256, 257, 258}; +static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned uart0_pins[] = {47, 48}; +static const unsigned uart0_muxvals[] = {0, 0}; +static const unsigned uart0b_pins[] = {227, 228}; +static const unsigned uart0b_muxvals[] = {3, 3}; +static const unsigned uart1_pins[] = {49, 50}; +static const unsigned uart1_muxvals[] = {0, 0}; +static const unsigned uart2_pins[] = {51, 52}; +static const unsigned uart2_muxvals[] = {0, 0}; +static const unsigned uart3_pins[] = {53, 54}; +static const unsigned uart3_muxvals[] = {0, 0}; +static const unsigned usb0_pins[] = {124, 125}; +static const unsigned usb0_muxvals[] = {0, 0}; +static const unsigned usb1_pins[] = {126, 127}; +static const unsigned usb1_muxvals[] = {0, 0}; +static const unsigned usb2_pins[] = {128, 129}; +static const unsigned usb2_muxvals[] = {0, 0}; + +static const struct uniphier_pinctrl_group ph1_pro5_groups[] = { + UNIPHIER_PINCTRL_GROUP(emmc), + UNIPHIER_PINCTRL_GROUP(emmc_dat8), + UNIPHIER_PINCTRL_GROUP(i2c0), + UNIPHIER_PINCTRL_GROUP(i2c1), + UNIPHIER_PINCTRL_GROUP(i2c2), + UNIPHIER_PINCTRL_GROUP(i2c3), + UNIPHIER_PINCTRL_GROUP(i2c5), + UNIPHIER_PINCTRL_GROUP(i2c5b), + UNIPHIER_PINCTRL_GROUP(i2c5c), + UNIPHIER_PINCTRL_GROUP(i2c6), + UNIPHIER_PINCTRL_GROUP(nand), + UNIPHIER_PINCTRL_GROUP(nand_cs1), + UNIPHIER_PINCTRL_GROUP(sd), + UNIPHIER_PINCTRL_GROUP(uart0), + UNIPHIER_PINCTRL_GROUP(uart0b), + UNIPHIER_PINCTRL_GROUP(uart1), + UNIPHIER_PINCTRL_GROUP(uart2), + UNIPHIER_PINCTRL_GROUP(uart3), + UNIPHIER_PINCTRL_GROUP(usb0), + UNIPHIER_PINCTRL_GROUP(usb1), + UNIPHIER_PINCTRL_GROUP(usb2), +}; + +static const char * const ph1_pro5_functions[] = { + "emmc", + "i2c0", + "i2c1", + "i2c2", + "i2c3", + "i2c5", + "i2c6", + "nand", + "sd", + "uart0", + "uart1", + "uart2", + "uart3", + "usb0", + "usb1", + "usb2", +}; + +static struct uniphier_pinctrl_socdata ph1_pro5_pinctrl_socdata = { + .pins = ph1_pro5_pins, + .pins_count = ARRAY_SIZE(ph1_pro5_pins), + .groups = ph1_pro5_groups, + .groups_count = ARRAY_SIZE(ph1_pro5_groups), + .functions = ph1_pro5_functions, + .functions_count = ARRAY_SIZE(ph1_pro5_functions), + .mux_bits = 4, + .reg_stride = 8, + .load_pinctrl = true, +}; + +static int ph1_pro5_pinctrl_probe(struct udevice *dev) +{ + return uniphier_pinctrl_probe(dev, &ph1_pro5_pinctrl_socdata); +} + +static const struct udevice_id ph1_pro5_pinctrl_match[] = { + { .compatible = "socionext,ph1-pro5-pinctrl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(ph1_pro5_pinctrl) = { + .name = "ph1-pro5-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(ph1_pro5_pinctrl_match), + .probe = ph1_pro5_pinctrl_probe, + .remove = uniphier_pinctrl_remove, + .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), + .ops = &uniphier_pinctrl_ops, + .flags = DM_FLAG_PRE_RELOC, +}; -- cgit v1.2.1 From 833de5fafb43df835f5a9d2a8b77c0ffbbde9cb0 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 11 Sep 2015 20:17:37 +0900 Subject: pinctrl: uniphier: add UniPhier ProXstream2 pinctrl driver Add pin configuration and pinmux support for UniPhier ProXstream2 SoC. Signed-off-by: Masahiro Yamada --- drivers/pinctrl/uniphier/Kconfig | 6 ++ drivers/pinctrl/uniphier/Makefile | 1 + drivers/pinctrl/uniphier/pinctrl-proxstream2.c | 140 +++++++++++++++++++++++++ 3 files changed, 147 insertions(+) create mode 100644 drivers/pinctrl/uniphier/pinctrl-proxstream2.c (limited to 'drivers') diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig index 9d3065db30..7f729b68a1 100644 --- a/drivers/pinctrl/uniphier/Kconfig +++ b/drivers/pinctrl/uniphier/Kconfig @@ -27,4 +27,10 @@ config PINCTRL_UNIPHIER_PH1_PRO5 default y select PINCTRL_UNIPHIER_CORE +config PINCTRL_UNIPHIER_PROXSTREAM2 + bool "UniPhier ProXstream2 SoC pinctrl driver" + depends on MACH_PROXSTREAM2 + default y + select PINCTRL_UNIPHIER_CORE + endif diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile index b0cd3e86bc..aed038c59f 100644 --- a/drivers/pinctrl/uniphier/Makefile +++ b/drivers/pinctrl/uniphier/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_SLD8) += pinctrl-ph1-sld8.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO5) += pinctrl-ph1-pro5.o +obj-$(CONFIG_PINCTRL_UNIPHIER_PROXSTREAM2) += pinctrl-proxstream2.o diff --git a/drivers/pinctrl/uniphier/pinctrl-proxstream2.c b/drivers/pinctrl/uniphier/pinctrl-proxstream2.c new file mode 100644 index 0000000000..2cca69d514 --- /dev/null +++ b/drivers/pinctrl/uniphier/pinctrl-proxstream2.c @@ -0,0 +1,140 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include "pinctrl-uniphier.h" + +static const struct uniphier_pinctrl_pin proxstream2_pins[] = { + UNIPHIER_PINCTRL_PIN(113, 0), + UNIPHIER_PINCTRL_PIN(114, 0), + UNIPHIER_PINCTRL_PIN(115, 0), + UNIPHIER_PINCTRL_PIN(116, 0), +}; + +static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42}; +static const unsigned emmc_muxvals[] = {9, 9, 9, 9, 9, 9, 9}; +static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46}; +static const unsigned emmc_dat8_muxvals[] = {9, 9, 9, 9}; +static const unsigned i2c0_pins[] = {109, 110}; +static const unsigned i2c0_muxvals[] = {8, 8}; +static const unsigned i2c1_pins[] = {111, 112}; +static const unsigned i2c1_muxvals[] = {8, 8}; +static const unsigned i2c2_pins[] = {171, 172}; +static const unsigned i2c2_muxvals[] = {8, 8}; +static const unsigned i2c3_pins[] = {159, 160}; +static const unsigned i2c3_muxvals[] = {8, 8}; +static const unsigned i2c5_pins[] = {183, 184}; +static const unsigned i2c5_muxvals[] = {11, 11}; +static const unsigned i2c6_pins[] = {185, 186}; +static const unsigned i2c6_muxvals[] = {11, 11}; +static const unsigned nand_pins[] = {30, 31, 32, 33, 34, 35, 36, 39, 40, 41, + 42, 43, 44, 45, 46}; +static const unsigned nand_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 8, 8}; +static const unsigned nand_cs1_pins[] = {37, 38}; +static const unsigned nand_cs1_muxvals[] = {8, 8}; +static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55}; +static const unsigned sd_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8}; +static const unsigned uart0_pins[] = {217, 218}; +static const unsigned uart0_muxvals[] = {8, 8}; +static const unsigned uart0b_pins[] = {179, 180}; +static const unsigned uart0b_muxvals[] = {10, 10}; +static const unsigned uart1_pins[] = {115, 116}; +static const unsigned uart1_muxvals[] = {8, 8}; +static const unsigned uart2_pins[] = {113, 114}; +static const unsigned uart2_muxvals[] = {8, 8}; +static const unsigned uart3_pins[] = {219, 220}; +static const unsigned uart3_muxvals[] = {8, 8}; +static const unsigned uart3b_pins[] = {181, 182}; +static const unsigned uart3b_muxvals[] = {10, 10}; +static const unsigned usb0_pins[] = {56, 57}; +static const unsigned usb0_muxvals[] = {8, 8}; +static const unsigned usb1_pins[] = {58, 59}; +static const unsigned usb1_muxvals[] = {8, 8}; +static const unsigned usb2_pins[] = {60, 61}; +static const unsigned usb2_muxvals[] = {8, 8}; +static const unsigned usb3_pins[] = {62, 63}; +static const unsigned usb3_muxvals[] = {8, 8}; + +static const struct uniphier_pinctrl_group proxstream2_groups[] = { + UNIPHIER_PINCTRL_GROUP(emmc), + UNIPHIER_PINCTRL_GROUP(emmc_dat8), + UNIPHIER_PINCTRL_GROUP(i2c0), + UNIPHIER_PINCTRL_GROUP(i2c1), + UNIPHIER_PINCTRL_GROUP(i2c2), + UNIPHIER_PINCTRL_GROUP(i2c3), + UNIPHIER_PINCTRL_GROUP(i2c5), + UNIPHIER_PINCTRL_GROUP(i2c6), + UNIPHIER_PINCTRL_GROUP(nand), + UNIPHIER_PINCTRL_GROUP(nand_cs1), + UNIPHIER_PINCTRL_GROUP(sd), + UNIPHIER_PINCTRL_GROUP(uart0), + UNIPHIER_PINCTRL_GROUP(uart0b), + UNIPHIER_PINCTRL_GROUP(uart1), + UNIPHIER_PINCTRL_GROUP(uart2), + UNIPHIER_PINCTRL_GROUP(uart3), + UNIPHIER_PINCTRL_GROUP(uart3b), + UNIPHIER_PINCTRL_GROUP(usb0), + UNIPHIER_PINCTRL_GROUP(usb1), + UNIPHIER_PINCTRL_GROUP(usb2), + UNIPHIER_PINCTRL_GROUP(usb3), +}; + +static const char * const proxstream2_functions[] = { + "emmc", + "i2c0", + "i2c1", + "i2c2", + "i2c3", + "i2c5", + "i2c6", + "nand", + "sd", + "uart0", + "uart0b", + "uart1", + "uart2", + "uart3", + "uart3b", + "usb0", + "usb1", + "usb2", + "usb3", +}; + +static struct uniphier_pinctrl_socdata proxstream2_pinctrl_socdata = { + .pins = proxstream2_pins, + .pins_count = ARRAY_SIZE(proxstream2_pins), + .groups = proxstream2_groups, + .groups_count = ARRAY_SIZE(proxstream2_groups), + .functions = proxstream2_functions, + .functions_count = ARRAY_SIZE(proxstream2_functions), + .mux_bits = 8, + .reg_stride = 4, + .load_pinctrl = false, +}; + +static int proxstream2_pinctrl_probe(struct udevice *dev) +{ + return uniphier_pinctrl_probe(dev, &proxstream2_pinctrl_socdata); +} + +static const struct udevice_id proxstream2_pinctrl_match[] = { + { .compatible = "socionext,proxstream2-pinctrl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(proxstream2_pinctrl) = { + .name = "proxstream2-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(proxstream2_pinctrl_match), + .probe = proxstream2_pinctrl_probe, + .remove = uniphier_pinctrl_remove, + .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), + .ops = &uniphier_pinctrl_ops, +}; -- cgit v1.2.1 From 080b7a5b4522d4a8fcda4a4e0c34b757ac99bdae Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 11 Sep 2015 20:17:38 +0900 Subject: pinctrl: uniphier: add UniPhier PH1-LD6b pinctrl driver Add pin configuration and pinmux support for UniPhier PH1-LD6b SoC. Signed-off-by: Masahiro Yamada --- drivers/pinctrl/uniphier/Kconfig | 6 ++ drivers/pinctrl/uniphier/Makefile | 1 + drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c | 133 ++++++++++++++++++++++++++++ 3 files changed, 140 insertions(+) create mode 100644 drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c (limited to 'drivers') diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig index 7f729b68a1..757edce178 100644 --- a/drivers/pinctrl/uniphier/Kconfig +++ b/drivers/pinctrl/uniphier/Kconfig @@ -33,4 +33,10 @@ config PINCTRL_UNIPHIER_PROXSTREAM2 default y select PINCTRL_UNIPHIER_CORE +config PINCTRL_UNIPHIER_PH1_LD6B + bool "UniPhier PH1-LD6b SoC pinctrl driver" + depends on MACH_PH1_LD6B + default y + select PINCTRL_UNIPHIER_CORE + endif diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile index aed038c59f..e215b10972 100644 --- a/drivers/pinctrl/uniphier/Makefile +++ b/drivers/pinctrl/uniphier/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_SLD8) += pinctrl-ph1-sld8.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO5) += pinctrl-ph1-pro5.o obj-$(CONFIG_PINCTRL_UNIPHIER_PROXSTREAM2) += pinctrl-proxstream2.o +obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD6B) += pinctrl-ph1-ld6b.o diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c new file mode 100644 index 0000000000..8703a215e4 --- /dev/null +++ b/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include "pinctrl-uniphier.h" + +static const struct uniphier_pinctrl_pin ph1_ld6b_pins[] = { + UNIPHIER_PINCTRL_PIN(113, 0), + UNIPHIER_PINCTRL_PIN(114, 0), + UNIPHIER_PINCTRL_PIN(115, 0), + UNIPHIER_PINCTRL_PIN(116, 0), + UNIPHIER_PINCTRL_PIN(217, 0), + UNIPHIER_PINCTRL_PIN(218, 0), + UNIPHIER_PINCTRL_PIN(219, 0), + UNIPHIER_PINCTRL_PIN(220, 0), +}; + +static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42}; +static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1}; +static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46}; +static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1}; +static const unsigned i2c0_pins[] = {109, 110}; +static const unsigned i2c0_muxvals[] = {0, 0}; +static const unsigned i2c1_pins[] = {111, 112}; +static const unsigned i2c1_muxvals[] = {0, 0}; +static const unsigned i2c2_pins[] = {115, 116}; +static const unsigned i2c2_muxvals[] = {1, 1}; +static const unsigned i2c3_pins[] = {118, 119}; +static const unsigned i2c3_muxvals[] = {1, 1}; +static const unsigned nand_pins[] = {30, 31, 32, 33, 34, 35, 36, 39, 40, 41, + 42, 43, 44, 45, 46}; +static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}; +static const unsigned nand_cs1_pins[] = {37, 38}; +static const unsigned nand_cs1_muxvals[] = {0, 0}; +static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55}; +static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned uart0_pins[] = {135, 136}; +static const unsigned uart0_muxvals[] = {3, 3}; +static const unsigned uart0b_pins[] = {11, 12}; +static const unsigned uart0b_muxvals[] = {2, 2}; +static const unsigned uart1_pins[] = {115, 116}; +static const unsigned uart1_muxvals[] = {0, 0}; +static const unsigned uart1b_pins[] = {113, 114}; +static const unsigned uart1b_muxvals[] = {1, 1}; +static const unsigned uart2_pins[] = {113, 114}; +static const unsigned uart2_muxvals[] = {2, 2}; +static const unsigned uart2b_pins[] = {86, 87}; +static const unsigned uart2b_muxvals[] = {1, 1}; +static const unsigned usb0_pins[] = {56, 57}; +static const unsigned usb0_muxvals[] = {0, 0}; +static const unsigned usb1_pins[] = {58, 59}; +static const unsigned usb1_muxvals[] = {0, 0}; +static const unsigned usb2_pins[] = {60, 61}; +static const unsigned usb2_muxvals[] = {0, 0}; +static const unsigned usb3_pins[] = {62, 63}; +static const unsigned usb3_muxvals[] = {0, 0}; + +static const struct uniphier_pinctrl_group ph1_ld6b_groups[] = { + UNIPHIER_PINCTRL_GROUP(emmc), + UNIPHIER_PINCTRL_GROUP(emmc_dat8), + UNIPHIER_PINCTRL_GROUP(i2c0), + UNIPHIER_PINCTRL_GROUP(i2c1), + UNIPHIER_PINCTRL_GROUP(i2c2), + UNIPHIER_PINCTRL_GROUP(i2c3), + UNIPHIER_PINCTRL_GROUP(nand), + UNIPHIER_PINCTRL_GROUP(nand_cs1), + UNIPHIER_PINCTRL_GROUP(sd), + UNIPHIER_PINCTRL_GROUP(uart0), + UNIPHIER_PINCTRL_GROUP(uart0b), + UNIPHIER_PINCTRL_GROUP(uart1), + UNIPHIER_PINCTRL_GROUP(uart1b), + UNIPHIER_PINCTRL_GROUP(uart2), + UNIPHIER_PINCTRL_GROUP(uart2b), + UNIPHIER_PINCTRL_GROUP(usb0), + UNIPHIER_PINCTRL_GROUP(usb1), + UNIPHIER_PINCTRL_GROUP(usb2), + UNIPHIER_PINCTRL_GROUP(usb3), +}; + +static const char * const ph1_ld6b_functions[] = { + "emmc", + "i2c0", + "i2c1", + "i2c2", + "i2c3", + "nand", + "sd", + "uart0", + "uart1", + "uart2", + "usb0", + "usb1", + "usb2", + "usb3", +}; + +static struct uniphier_pinctrl_socdata ph1_ld6b_pinctrl_socdata = { + .pins = ph1_ld6b_pins, + .pins_count = ARRAY_SIZE(ph1_ld6b_pins), + .groups = ph1_ld6b_groups, + .groups_count = ARRAY_SIZE(ph1_ld6b_groups), + .functions = ph1_ld6b_functions, + .functions_count = ARRAY_SIZE(ph1_ld6b_functions), + .mux_bits = 8, + .reg_stride = 4, + .load_pinctrl = false, +}; + +static int ph1_ld6b_pinctrl_probe(struct udevice *dev) +{ + return uniphier_pinctrl_probe(dev, &ph1_ld6b_pinctrl_socdata); +} + +static const struct udevice_id ph1_ld6b_pinctrl_match[] = { + { .compatible = "socionext,ph1-ld6b-pinctrl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(ph1_ld6b_pinctrl) = { + .name = "ph1-ld6b-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(ph1_ld6b_pinctrl_match), + .probe = ph1_ld6b_pinctrl_probe, + .remove = uniphier_pinctrl_remove, + .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), + .ops = &uniphier_pinctrl_ops, +}; -- cgit v1.2.1 From 8497ccc4c23beae38130489d85c97ae38058f20b Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 22 Sep 2015 00:27:34 +0900 Subject: ARM: uniphier: rename CONFIG_MACH_* to CONFIG_ARCH_UNIPHIER_* I want these prefixed with CONFIG_ARCH_UNIPHIER_ to clarify they belong to UniPhier SoC family. Signed-off-by: Masahiro Yamada --- drivers/pinctrl/uniphier/Kconfig | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig index 757edce178..2ff616e946 100644 --- a/drivers/pinctrl/uniphier/Kconfig +++ b/drivers/pinctrl/uniphier/Kconfig @@ -5,37 +5,37 @@ config PINCTRL_UNIPHIER_CORE config PINCTRL_UNIPHIER_PH1_LD4 bool "UniPhier PH1-LD4 SoC pinctrl driver" - depends on MACH_PH1_LD4 + depends on ARCH_UNIPHIER_PH1_LD4 default y select PINCTRL_UNIPHIER_CORE config PINCTRL_UNIPHIER_PH1_PRO4 bool "UniPhier PH1-Pro4 SoC pinctrl driver" - depends on MACH_PH1_PRO4 + depends on ARCH_UNIPHIER_PH1_PRO4 default y select PINCTRL_UNIPHIER_CORE config PINCTRL_UNIPHIER_PH1_SLD8 bool "UniPhier PH1-sLD8 SoC pinctrl driver" - depends on MACH_PH1_SLD8 + depends on ARCH_UNIPHIER_PH1_SLD8 default y select PINCTRL_UNIPHIER_CORE config PINCTRL_UNIPHIER_PH1_PRO5 bool "UniPhier PH1-Pro5 SoC pinctrl driver" - depends on MACH_PH1_PRO5 + depends on ARCH_UNIPHIER_PH1_PRO5 default y select PINCTRL_UNIPHIER_CORE config PINCTRL_UNIPHIER_PROXSTREAM2 bool "UniPhier ProXstream2 SoC pinctrl driver" - depends on MACH_PROXSTREAM2 + depends on ARCH_UNIPHIER_PROXSTREAM2 default y select PINCTRL_UNIPHIER_CORE config PINCTRL_UNIPHIER_PH1_LD6B bool "UniPhier PH1-LD6b SoC pinctrl driver" - depends on MACH_PH1_LD6B + depends on ARCH_UNIPHIER_PH1_LD6B default y select PINCTRL_UNIPHIER_CORE -- cgit v1.2.1