From af523a0d56b272bfd7d2a7ee4eccf07c7bb9529e Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Wed, 11 Nov 2015 17:58:34 +0800 Subject: pci/layerscape: add support for LS1043A PCIe LUT register access The endian and base address of PEX LUT register region is different between Chassis 2 and Chassis 3, so move the base address definition to chassis specific header file and add pex_lut_* functions to access LUT register. Signed-off-by: Mingkai Hu Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- drivers/pci/pcie_layerscape.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'drivers/pci/pcie_layerscape.c') diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index c1e3627c50..58e88ae45e 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -11,8 +11,9 @@ #include #include #include -#ifdef CONFIG_FSL_LAYERSCAPE +#ifndef CONFIG_LS102XA #include +#include #endif #ifndef CONFIG_SYS_PCI_MEMORY_BUS @@ -57,11 +58,6 @@ #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) #define PCIE_ATU_UPPER_TARGET 0x91C -/* LUT registers */ -#define PCIE_LUT_BASE 0x80000 -#define PCIE_LUT_LCTRL0 0x7F8 -#define PCIE_LUT_DBG 0x7FC - #define PCIE_DBI_RO_WR_EN 0x8bc #define PCIE_LINK_CAP 0x7c @@ -162,7 +158,7 @@ static int ls_pcie_link_state(struct ls_pcie *pcie) { u32 state; - state = readl(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) & + state = pex_lut_in32(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) & LTSSM_STATE_MASK; if (state < LTSSM_PCIE_L0) { debug("....PCIe link error. LTSSM=0x%02x.\n", state); @@ -466,16 +462,20 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct ls_pcie_info *info) for (pf = 0; pf < PCIE_PF_NUM; pf++) { for (vf = 0; vf <= PCIE_VF_NUM; vf++) { +#ifndef CONFIG_LS102XA writel(PCIE_LCTRL0_VAL(pf, vf), pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0); +#endif ls_pcie_ep_setup_bars(pcie->dbi); ls_pcie_ep_setup_atu(pcie, info); } } /* Disable CFG2 */ +#ifndef CONFIG_LS102XA writel(0, pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0); +#endif } else { ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE); ls_pcie_ep_setup_atu(pcie, info); -- cgit v1.2.1