From 1ff4f321b69950acca1b06daed89d872a52a337c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 18 Jan 2016 20:19:18 -0700 Subject: dm: x86: Add a driver for Intel PCH7 At some point we may need to distinguish between different types of PCHs, but for existing supported platforms we only need to worry about version 7 and version 9 bridges. Add a driver for the PCH7. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/pch/pch7.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 drivers/pch/pch7.c (limited to 'drivers/pch/pch7.c') diff --git a/drivers/pch/pch7.c b/drivers/pch/pch7.c new file mode 100644 index 0000000000..ef724221c2 --- /dev/null +++ b/drivers/pch/pch7.c @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define BIOS_CTRL 0xd8 + +static int pch7_get_sbase(struct udevice *dev, ulong *sbasep) +{ + u32 rcba; + + dm_pci_read_config32(dev, PCH_RCBA, &rcba); + /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */ + rcba = rcba & 0xffffc000; + *sbasep = rcba + 0x3020; + + return 0; +} + +static enum pch_version pch7_get_version(struct udevice *dev) +{ + return PCHV_7; +} + +static int pch7_set_spi_protect(struct udevice *dev, bool protect) +{ + uint8_t bios_cntl; + + /* Adjust the BIOS write protect to dis/allow write commands */ + dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl); + if (protect) + bios_cntl &= ~BIOS_CTRL_BIOSWE; + else + bios_cntl |= BIOS_CTRL_BIOSWE; + dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl); + + return 0; +} + +static const struct pch_ops pch7_ops = { + .get_sbase = pch7_get_sbase, + .get_version = pch7_get_version, + .set_spi_protect = pch7_set_spi_protect, +}; + +static const struct udevice_id pch7_ids[] = { + { .compatible = "intel,pch7" }, + { } +}; + +U_BOOT_DRIVER(pch7_drv) = { + .name = "intel-pch7", + .id = UCLASS_PCH, + .of_match = pch7_ids, + .ops = &pch7_ops, +}; -- cgit v1.2.1