From e5e7c747a0d591116f3418b071d2bb3629eafe56 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sat, 15 Aug 2015 23:06:56 +0530 Subject: doc: device-tree-bindings: spi: Add zynq qspi info Added device-tree-binding information for zynq qspi controller driver. Signed-off-by: Jagan Teki Cc: Simon Glass Cc: Siva Durga Prasad Paladugu Acked-by: Michal Simek Tested-by: Jagan Teki --- doc/device-tree-bindings/spi/spi-zynq-qspi.txt | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 doc/device-tree-bindings/spi/spi-zynq-qspi.txt (limited to 'doc') diff --git a/doc/device-tree-bindings/spi/spi-zynq-qspi.txt b/doc/device-tree-bindings/spi/spi-zynq-qspi.txt new file mode 100644 index 0000000000..47472fdb8c --- /dev/null +++ b/doc/device-tree-bindings/spi/spi-zynq-qspi.txt @@ -0,0 +1,26 @@ +Xilinx Zynq QSPI controller Device Tree Bindings +------------------------------------------------- + +Required properties: +- compatible : Should be "xlnx,zynq-qspi-1.0". +- reg : Physical base address and size of QSPI registers map. +- interrupts : Property with a value describing the interrupt + number. +- interrupt-parent : Must be core interrupt controller +- clock-names : List of input clock names - "ref_clk", "pclk" + (See clock bindings for details). +- clocks : Clock phandles (see clock bindings for details). + +Optional properties: +- num-cs : Number of chip selects used. + +Example: + qspi@e000d000 { + compatible = "xlnx,zynq-qspi-1.0"; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 10>, <&clkc 43>; + interrupt-parent = <&intc>; + interrupts = <0 19 4>; + num-cs = <1>; + reg = <0xe000d000 0x1000>; + } ; -- cgit v1.2.1