From a8a8fc9ceea8430224c8c0ac932a75c029a1e225 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sat, 27 Jun 2015 00:51:33 +0530 Subject: dts: zynq: Add zynq spi controller nodes This patch adds zynq spi controller nodes in zynq-7000.dtsi. Signed-off-by: Jagan Teki Acked-by: Simon Glass Cc: Michal Simek Cc: Siva Durga Prasad Paladugu Tested-by: Jagan Teki --- doc/device-tree-bindings/spi/spi-zynq.txt | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 doc/device-tree-bindings/spi/spi-zynq.txt (limited to 'doc/device-tree-bindings') diff --git a/doc/device-tree-bindings/spi/spi-zynq.txt b/doc/device-tree-bindings/spi/spi-zynq.txt new file mode 100644 index 0000000000..a7c275717b --- /dev/null +++ b/doc/device-tree-bindings/spi/spi-zynq.txt @@ -0,0 +1,27 @@ +Zynq SPI controller Device Tree Bindings +---------------------------------------- + +Required properties: +- compatible : Should be "xlnx,spi-zynq". +- reg : Physical base address and size of SPI registers map. +- status : Status will be disabled in dtsi and enabled in required dts. +- interrupt-parent : Must be core interrupt controller. +- interrupts : Property with a value describing the interrupt + number. +- clocks : Clock phandles (see clock bindings for details). +- clock-names : List of input clock names - "ref_clk", "pclk" + (See clock bindings for details). + +Example: + + spi@e0006000 { + compatible = "xlnx,zynq-spi"; + reg = <0xe0006000 0x1000>; + status = "disabled"; + interrupt-parent = <&intc>; + interrupts = <0 26 4>; + clocks = <&clkc 25>, <&clkc 34>; + clock-names = "ref_clk", "pclk"; + #address-cells = <1>; + #size-cells = <0>; + } ; -- cgit v1.2.1