From 6fbf261f8df294e589cfadebebe5468e3c0f29e9 Mon Sep 17 00:00:00 2001
From: Xie Xiaobo <r63061@freescale.com>
Date: Fri, 9 Mar 2007 19:08:25 +0800
Subject: Fix two bugs for MPC83xx DDR2 controller SPD Init

There are a few bugs in the cpu/mpc83xx/spd_sdram.c
the first bug is that the picos_to_clk routine introduces a huge
rounding error in 83xx.
the second bug is that the mode register write recovery field is
tWR-1, not tWR >> 1.
---
 cpu/mpc83xx/spd_sdram.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'cpu')

diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index d9b8753ca0..41a1f1fc7b 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -58,8 +58,8 @@ picos_to_clk(int picos)
 	int clks;
 
 	ddr_bus_clk = gd->ddr_clk >> 1;
-	clks = picos / ((1000000000 / ddr_bus_clk) * 1000);
-	if (picos % ((1000000000 / ddr_bus_clk) * 1000) != 0)
+	clks = picos / (1000000000 / (ddr_bus_clk / 1000));
+	if (picos % (1000000000 / (ddr_bus_clk / 1000)) != 0)
 		clks++;
 
 	return clks;
@@ -624,7 +624,7 @@ long int spd_sdram()
 			 | (1 << (16 + 10))             /* DQS Differential disable */
 			 | (add_lat << (16 + 3))        /* Additive Latency in EMRS1 */
 			 | (mode_odt_enable << 16)      /* ODT Enable in EMRS1 */
-			 | ((twr_clk >> 1) << 9)        /* Write Recovery Autopre */
+			 | ((twr_clk - 1) << 9)         /* Write Recovery Autopre */
 			 | (caslat << 4)                /* caslat */
 			 | (burstlen << 0)              /* Burst length */
 			);
-- 
cgit v1.2.1


From 0643631aa1036cd746bf5d15f5a34bc7bc01ea4f Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Sat, 21 Apr 2007 21:02:40 +0200
Subject: 16bit read/write little endian

---
 cpu/microblaze/start.S | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

(limited to 'cpu')

diff --git a/cpu/microblaze/start.S b/cpu/microblaze/start.S
index 29481af9ae..453815818d 100644
--- a/cpu/microblaze/start.S
+++ b/cpu/microblaze/start.S
@@ -117,3 +117,36 @@ clear_bss:
 3:	/* jumping to board_init */
 	brai	board_init
 1:	bri	1b
+
+/*
+ * Read 16bit little endian
+ */
+	.text
+	.global	in16
+	.ent	in16
+	.align	2
+in16:	lhu	r3, r0, r5
+	bslli	r4, r3, 8
+	bsrli	r3, r3, 8
+	andi	r4, r4, 0xffff
+	or	r3, r3, r4
+	rtsd	r15, 8
+	sext16	r3, r3
+	.end	in16
+
+/*
+ * Write 16bit little endian
+ * first parameter(r5) - address, second(r6) - short value
+ */
+	.text
+	.global	out16
+	.ent	out16
+	.align	2
+out16:	bslli	r3, r6, 8
+	bsrli	r6, r6, 8
+	andi	r3, r3, 0xffff
+	or	r3, r3, r6
+	sh	r3, r0, r5
+	rtsd	r15, 8
+	or	r0, r0, r0
+	.end	out16
-- 
cgit v1.2.1


From a35b0c4950d84cf9e3a9e32b916135956d1ac636 Mon Sep 17 00:00:00 2001
From: Scott Wood <scottwood@freescale.com>
Date: Mon, 16 Apr 2007 14:34:15 -0500
Subject: mpc83xx: Recognize SPR values for MPC8311 and MPC8313.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 cpu/mpc83xx/cpu.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

(limited to 'cpu')

diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index e934ba638f..d569c49727 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -124,6 +124,18 @@ int checkcpu(void)
 	case SPR_8321_REV11:
 		puts("MPC8321, ");
 		break;
+	case SPR_8311_REV10:
+		puts("MPC8311, ");
+		break;
+	case SPR_8311E_REV10:
+		puts("MPC8311E, ");
+		break;
+	case SPR_8313_REV10:
+		puts("MPC8313, ");
+		break;
+	case SPR_8313E_REV10:
+		puts("MPC8313E, ");
+		break;
 	default:
 		puts("Rev: Unknown revision number.\nWarning: Unsupported cpu revision!\n");
 		return 0;
-- 
cgit v1.2.1


From 95e7ef897e54591e615fc1b458b74c286fe1fb06 Mon Sep 17 00:00:00 2001
From: Scott Wood <scottwood@freescale.com>
Date: Mon, 16 Apr 2007 14:34:16 -0500
Subject: mpc83xx: Change PVR_83xx to PVR_E300C1-3, and update checkcpu().

Rather than misleadingly define PVR_83xx as the specific type of 83xx
being built for, the PVR of each core revision is defined. checkcpu() now
prints the core that it detects, rather than aborting if it doesn't find
what it thinks it wants.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 cpu/mpc83xx/cpu.c | 21 +++++++++++++++++----
 1 file changed, 17 insertions(+), 4 deletions(-)

(limited to 'cpu')

diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index d569c49727..332afaad9f 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -52,13 +52,26 @@ int checkcpu(void)
 
 	immr = (immap_t *)CFG_IMMR;
 
-	if ((pvr & 0xFFFF0000) != PVR_83xx) {
-		puts("Not MPC83xx Family!!!\n");
-		return -1;
+	puts("CPU: ");
+
+	switch (pvr & 0xffff0000) {
+		case PVR_E300C1:
+			printf("e300c1, ");
+			break;
+
+		case PVR_E300C2:
+			printf("e300c2, ");
+			break;
+
+		case PVR_E300C3:
+			printf("e300c3, ");
+			break;
+
+		default:
+			printf("Unknown core, ");
 	}
 
 	spridr = immr->sysconf.spridr;
-	puts("CPU: ");
 	switch(spridr) {
 	case SPR_8349E_REV10:
 	case SPR_8349E_REV11:
-- 
cgit v1.2.1


From 7c98e5193e93df6b9b651851d54b638a61ebb0ea Mon Sep 17 00:00:00 2001
From: Scott Wood <scottwood@freescale.com>
Date: Mon, 16 Apr 2007 14:34:19 -0500
Subject: mpc83xx: Add 831x support to speed.c.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 cpu/mpc83xx/speed.c | 68 +++++++++++++++++++++++++++++++++--------------------
 1 file changed, 42 insertions(+), 26 deletions(-)

(limited to 'cpu')

diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index c75993059e..1a440310e5 100644
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -99,11 +99,13 @@ int get_clocks(void)
 	u32 lcrr;
 
 	u32 csb_clk;
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X)
 	u32 tsec1_clk;
 	u32 tsec2_clk;
-	u32 usbmph_clk;
 	u32 usbdr_clk;
+#endif
+#ifdef CONFIG_MPC834X
+	u32 usbmph_clk;
 #endif
 	u32 core_clk;
 	u32 i2c1_clk;
@@ -148,7 +150,7 @@ int get_clocks(void)
 
 	sccr = im->clk.sccr;
 
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X)
 	switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
 	case 0:
 		tsec1_clk = 0;
@@ -167,6 +169,26 @@ int get_clocks(void)
 		return -4;
 	}
 
+	switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
+	case 0:
+		usbdr_clk = 0;
+		break;
+	case 1:
+		usbdr_clk = csb_clk;
+		break;
+	case 2:
+		usbdr_clk = csb_clk / 2;
+		break;
+	case 3:
+		usbdr_clk = csb_clk / 3;
+		break;
+	default:
+		/* unkown SCCR_USBDRCM value */
+		return -8;
+	}
+#endif
+
+#if defined(CONFIG_MPC834X)
 	switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
 	case 0:
 		tsec2_clk = 0;
@@ -205,24 +227,6 @@ int get_clocks(void)
 		return -7;
 	}
 
-	switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
-	case 0:
-		usbdr_clk = 0;
-		break;
-	case 1:
-		usbdr_clk = csb_clk;
-		break;
-	case 2:
-		usbdr_clk = csb_clk / 2;
-		break;
-	case 3:
-		usbdr_clk = csb_clk / 3;
-		break;
-	default:
-		/* unkown SCCR_USBDRCM value */
-		return -8;
-	}
-
 	if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
 		/* if USB MPH clock is not disabled and
 		 * USB DR clock is not disabled then
@@ -230,8 +234,16 @@ int get_clocks(void)
 		 */
 		return -9;
 	}
+#elif defined(CONFIG_MPC831X)
+	tsec2_clk = tsec1_clk;
+
+	if (!(sccr & SCCR_TSEC1ON))
+		tsec1_clk = 0;
+	if (!(sccr & SCCR_TSEC2ON))
+		tsec2_clk = 0;
 #endif
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
+
+#if !defined(CONFIG_MPC834X)
 	i2c1_clk = csb_clk;
 #endif
 #if !defined(CONFIG_MPC832X)
@@ -314,11 +326,13 @@ int get_clocks(void)
 #endif
 
 	gd->csb_clk = csb_clk;
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X)
 	gd->tsec1_clk = tsec1_clk;
 	gd->tsec2_clk = tsec2_clk;
-	gd->usbmph_clk = usbmph_clk;
 	gd->usbdr_clk = usbdr_clk;
+#endif
+#if defined(CONFIG_MPC834X)
+	gd->usbmph_clk = usbmph_clk;
 #endif
 	gd->core_clk = core_clk;
 	gd->i2c1_clk = i2c1_clk;
@@ -371,11 +385,13 @@ int print_clock_conf(void)
 #if !defined(CONFIG_MPC832X)
 	printf("  I2C2:                %4d MHz\n", gd->i2c2_clk / 1000000);
 #endif
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X)
 	printf("  TSEC1:               %4d MHz\n", gd->tsec1_clk / 1000000);
 	printf("  TSEC2:               %4d MHz\n", gd->tsec2_clk / 1000000);
-	printf("  USB MPH:             %4d MHz\n", gd->usbmph_clk / 1000000);
 	printf("  USB DR:              %4d MHz\n", gd->usbdr_clk / 1000000);
+#endif
+#if defined(CONFIG_MPC834X)
+	printf("  USB MPH:             %4d MHz\n", gd->usbmph_clk / 1000000);
 #endif
 	return 0;
 }
-- 
cgit v1.2.1


From 49ea3b6eafe606285ae4d5c378026153dde53200 Mon Sep 17 00:00:00 2001
From: Scott Wood <scottwood@freescale.com>
Date: Mon, 16 Apr 2007 14:34:21 -0500
Subject: mpc83xx: Add generic PCI setup code.

Board code can now request the generic setup code rather than having to
copy-and-paste it for themselves.  Boards should be converted to use this
once they're tested with it.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 cpu/mpc83xx/Makefile |   2 +-
 cpu/mpc83xx/pci.c    | 191 +++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 192 insertions(+), 1 deletion(-)
 create mode 100644 cpu/mpc83xx/pci.c

(limited to 'cpu')

diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile
index 4b9dcc8180..bb96f774fe 100644
--- a/cpu/mpc83xx/Makefile
+++ b/cpu/mpc83xx/Makefile
@@ -29,7 +29,7 @@ LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
 COBJS	= traps.o cpu.o cpu_init.o speed.o interrupts.o \
-	  spd_sdram.o qe_io.o
+	  spd_sdram.o qe_io.o pci.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c
new file mode 100644
index 0000000000..2a2b0bd902
--- /dev/null
+++ b/cpu/mpc83xx/pci.c
@@ -0,0 +1,191 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2007
+ *
+ * Author: Scott Wood <scottwood@freescale.com>,
+ * with some bits from older board-specific PCI initialization.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/mpc8349_pci.h>
+
+#ifdef CONFIG_83XX_GENERIC_PCI
+#define MAX_BUSES 2
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pci_controller pci_hose[MAX_BUSES];
+static int pci_num_buses;
+
+static void pci_init_bus(int bus, struct pci_region *reg)
+{
+	volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+	volatile pot83xx_t *pot = immr->ios.pot;
+	volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus];
+	struct pci_controller *hose = &pci_hose[bus];
+	u32 dev;
+	u16 reg16;
+	int i;
+
+	if (bus == 1)
+		pot += 3;
+
+	/* Setup outbound translation windows */
+	for (i = 0; i < 3; i++, reg++, pot++) {
+		if (reg->size == 0)
+			break;
+
+		hose->regions[i] = *reg;
+		hose->region_count++;
+
+		pot->potar = reg->bus_start >> 12;
+		pot->pobar = reg->phys_start >> 12;
+		pot->pocmr = ~(reg->size - 1) >> 12;
+
+		if (reg->flags & PCI_REGION_IO)
+			pot->pocmr |= POCMR_IO;
+#ifdef CONFIG_83XX_PCI_STREAMING
+		else if (reg->flags & PCI_REGION_PREFETCH)
+			pot->pocmr |= POCMR_SE;
+#endif
+
+		if (bus == 1)
+			pot->pocmr |= POCMR_DST;
+
+		pot->pocmr |= POCMR_EN;
+	}
+
+	/* Point inbound translation at RAM */
+	pci_ctrl->pitar1 = 0;
+	pci_ctrl->pibar1 = 0;
+	pci_ctrl->piebar1 = 0;
+	pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
+	                   PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
+
+	i = hose->region_count++;
+	hose->regions[i].bus_start = 0;
+	hose->regions[i].phys_start = 0;
+	hose->regions[i].size = gd->ram_size;
+	hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY;
+
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	pci_setup_indirect(hose, CFG_IMMR + 0x8300 + bus * 0x80,
+	                         CFG_IMMR + 0x8304 + bus * 0x80);
+
+	pci_register_hose(hose);
+
+	/*
+	 * Write to Command register
+	 */
+	reg16 = 0xff;
+	dev = PCI_BDF(hose->first_busno, 0, 0);
+	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
+	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
+
+	/*
+	 * Clear non-reserved bits in status register.
+	 */
+	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+	printf("PCI:   Bus Dev VenId DevId Class Int\n");
+#endif
+	/*
+	 * Hose scan.
+	 */
+	hose->last_busno = pci_hose_scan(hose);
+}
+
+/*
+ * The caller must have already set OCCR, and the PCI_LAW BARs
+ * must have been set to cover all of the requested regions.
+ *
+ * If fewer than three regions are requested, then the region
+ * list is terminated with a region of size 0.
+ */
+void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot)
+{
+	volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+	int i;
+
+	if (num_buses > MAX_BUSES) {
+		printf("%d PCI buses requsted, %d supported\n",
+		       num_buses, MAX_BUSES);
+
+		num_buses = MAX_BUSES;
+	}
+
+	pci_num_buses = num_buses;
+
+	/*
+	 * Release PCI RST Output signal.
+	 * Power on to RST high must be at least 100 ms as per PCI spec.
+	 * On warm boots only 1 ms is required.
+	 */
+	udelay(warmboot ? 1000 : 100000);
+
+	for (i = 0; i < num_buses; i++)
+		immr->pci_ctrl[i].gcr = 1;
+
+	/*
+	 * RST high to first config access must be at least 2^25 cycles
+	 * as per PCI spec.  This could be cut in half if we know we're
+	 * running at 66MHz.  This could be insufficiently long if we're
+	 * running the PCI bus at significantly less than 33MHz.
+	 */
+	udelay(1020000);
+
+	for (i = 0; i < num_buses; i++)
+		pci_init_bus(i, reg[i]);
+}
+
+#ifdef CONFIG_OF_FLAT_TREE
+void ft_pci_setup(void *blob, bd_t *bd)
+{
+	u32 *p;
+	int len;
+
+	if (pci_num_buses < 1)
+		return;
+
+	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
+	if (p) {
+		p[0] = pci_hose[0].first_busno;
+		p[1] = pci_hose[0].last_busno;
+	}
+
+	if (pci_num_buses < 2)
+		return;
+
+	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
+	if (p) {
+		p[0] = pci_hose[1].first_busno;
+		p[1] = pci_hose[1].last_busno;
+	}
+}
+#endif /* CONFIG_OF_FLAT_TREE */
+
+#endif /* CONFIG_83XX_GENERIC_PCI */
-- 
cgit v1.2.1


From 5c5d3242935cf3543af01142627494434834cf98 Mon Sep 17 00:00:00 2001
From: Kim Phillips <kim.phillips@freescale.com>
Date: Wed, 25 Apr 2007 12:34:38 -0500
Subject: mpc83xx: minor fixups for 8313rdb introduction

---
 cpu/mpc83xx/pci.c | 1 +
 1 file changed, 1 insertion(+)

(limited to 'cpu')

diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c
index 2a2b0bd902..785d6129da 100644
--- a/cpu/mpc83xx/pci.c
+++ b/cpu/mpc83xx/pci.c
@@ -25,6 +25,7 @@
 
 #include <common.h>
 #include <pci.h>
+#include <ft_build.h>
 #include <asm/mpc8349_pci.h>
 
 #ifdef CONFIG_83XX_GENERIC_PCI
-- 
cgit v1.2.1


From 54b2d434ae9d01787936f34fe1759cf3d7624ae3 Mon Sep 17 00:00:00 2001
From: Kim Phillips <kim.phillips@freescale.com>
Date: Mon, 30 Apr 2007 15:26:21 -0500
Subject: mpc83xx: replace elaborate boottime verbosity with 'clocks' command

and fix CPU: to align with Board: display text.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
 cpu/mpc83xx/cpu.c   |  8 +++++---
 cpu/mpc83xx/speed.c | 10 ++++++++--
 2 files changed, 13 insertions(+), 5 deletions(-)

(limited to 'cpu')

diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index 332afaad9f..e078f27a23 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -52,7 +52,7 @@ int checkcpu(void)
 
 	immr = (immap_t *)CFG_IMMR;
 
-	puts("CPU: ");
+	puts("CPU:   ");
 
 	switch (pvr & 0xffff0000) {
 		case PVR_E300C1:
@@ -158,10 +158,12 @@ int checkcpu(void)
 	/* Multiple revisons of 834x processors may have the same SPRIDR value.
 	 * So use PVR to identify the revision number.
 	 */
-	printf("Rev: %02x at %s MHz\n", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock));
+	printf("Rev: %02x at %s MHz", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock));
 #else
-	printf("Rev: %02x at %s MHz\n", spridr & 0x0000FFFF, strmhz(buf, clock));
+	printf("Rev: %02x at %s MHz", spridr & 0x0000FFFF, strmhz(buf, clock));
 #endif
+	printf(", CSB: %4d MHz\n", gd->csb_clk / 1000000);
+
 	return 0;
 }
 
diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index 1a440310e5..bf30616548 100644
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -25,6 +25,7 @@
 
 #include <common.h>
 #include <mpc83xx.h>
+#include <command.h>
 #include <asm/processor.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -365,11 +366,11 @@ ulong get_bus_freq(ulong dummy)
 	return gd->csb_clk;
 }
 
-int print_clock_conf(void)
+int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
 	printf("Clock configuration:\n");
-	printf("  Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
 	printf("  Core:                %4d MHz\n", gd->core_clk / 1000000);
+	printf("  Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
 	printf("  QE:                  %4d MHz\n", gd->qe_clk / 1000000);
 	printf("  BRG:                 %4d MHz\n", gd->brg_clk / 1000000);
@@ -395,3 +396,8 @@ int print_clock_conf(void)
 #endif
 	return 0;
 }
+
+U_BOOT_CMD(clocks, 1, 0, do_clocks,
+	"clocks  - print clock configuration\n",
+	"    clocks\n"
+);
-- 
cgit v1.2.1


From f64702b7fc8f8df39d31add770df6e372f9e9ce3 Mon Sep 17 00:00:00 2001
From: Timur Tabi <timur@freescale.com>
Date: Mon, 30 Apr 2007 13:59:50 -0500
Subject: Fix memory initialization on MPC8349E-mITX

Define CFG_DDR_SDRAM_CLK_CNTL for the MPC8349E-mITX and MPC8349E-mITX-GP.
This allows ddr->sdram_clk_cntl to be properly initialized.  This is necessary
on some ITX boards, notably those with a revision 3.1 CPU.

Also change spd_sdram() in cpu/mpc83xx/spd_sdram.c to not write anything into
ddr->sdram_clk_cntl if CFG_DDR_SDRAM_CLK_CNTL is not defined.

Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-by: Michael Benedict <MBenedict@twacs.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
 cpu/mpc83xx/spd_sdram.c | 5 -----
 1 file changed, 5 deletions(-)

(limited to 'cpu')

diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 41a1f1fc7b..647813f68d 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -693,11 +693,6 @@ long int spd_sdram()
 
 #ifdef CFG_DDR_SDRAM_CLK_CNTL	/* Optional platform specific value */
 	ddr->sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
-#else
-	/* SS_EN = 0, source synchronous disable
-	 * CLK_ADJST = 0, MCK/MCK# is launched aligned with addr/cmd
-	 */
-	ddr->sdram_clk_cntl = 0x00000000;
 #endif
 	debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
 
-- 
cgit v1.2.1


From 42efed6130c8fcf7da881385b5427065d2801757 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Mon, 7 May 2007 17:22:25 +0200
Subject: fix: interrupt handler for multiple sources

---
 cpu/microblaze/interrupts.c | 19 ++++++++++++-------
 cpu/microblaze/timer.c      |  4 +---
 2 files changed, 13 insertions(+), 10 deletions(-)

(limited to 'cpu')

diff --git a/cpu/microblaze/interrupts.c b/cpu/microblaze/interrupts.c
index 2db847cd02..115e58d7f0 100644
--- a/cpu/microblaze/interrupts.c
+++ b/cpu/microblaze/interrupts.c
@@ -27,6 +27,7 @@
 #include <common.h>
 #include <command.h>
 #include <asm/microblaze_intc.h>
+#include <asm/asm.h>
 
 #undef DEBUG_INT
 
@@ -106,7 +107,6 @@ void install_interrupt_handler (int irq, interrupt_handler_t * hdlr, void *arg)
 		act->count = 0;
 		enable_one_interrupt (irq);
 	} else {		/* disable */
-
 		act->handler = (interrupt_handler_t *) def_hdlr;
 		act->arg = (void *)irq;
 		disable_one_interrupt (irq);
@@ -147,12 +147,13 @@ int interrupts_init (void)
 
 void interrupt_handler (void)
 {
-	int irqs;
-	irqs = (intc->isr & intc->ier);	/* find active interrupt */
-
+	int irqs = (intc->isr & intc->ier);	/* find active interrupt */
+	int i = 1;
 #ifdef DEBUG_INT
+	int value;
 	printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
 		intc->iar, intc->mer);
+	R14(value);
 	printf ("Interrupt handler on %x line, r14 %x\n", irqs, value);
 #endif
 	struct irq_action *act = vecs;
@@ -165,15 +166,19 @@ void interrupt_handler (void)
 #endif
 			act->handler (act->arg);
 			act->count++;
+			intc->iar = i;
+			return;
 		}
 		irqs >>= 1;
 		act++;
+		i <<= 1;
 	}
-	intc->iar = 0xFFFFFFFF;	/* erase all events */
-#ifdef DEBUG
+
+#ifdef DEBUG_INT
 	printf ("Dump INTC reg, isr %x, ier %x, iar %x, mer %x\n", intc->isr,
 		intc->ier, intc->iar, intc->mer);
-	printf ("Interrupt handler on %x line, r14\n", irqs);
+	R14(value);
+	printf ("Interrupt handler on %x line, r14 %x\n", irqs, value);
 #endif
 }
 #endif
diff --git a/cpu/microblaze/timer.c b/cpu/microblaze/timer.c
index be4fd57cc4..ab1cb12749 100644
--- a/cpu/microblaze/timer.c
+++ b/cpu/microblaze/timer.c
@@ -24,6 +24,7 @@
 
 #include <common.h>
 #include <asm/microblaze_timer.h>
+#include <asm/microblaze_intc.h>
 
 volatile int timestamp = 0;
 
@@ -44,9 +45,6 @@ void set_timer (ulong t)
 
 #ifdef CFG_INTC_0
 #ifdef CFG_TIMER_0
-extern void install_interrupt_handler (int irq, interrupt_handler_t * hdlr,
-				       void *arg);
-
 microblaze_timer_t *tmr = (microblaze_timer_t *) (CFG_TIMER_0_ADDR);
 
 void timer_isr (void *arg)
-- 
cgit v1.2.1


From fb7c2dbef02c9f6f8d7b04ec4c2bfb91418b9c01 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Mon, 7 May 2007 19:12:43 +0200
Subject: fix: clean interrupt

---
 cpu/microblaze/Makefile     |  3 ++-
 cpu/microblaze/interrupts.c | 13 +++++++++++--
 2 files changed, 13 insertions(+), 3 deletions(-)

(limited to 'cpu')

diff --git a/cpu/microblaze/Makefile b/cpu/microblaze/Makefile
index db1afa553d..b7be5e146c 100644
--- a/cpu/microblaze/Makefile
+++ b/cpu/microblaze/Makefile
@@ -26,7 +26,8 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
-SOBJS	= dcache.o icache.o irq.o disable_int.o enable_int.o
+#SOBJS	= dcache.o icache.o irq.o disable_int.o enable_int.o
+SOBJS	= dcache.o icache.o irq.o
 COBJS	= cpu.o interrupts.o cache.o exception.o timer.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/cpu/microblaze/interrupts.c b/cpu/microblaze/interrupts.c
index 115e58d7f0..c0c92ec559 100644
--- a/cpu/microblaze/interrupts.c
+++ b/cpu/microblaze/interrupts.c
@@ -36,12 +36,14 @@ extern void microblaze_enable_interrupts (void);
 
 void enable_interrupts (void)
 {
-	microblaze_enable_interrupts ();
+	__asm__ __volatile__ ("msrset r0, 0x2");
+	//microblaze_enable_interrupts ();
 }
 
 int disable_interrupts (void)
 {
-	microblaze_disable_interrupts ();
+	__asm__ __volatile__ ("msrclr r0, 0x2");
+	//microblaze_disable_interrupts ();
 	return 0;
 }
 
@@ -49,6 +51,10 @@ int disable_interrupts (void)
 #ifdef CFG_TIMER_0
 extern void timer_init (void);
 #endif
+#ifdef CFG_FSL_2
+extern void fsl_init2 (void);
+#endif
+
 
 static struct irq_action vecs[CFG_INTC_0_NUM];
 
@@ -140,6 +146,9 @@ int interrupts_init (void)
 	intc_init ();
 #ifdef CFG_TIMER_0
 	timer_init ();
+#endif
+#ifdef CFG_FSL_2
+	fsl_init2 ();
 #endif
 	enable_interrupts ();
 	return 0;
-- 
cgit v1.2.1


From f3f001a341ef185d0f13841be5b5dc3395aacc31 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Mon, 7 May 2007 19:25:08 +0200
Subject: fix: remove asm code

---
 cpu/microblaze/Makefile      |  3 +-
 cpu/microblaze/cache.c       | 16 ++++++++++
 cpu/microblaze/dcache.S      | 68 -------------------------------------------
 cpu/microblaze/disable_int.S | 46 -----------------------------
 cpu/microblaze/enable_int.S  | 38 ------------------------
 cpu/microblaze/icache.S      | 69 --------------------------------------------
 6 files changed, 17 insertions(+), 223 deletions(-)
 delete mode 100644 cpu/microblaze/dcache.S
 delete mode 100644 cpu/microblaze/disable_int.S
 delete mode 100644 cpu/microblaze/enable_int.S
 delete mode 100644 cpu/microblaze/icache.S

(limited to 'cpu')

diff --git a/cpu/microblaze/Makefile b/cpu/microblaze/Makefile
index b7be5e146c..9d542013cc 100644
--- a/cpu/microblaze/Makefile
+++ b/cpu/microblaze/Makefile
@@ -26,8 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
-#SOBJS	= dcache.o icache.o irq.o disable_int.o enable_int.o
-SOBJS	= dcache.o icache.o irq.o
+SOBJS	= irq.o
 COBJS	= cpu.o interrupts.o cache.o exception.o timer.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/cpu/microblaze/cache.c b/cpu/microblaze/cache.c
index fc388ebb56..683044caea 100644
--- a/cpu/microblaze/cache.c
+++ b/cpu/microblaze/cache.c
@@ -45,4 +45,20 @@ int icache_status (void)
 	__asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory");
 	return i;
 }
+
+void	icache_enable (void) {
+	__asm__ __volatile__ ("msrset r0, 0x80");
+}
+
+void	icache_disable(void) {
+	__asm__ __volatile__ ("msrclr r0, 0x80");
+}
+
+void	dcache_enable (void) {
+	__asm__ __volatile__ ("msrset r0, 0x20");
+}
+
+void	dcache_disable(void) {
+	__asm__ __volatile__ ("msrclr r0, 0x20");
+}
 #endif
diff --git a/cpu/microblaze/dcache.S b/cpu/microblaze/dcache.S
deleted file mode 100644
index eaf96717eb..0000000000
--- a/cpu/microblaze/dcache.S
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * (C) Copyright 2007 Michal Simek
- *
- * Michal  SIMEK <monstr@monstr.eu>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-	.text
-	.globl	dcache_enable
-	.ent	dcache_enable
-	.align	2
-dcache_enable:
-	/* Make space on stack for a temporary */
-	addi	r1, r1, -4
-	/* Save register r12 */
-	swi	r12, r1, 0
-	/* Read the MSR register */
-	mfs	r12, rmsr
-	/* Set the instruction enable bit */
-	ori	r12, r12, 0x80
-	/* Save the MSR register */
-	mts	rmsr, r12
-	/* Load register r12 */
-	lwi	r12, r1, 0
-	/* Return */
-	rtsd	r15, 8
-	/* Update stack in the delay slot */
-	addi	r1, r1, 4
-	.end	dcache_enable
-
-	.text
-	.globl	dcache_disable
-	.ent	dcache_disable
-	.align	2
-dcache_disable:
-	/* Make space on stack for a temporary */
-	addi	r1, r1, -4
-	/* Save register r12 */
-	swi	r12, r1, 0
-	/* Read the MSR register */
-	mfs	r12, rmsr
-	/* Clear the data cache enable bit */
-	andi	r12, r12, ~0x80
-	/* Save the MSR register */
-	mts	rmsr, r12
-	/* Load register r12 */
-	lwi	r12, r1, 0
-	/* Return */
-	rtsd	r15, 8
-	/* Update stack in the delay slot */
-	addi	r1, r1, 4
-	.end	dcache_disable
diff --git a/cpu/microblaze/disable_int.S b/cpu/microblaze/disable_int.S
deleted file mode 100644
index aecd79513c..0000000000
--- a/cpu/microblaze/disable_int.S
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * (C) Copyright 2007 Michal Simek
- *
- * Michal  SIMEK <monstr@monstr.eu>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-	.text
-	.globl	microblaze_disable_interrupts
-	.ent	microblaze_disable_interrupts
-	.align	2
-microblaze_disable_interrupts:
-	#Make space on stack for a temporary
-	addi	r1, r1, -4
-	#Save register r12
-	swi	r12, r1, 0
-	#Read the MSR register
-	mfs	r12, rmsr
-	#Clear the interrupt enable bit
-	andi	r12, r12, ~2
-	#Save the MSR register
-	mts	rmsr, r12
-	#Load register r12
-	lwi	r12, r1, 0
-	#Return
-	rtsd	r15, 8
-	#Update stack in the delay slot
-	addi	r1, r1, 4
-	.end	microblaze_disable_interrupts
diff --git a/cpu/microblaze/enable_int.S b/cpu/microblaze/enable_int.S
deleted file mode 100644
index c096c6c3c0..0000000000
--- a/cpu/microblaze/enable_int.S
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * (C) Copyright 2007 Michal Simek
- *
- * Michal  SIMEK <monstrmonstr.eu>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-	.text
-	.globl	microblaze_enable_interrupts
-	.ent	microblaze_enable_interrupts
-	.align	2
-microblaze_enable_interrupts:
-	addi	r1, r1, -4
-	swi	r12, r1, 0
-	mfs	r12, rmsr
-	ori	r12, r12, 2
-	mts	rmsr, r12
-	lwi	r12, r1, 0
-	rtsd	r15, 8
-	addi	r1, r1, 4
-	.end	microblaze_enable_interrupts
diff --git a/cpu/microblaze/icache.S b/cpu/microblaze/icache.S
deleted file mode 100644
index 25940d106e..0000000000
--- a/cpu/microblaze/icache.S
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * (C) Copyright 2007 Michal Simek
- *
- * Michal  SIMEK <monstr@monstr.eu>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-	.text
-	.globl	icache_enable
-	.ent	icache_enable
-	.align	2
-icache_enable:
-	/* Make space on stack for a temporary */
-	addi	r1, r1, -4
-	/* Save register r12 */
-	swi	r12, r1, 0
-	/* Read the MSR register */
-	mfs	r12, rmsr
-	/* Set the instruction enable bit */
-	ori	r12, r12, 0x20
-	/* Save the MSR register */
-	mts	rmsr, r12
-	/* Load register r12 */
-	lwi	r12, r1, 0
-	/* Return */
-	rtsd	r15, 8
-	/* Update stack in the delay slot */
-	addi	r1, r1, 4
-	.end	icache_enable
-
-	.text
-	.globl	icache_disable
-	.ent	icache_disable
-	.align	2
-icache_disable:
-	/* Make space on stack for a temporary */
-	addi	r1, r1, -4
-	/* Save register r12 */
-	swi	r12, r1, 0
-	/* Read the MSR register */
-	mfs	r12, rmsr
-	/* Clear the instruction enable bit */
-	andi	r12, r12, ~0x20
-	/* Save the MSR register */
-	mts	rmsr, r12
-	/* Load register r12 */
-	lwi	r12, r1, 0
-	/* Return */
-	rtsd	r15, 8
-	/* Update stack in the delay slot */
-	addi	r1, r1, 4
-	.end	icache_disable
-- 
cgit v1.2.1


From 792032baa7d625e34c981ab6df521911bd8dc861 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Mon, 7 May 2007 19:30:12 +0200
Subject: fix: interrupt handler remove asm code

---
 cpu/microblaze/interrupts.c | 2 --
 cpu/microblaze/irq.S        | 9 +--------
 2 files changed, 1 insertion(+), 10 deletions(-)

(limited to 'cpu')

diff --git a/cpu/microblaze/interrupts.c b/cpu/microblaze/interrupts.c
index c0c92ec559..dd6a0c7776 100644
--- a/cpu/microblaze/interrupts.c
+++ b/cpu/microblaze/interrupts.c
@@ -37,13 +37,11 @@ extern void microblaze_enable_interrupts (void);
 void enable_interrupts (void)
 {
 	__asm__ __volatile__ ("msrset r0, 0x2");
-	//microblaze_enable_interrupts ();
 }
 
 int disable_interrupts (void)
 {
 	__asm__ __volatile__ ("msrclr r0, 0x2");
-	//microblaze_disable_interrupts ();
 	return 0;
 }
 
diff --git a/cpu/microblaze/irq.S b/cpu/microblaze/irq.S
index a4e3fbfad6..393d6e8dd4 100644
--- a/cpu/microblaze/irq.S
+++ b/cpu/microblaze/irq.S
@@ -151,14 +151,7 @@ _interrupt_handler:
 	addi	r1, r1, 4
 
 	/* enable_interrupt */
-	addi	r1, r1, -4
-	swi	r12, r1, 0
-	mfs	r12, rmsr
-	ori	r12, r12, 2
-	mts	rmsr, r12
-	lwi	r12, r1, 0
-	addi	r1, r1, 4
-	nop
+	msrset	r0, 2
 	bra	r14
 	nop
 	nop
-- 
cgit v1.2.1


From 008861a2f3ef2c062744d733787c7e530a1b8761 Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Mon, 7 May 2007 22:36:15 +0200
Subject: [MPC5xxx] There are networking problems on the Motion-PRO board with
 current PHY initalization code (tftp timeouts all the time). This commit
 temporarily disables PHY initalization sequence to make the networking
 operational, until a fix is found.

---
 cpu/mpc5xxx/fec.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

(limited to 'cpu')

diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c
index e6392340a9..0b8f24d18a 100644
--- a/cpu/mpc5xxx/fec.c
+++ b/cpu/mpc5xxx/fec.c
@@ -395,7 +395,9 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
 static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
 {
 	mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
+#ifndef CONFIG_MOTIONPRO
 	const uint8 phyAddr = CONFIG_PHY_ADDR;	/* Only one PHY */
+#endif /* !CONFIG_MOTIONPRO */
 
 #if (DEBUG & 0x1)
 	printf ("mpc5xxx_fec_init_phy... Begin\n");
@@ -428,6 +430,14 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
 	 */
 	fec->eth->imask = 0x00000000;
 
+/*
+ * In original Promess-provided code PHY initialization is disabled with the
+ * following comment: "Phy initialization is DISABLED for now.  There was a
+ * problem with running 100 Mbps on PRO board". Thus we temporarily disable
+ * PHY initialization for the Motion-PRO board, until a proper fix is found.
+ */
+
+#ifndef CONFIG_MOTIONPRO
 	if (fec->xcv_type != SEVENWIRE) {
 		/*
 		 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
@@ -550,6 +560,7 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
 		}
 
 	}
+#endif /* !CONFIG_MOTIONPRO */
 
 #if (DEBUG & 0x2)
 	if (fec->xcv_type != SEVENWIRE)
-- 
cgit v1.2.1


From fb05f6da35ea1c15c553abe6f23f656bf18dc5db Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Mon, 7 May 2007 23:58:31 +0200
Subject: new: USE_MSR_INTR support

---
 cpu/microblaze/cache.c      |  9 +++++----
 cpu/microblaze/interrupts.c |  4 ++--
 cpu/microblaze/irq.S        | 14 ++++++++++++++
 3 files changed, 21 insertions(+), 6 deletions(-)
 mode change 100644 => 100755 cpu/microblaze/cache.c
 mode change 100644 => 100755 cpu/microblaze/interrupts.c
 mode change 100644 => 100755 cpu/microblaze/irq.S

(limited to 'cpu')

diff --git a/cpu/microblaze/cache.c b/cpu/microblaze/cache.c
old mode 100644
new mode 100755
index 683044caea..4f36a84ec4
--- a/cpu/microblaze/cache.c
+++ b/cpu/microblaze/cache.c
@@ -23,6 +23,7 @@
  */
 
 #include <common.h>
+#include <asm/asm.h>
 
 #if (CONFIG_COMMANDS & CFG_CMD_CACHE)
 
@@ -47,18 +48,18 @@ int icache_status (void)
 }
 
 void	icache_enable (void) {
-	__asm__ __volatile__ ("msrset r0, 0x80");
+	MSRSET(0x20);
 }
 
 void	icache_disable(void) {
-	__asm__ __volatile__ ("msrclr r0, 0x80");
+	MSRCLR(0x20);
 }
 
 void	dcache_enable (void) {
-	__asm__ __volatile__ ("msrset r0, 0x20");
+	MSRSET(0x80);
 }
 
 void	dcache_disable(void) {
-	__asm__ __volatile__ ("msrclr r0, 0x20");
+	MSRCLR(0x80);
 }
 #endif
diff --git a/cpu/microblaze/interrupts.c b/cpu/microblaze/interrupts.c
old mode 100644
new mode 100755
index dd6a0c7776..b61153f8e6
--- a/cpu/microblaze/interrupts.c
+++ b/cpu/microblaze/interrupts.c
@@ -36,12 +36,12 @@ extern void microblaze_enable_interrupts (void);
 
 void enable_interrupts (void)
 {
-	__asm__ __volatile__ ("msrset r0, 0x2");
+	MSRSET(0x2);
 }
 
 int disable_interrupts (void)
 {
-	__asm__ __volatile__ ("msrclr r0, 0x2");
+	MSRCLR(0x2);
 	return 0;
 }
 
diff --git a/cpu/microblaze/irq.S b/cpu/microblaze/irq.S
old mode 100644
new mode 100755
index 393d6e8dd4..e1fc19046c
--- a/cpu/microblaze/irq.S
+++ b/cpu/microblaze/irq.S
@@ -23,6 +23,7 @@
  */
 
 #include <config.h>
+#include <asm/asm.h>
 	.text
 	.global _interrupt_handler
 _interrupt_handler:
@@ -151,7 +152,20 @@ _interrupt_handler:
 	addi	r1, r1, 4
 
 	/* enable_interrupt */
+#ifdef XILINX_USE_MSR_INSTR
 	msrset	r0, 2
+#else
+	/* FIXME unstable in stressed mode - two irqs */
+	nop
+	addi	r1, r1, -4
+	swi	r12, r1, 0
+	mfs	r12, rmsr
+	ori	r12, r12, 2
+	mts	rmsr, r12
+	lwi	r12, r1, 0
+	addi	r1, r1, 4
+	nop
+#endif
 	bra	r14
 	nop
 	nop
-- 
cgit v1.2.1


From 1a50f164beb065f360fbddb76029607d6b099698 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Tue, 8 May 2007 14:52:52 +0200
Subject: add: Microblaze V5 exception handling

---
 cpu/microblaze/exception.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

(limited to 'cpu')

diff --git a/cpu/microblaze/exception.c b/cpu/microblaze/exception.c
index b135acbad9..87ecbeaa49 100644
--- a/cpu/microblaze/exception.c
+++ b/cpu/microblaze/exception.c
@@ -23,15 +23,16 @@
  */
 
 #include <common.h>
+#include <asm/asm.h>
 
 void _hw_exception_handler (void)
 {
 	int address = 0;
 	int state = 0;
 	/* loading address of exception EAR */
-	__asm__ __volatile ("mfs %0,rear"::"r" (address):"memory");
+	MFSEAR(address);
 	/* loading excetpion state register ESR */
-	__asm__ __volatile ("mfs %0,resr"::"r" (state):"memory");
+	MFSESR(state);
 	printf ("Hardware exception at 0x%x address\n", address);
 	switch (state & 0x1f) {	/* mask on exception cause */
 	case 0x1:
@@ -49,6 +50,11 @@ void _hw_exception_handler (void)
 	case 0x5:
 		puts ("Divide by zero exception\n");
 		break;
+#ifdef MICROBLAZE_V5
+	case 0x1000:
+		puts ("Exception in delay slot\n");
+		break;
+#endif
 	default:
 		puts ("Undefined cause\n");
 		break;
-- 
cgit v1.2.1


From e69f66c6ebe82bbbd1da766bc4eda40ec7ee5af1 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Tue, 8 May 2007 15:57:43 +0200
Subject: add: reading special purpose registers

---
 cpu/microblaze/exception.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'cpu')

diff --git a/cpu/microblaze/exception.c b/cpu/microblaze/exception.c
index 87ecbeaa49..d76b05a526 100644
--- a/cpu/microblaze/exception.c
+++ b/cpu/microblaze/exception.c
@@ -30,9 +30,9 @@ void _hw_exception_handler (void)
 	int address = 0;
 	int state = 0;
 	/* loading address of exception EAR */
-	MFSEAR(address);
+	MFS (address, rear);
 	/* loading excetpion state register ESR */
-	MFSESR(state);
+	MFS (state, resr);
 	printf ("Hardware exception at 0x%x address\n", address);
 	switch (state & 0x1f) {	/* mask on exception cause */
 	case 0x1:
-- 
cgit v1.2.1