From 2f5d414ccb4024dd0992ff6b22561732dbc73590 Mon Sep 17 00:00:00 2001
From: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Date: Tue, 25 Mar 2008 21:30:06 +0900
Subject: [MIPS] cpu/mips/cache.S: Introduce NESTED/LEAF/END macros

This patch replaces the current function definitions with NESTED, LEAF
and END macro. They specify some more additional information about the
function; an alignment of symbol, type of symbol, stack frame usage, etc.
These information explicitly tells the assembler and the debugger about
the types of code we want to generate.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
---
 cpu/mips/cache.S | 25 +++++++------------------
 1 file changed, 7 insertions(+), 18 deletions(-)

(limited to 'cpu')

diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S
index 67ee19fba8..e2e1da0505 100644
--- a/cpu/mips/cache.S
+++ b/cpu/mips/cache.S
@@ -24,6 +24,7 @@
 
 #include <config.h>
 #include <version.h>
+#include <asm/asm.h>
 #include <asm/regdef.h>
 #include <asm/mipsregs.h>
 #include <asm/addrspace.h>
@@ -119,10 +120,7 @@
 * RETURNS: N/A
 *
 */
-	.globl	mips_cache_reset
-	.ent	mips_cache_reset
-mips_cache_reset:
-
+NESTED(mips_cache_reset, 0, ra)
 	li	t2, CFG_ICACHE_SIZE
 	li	t3, CFG_DCACHE_SIZE
 	li	t4, CFG_CACHELINE_SIZE
@@ -198,8 +196,7 @@ mips_cache_reset:
 	icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
 
 	j	ra
-
-	.end	mips_cache_reset
+	END(mips_cache_reset)
 
 /*******************************************************************************
 *
@@ -208,15 +205,11 @@ mips_cache_reset:
 * RETURNS: 0 - cache disabled; 1 - cache enabled
 *
 */
-	.globl	dcache_status
-	.ent	dcache_status
-dcache_status:
-
+LEAF(dcache_status)
 	mfc0	v0, CP0_CONFIG
 	andi	v0, v0, 1
 	j	ra
-
-	.end	dcache_status
+	END(dcache_status)
 
 /*******************************************************************************
 *
@@ -225,18 +218,14 @@ dcache_status:
 * RETURNS: N/A
 *
 */
-	.globl	dcache_disable
-	.ent	dcache_disable
-dcache_disable:
-
+LEAF(dcache_disable)
 	mfc0	t0, CP0_CONFIG
 	li	t1, -8
 	and	t0, t0, t1
 	ori	t0, t0, CONF_CM_UNCACHED
 	mtc0	t0, CP0_CONFIG
 	j	ra
-
-	.end	dcache_disable
+	END(dcache_disable)
 
 #ifdef CFG_INIT_RAM_LOCK_MIPS
 /*******************************************************************************
-- 
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