From 6b70ffb9d1b2e791161f3cf92937aa45b4a07b78 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 16 Jun 2008 15:55:53 -0500 Subject: fdt: add crypto node handling for MPC8{3, 5}xxE processors Delete the crypto node if not on an E-processor. If on 8360 or 834x family, check rev and up-rev crypto node (to SEC rev. 2.4 property values) if on an 'EA' processor, e.g. MPC8349EA. Signed-off-by: Kim Phillips --- cpu/mpc83xx/fdt.c | 18 ++++++++++++++++++ cpu/mpc85xx/fdt.c | 5 +++++ 2 files changed, 23 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc83xx/fdt.c b/cpu/mpc83xx/fdt.c index 02c4d0529c..267ae6adc5 100644 --- a/cpu/mpc83xx/fdt.c +++ b/cpu/mpc83xx/fdt.c @@ -26,6 +26,7 @@ #include #include #include +#include extern void ft_qe_setup(void *blob); @@ -33,6 +34,23 @@ DECLARE_GLOBAL_DATA_PTR; void ft_cpu_setup(void *blob, bd_t *bd) { + immap_t *immr = (immap_t *)CFG_IMMR; + int spridr = immr->sysconf.spridr; + + /* + * delete crypto node if not on an E-processor + * initial revisions of the MPC834xE/6xE have the original SEC 2.0. + * EA revisions got the SEC uprevved to 2.4 but since the default device + * tree contains SEC 2.0 properties we uprev them here. + */ + if (!IS_E_PROCESSOR(spridr)) + fdt_fixup_crypto_node(blob, 0); + else if (IS_E_PROCESSOR(spridr) && + (SPR_FAMILY(spridr) == SPR_834X_FAMILY || + SPR_FAMILY(spridr) == SPR_836X_FAMILY) && + REVID_MAJOR(spridr) >= 2) + fdt_fixup_crypto_node(blob, 0x0204); + #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) fdt_fixup_ethernet(blob, bd); diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 92952e6d6e..c8d2c6ac22 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -29,6 +29,7 @@ #include extern void ft_qe_setup(void *blob); + #ifdef CONFIG_MP #include "mp.h" DECLARE_GLOBAL_DATA_PTR; @@ -205,6 +206,10 @@ static inline void ft_fixup_cache(void *blob) void ft_cpu_setup(void *blob, bd_t *bd) { + /* delete crypto node if not on an E-processor */ + if (!IS_E_PROCESSOR(get_svr())) + fdt_fixup_crypto_node(blob, 0); + #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) fdt_fixup_ethernet(blob, bd); -- cgit v1.2.1 From 06b4186c10204b6683edb047ac5f506fb0ce0937 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Tue, 17 Jun 2008 17:45:22 -0500 Subject: mpc85xx: use IS_E_PROCESSOR macro Signed-off-by: Kim Phillips --- cpu/mpc85xx/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 0d50549f2d..bde8e56703 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -97,7 +97,7 @@ int checkcpu (void) if (cpu) { puts(cpu->name); - if (svr & 0x80000) + if (IS_E_PROCESSOR(svr)) puts("E"); } else { puts("Unknown"); -- cgit v1.2.1 From 24ef76f320fbadf074105229826514db140f939f Mon Sep 17 00:00:00 2001 From: Andrew Klossner Date: Wed, 2 Jul 2008 07:03:53 -0700 Subject: Change the temp map to ROM to align addresses to page size. With a page size of BOOKE_PAGESZ_16M, both the real and effective addresses must be multiples of 16MB. The hardware silently truncates them so the code happens to work. This patch clarifies the situation by establishing addresses that the hardware doesn't need to truncate. Signed-off-by: Andrew Klossner Signed-off-by: Andy Fleming --- cpu/mpc85xx/start.S | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 2b5d90e278..10fe93629c 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -188,11 +188,12 @@ _start_e500: lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@h ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@l - lis r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@h - ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@l + /* Align the mapping to 16MB */ + lis r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xff000000, (MAS2_I|MAS2_G))@h + ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xff000000, (MAS2_I|MAS2_G))@l - lis r9,FSL_BOOKE_MAS3(0xff800000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h - ori r9,r9,FSL_BOOKE_MAS3(0xff800000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l + lis r9,FSL_BOOKE_MAS3(0xff000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(0xff000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l mtspr MAS0,r6 mtspr MAS1,r7 -- cgit v1.2.1 From 71074abbe0c76429577aff58aeff0a24ad210b23 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Wed, 9 Jul 2008 13:23:05 -0400 Subject: 8xxx-fdt: set ns16550 clock from CFG_NS16550_CLK, not bi_busfreq Some boards that have external 16550 UARTs don't have a direct tie between bi_busfreq and the clock used for the UARTs. Boards that do have such a tie should set CFG_NS16550_CLK to be get_bus_freq(0) -- which most of them do already. Signed-off-by: Paul Gortmaker Acked-by: Kim Phillips --- cpu/mpc83xx/fdt.c | 2 +- cpu/mpc85xx/fdt.c | 2 +- cpu/mpc86xx/fdt.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc83xx/fdt.c b/cpu/mpc83xx/fdt.c index 267ae6adc5..fda85c15d0 100644 --- a/cpu/mpc83xx/fdt.c +++ b/cpu/mpc83xx/fdt.c @@ -78,7 +78,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CFG_NS16550 do_fixup_by_compat_u32(blob, "ns16550", - "clock-frequency", bd->bi_busfreq, 1); + "clock-frequency", CFG_NS16550_CLK, 1); #endif fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index c8d2c6ac22..c159934c5b 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -229,7 +229,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CFG_NS16550 do_fixup_by_compat_u32(blob, "ns16550", - "clock-frequency", bd->bi_busfreq, 1); + "clock-frequency", CFG_NS16550_CLK, 1); #endif #ifdef CONFIG_CPM2 diff --git a/cpu/mpc86xx/fdt.c b/cpu/mpc86xx/fdt.c index 379306ea4f..80a5c78a79 100644 --- a/cpu/mpc86xx/fdt.c +++ b/cpu/mpc86xx/fdt.c @@ -30,6 +30,6 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CFG_NS16550 do_fixup_by_compat_u32(blob, "ns16550", - "clock-frequency", bd->bi_busfreq, 1); + "clock-frequency", CFG_NS16550_CLK, 1); #endif } -- cgit v1.2.1 From 73f15a060f67a2462551c334215bd20fac6b81d1 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 14 Jul 2008 14:07:00 -0500 Subject: 85xx: Cleanup L2 cache size detection The L2 size detection code was a bit confusing and we kept having to add code to it to handle new processors. Change the sense of detection so we look for the older processors that aren't changing. Also added support for 1M cache size on 8572. Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu_init.c | 47 ++++++++++++++++++++++++++++++----------------- 1 file changed, 30 insertions(+), 17 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 736aef1725..4feb7519aa 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -261,37 +261,50 @@ int cpu_init_r(void) volatile uint cache_ctl; uint svr, ver; uint l2srbar; + u32 l2siz_field; svr = get_svr(); ver = SVR_SOC_VER(svr); asm("msync;isync"); cache_ctl = l2cache->l2ctl; + l2siz_field = (cache_ctl >> 28) & 0x3; - switch (cache_ctl & 0x30000000) { - case 0x20000000: - if (ver == SVR_8548 || ver == SVR_8548_E || - ver == SVR_8544 || ver == SVR_8568_E) { - puts ("512 KB "); - /* set L2E=1, L2I=1, & L2SRAM=0 */ - cache_ctl = 0xc0000000; + switch (l2siz_field) { + case 0x0: + printf(" unknown size (0x%08x)\n", cache_ctl); + return -1; + break; + case 0x1: + if (ver == SVR_8540 || ver == SVR_8560 || + ver == SVR_8541 || ver == SVR_8541_E || + ver == SVR_8555 || ver == SVR_8555_E) { + puts("128 KB "); + /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */ + cache_ctl = 0xc4000000; } else { + puts("256 KB "); + cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ + } + break; + case 0x2: + if (ver == SVR_8540 || ver == SVR_8560 || + ver == SVR_8541 || ver == SVR_8541_E || + ver == SVR_8555 || ver == SVR_8555_E) { puts("256 KB "); /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ cache_ctl = 0xc8000000; + } else { + puts ("512 KB "); + /* set L2E=1, L2I=1, & L2SRAM=0 */ + cache_ctl = 0xc0000000; } break; - case 0x10000000: - puts("256 KB "); - if (ver == SVR_8544 || ver == SVR_8544_E) { - cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ - } + case 0x3: + puts("1024 KB "); + /* set L2E=1, L2I=1, & L2SRAM=0 */ + cache_ctl = 0xc0000000; break; - case 0x30000000: - case 0x00000000: - default: - printf(" unknown size (0x%08x)\n", cache_ctl); - return -1; } if (l2cache->l2ctl & 0x80000000) { -- cgit v1.2.1