From 9343dbf85bc03033f2102d8e8543567c2c1ad2d2 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Sat, 24 Feb 2007 01:16:45 -0600 Subject: Tweak DDR ECC error counter Enable single-bit error counter when memory was cleared by ddr controller. Signed-off-by: Ed Swarthout Signed-off-by: Andy Fleming --- cpu/mpc85xx/spd_sdram.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'cpu/mpc85xx/spd_sdram.c') diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 6da5367a70..4b3c4eb706 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -786,14 +786,17 @@ spd_sdram(void) * Is this an ECC DDR chip? * But don't mess with it if the DDR controller will init mem. */ -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +#ifdef CONFIG_DDR_ECC if (spd.config == 0x02) { +#ifndef CONFIG_ECC_INIT_VIA_DDRCONTROLLER ddr->err_disable = 0x0000000d; +#endif ddr->err_sbe = 0x00ff0000; } + debug("DDR: err_disable = 0x%08x\n", ddr->err_disable); debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe); -#endif +#endif /* CONFIG_DDR_ECC */ asm("sync;isync;msync"); udelay(500); -- cgit v1.2.1 From 1f9a318cea14272edd10d63739e2d326c90f430e Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Fri, 23 Feb 2007 16:28:46 -0600 Subject: Only set ddrioovcr for 8548 rev1. Signed-off-by: Ed Swarthout Signed-off-by: Andy Fleming --- cpu/mpc85xx/spd_sdram.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) (limited to 'cpu/mpc85xx/spd_sdram.c') diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 4b3c4eb706..16a697d40c 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -263,13 +263,14 @@ spd_sdram(void) } /* - * Adjust DDR II IO voltage biasing. It just makes it work. + * Adjust DDR II IO voltage biasing. + * Only 8548 rev 1 needs the fix */ - if (spd.mem_type == SPD_MEMTYPE_DDR2) { - gur->ddrioovcr = (0 - | 0x80000000 /* Enable */ - | 0x10000000 /* VSEL to 1.8V */ - ); + if ((SVR_VER(get_svr()) == SVR_8548_E) && + (SVR_MJREV(get_svr()) == 1) && + (spd.mem_type == SPD_MEMTYPE_DDR2)) { + gur->ddrioovcr = (0x80000000 /* Enable */ + | 0x10000000);/* VSEL to 1.8V */ } /* -- cgit v1.2.1 From 0d8c3a2096eaff8d7de89d45e9af4d4b0d4868fe Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Fri, 23 Feb 2007 17:12:25 -0600 Subject: Support 1G size on 8548 e500v2 and newer cores support 1G page sizes. Signed-off-by: Ed Swarthout Signed-off-by: Andy Fleming --- cpu/mpc85xx/spd_sdram.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'cpu/mpc85xx/spd_sdram.c') diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 16a697d40c..3777f49adc 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -995,17 +995,24 @@ setup_laws_and_tlbs(unsigned int memsize) break; case 256: case 512: + tlb_size = BOOKE_PAGESZ_256M; + break; case 1024: case 2048: - tlb_size = BOOKE_PAGESZ_256M; + if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx)) + tlb_size = BOOKE_PAGESZ_1G; + else + tlb_size = BOOKE_PAGESZ_256M; break; default: puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G are supported.\n"); /* * The memory was not able to be mapped. + * Default to a small size. */ - return 0; + tlb_size = BOOKE_PAGESZ_64M; + memsize=64; break; } -- cgit v1.2.1