From 3c2a67eec8a0facc865b400caca52e7f6b7adf01 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 17 Sep 2009 01:52:37 -0500 Subject: ppc/p4080: Handle timebase enabling and frequency reporting On CoreNet style platforms the timebase frequency is the bus frequency defined by 16 (on PQ3 it is divide by 8). Also on the CoreNet platforms the core not longer controls the enabling of the timebase. We now need to enable the boot core's timebase via CCSR register writes. Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'cpu/mpc85xx/cpu.c') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index bdd9ee4c83..25c04169fd 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -184,7 +184,11 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) */ unsigned long get_tbclk (void) { +#ifdef CONFIG_FSL_CORENET + return (gd->bus_clk + 8) / 16; +#else return (gd->bus_clk + 4UL)/8UL; +#endif } -- cgit v1.2.1