From 8d1e3cb14009d3fb4752489e02ae1a88d75e6b0b Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 23 Jan 2015 00:24:15 +0900 Subject: powerpc: mpc83xx: remove MPC8360ERDK, EMPC8360EMDS support These boards are still non-generic boards. Signed-off-by: Masahiro Yamada Cc: Dave Liu Cc: Anton Vorontsov --- board/freescale/common/pq-mds-pib.c | 2 +- board/freescale/mpc8360emds/Kconfig | 12 - board/freescale/mpc8360emds/MAINTAINERS | 15 - board/freescale/mpc8360emds/Makefile | 9 - board/freescale/mpc8360emds/README | 155 ---------- board/freescale/mpc8360emds/mpc8360emds.c | 453 ------------------------------ board/freescale/mpc8360emds/pci.c | 147 ---------- board/freescale/mpc8360erdk/Kconfig | 12 - board/freescale/mpc8360erdk/MAINTAINERS | 7 - board/freescale/mpc8360erdk/Makefile | 9 - board/freescale/mpc8360erdk/mpc8360erdk.c | 350 ----------------------- board/freescale/mpc8360erdk/nand.c | 89 ------ 12 files changed, 1 insertion(+), 1259 deletions(-) delete mode 100644 board/freescale/mpc8360emds/Kconfig delete mode 100644 board/freescale/mpc8360emds/MAINTAINERS delete mode 100644 board/freescale/mpc8360emds/Makefile delete mode 100644 board/freescale/mpc8360emds/README delete mode 100644 board/freescale/mpc8360emds/mpc8360emds.c delete mode 100644 board/freescale/mpc8360emds/pci.c delete mode 100644 board/freescale/mpc8360erdk/Kconfig delete mode 100644 board/freescale/mpc8360erdk/MAINTAINERS delete mode 100644 board/freescale/mpc8360erdk/Makefile delete mode 100644 board/freescale/mpc8360erdk/mpc8360erdk.c delete mode 100644 board/freescale/mpc8360erdk/nand.c (limited to 'board') diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c index 5f7a67d057..1eb37866e3 100644 --- a/board/freescale/common/pq-mds-pib.c +++ b/board/freescale/common/pq-mds-pib.c @@ -63,7 +63,7 @@ int pib_init(void) #endif #if defined(CONFIG_PQ_MDS_PIB_ATM) -#if defined(CONFIG_MPC8360EMDS) || defined(CONFIG_MPC8569MDS) +#if defined(CONFIG_MPC8569MDS) val8 = 0; i2c_write(0x20, 0x6, 1, &val8, 1); i2c_write(0x20, 0x7, 1, &val8, 1); diff --git a/board/freescale/mpc8360emds/Kconfig b/board/freescale/mpc8360emds/Kconfig deleted file mode 100644 index 3f4f95cac2..0000000000 --- a/board/freescale/mpc8360emds/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8360EMDS - -config SYS_BOARD - default "mpc8360emds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8360EMDS" - -endif diff --git a/board/freescale/mpc8360emds/MAINTAINERS b/board/freescale/mpc8360emds/MAINTAINERS deleted file mode 100644 index 91ff2ef4e8..0000000000 --- a/board/freescale/mpc8360emds/MAINTAINERS +++ /dev/null @@ -1,15 +0,0 @@ -MPC8360EMDS BOARD -M: Dave Liu -S: Maintained -F: board/freescale/mpc8360emds/ -F: include/configs/MPC8360EMDS.h -F: configs/MPC8360EMDS_33_defconfig -F: configs/MPC8360EMDS_33_ATM_defconfig -F: configs/MPC8360EMDS_33_HOST_33_defconfig -F: configs/MPC8360EMDS_33_HOST_66_defconfig -F: configs/MPC8360EMDS_33_SLAVE_defconfig -F: configs/MPC8360EMDS_66_defconfig -F: configs/MPC8360EMDS_66_ATM_defconfig -F: configs/MPC8360EMDS_66_HOST_33_defconfig -F: configs/MPC8360EMDS_66_HOST_66_defconfig -F: configs/MPC8360EMDS_66_SLAVE_defconfig diff --git a/board/freescale/mpc8360emds/Makefile b/board/freescale/mpc8360emds/Makefile deleted file mode 100644 index e8332cea3f..0000000000 --- a/board/freescale/mpc8360emds/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += mpc8360emds.o -obj-$(CONFIG_PCI) += pci.o diff --git a/board/freescale/mpc8360emds/README b/board/freescale/mpc8360emds/README deleted file mode 100644 index 6afa753969..0000000000 --- a/board/freescale/mpc8360emds/README +++ /dev/null @@ -1,155 +0,0 @@ -Freescale MPC8360EMDS Board ------------------------------------------ -1. Board Switches and Jumpers -1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC8360EMDS board - For some reason, the HW designers describe the switch settings - in terms of 0 and 1, and then map that to physical switches where - the label "On" refers to logic 0 and "Off" is logic 1. - - Switch bits are numbered 1 through, like, 4 6 8 or 10, but the - bits may contribute to signals that are numbered based at 0, - and some of those signals may be high-bit-number-0 too. Heed - well the names and labels and do not get confused. - - "Off" == 1 - "On" == 0 - - SW18 is switch 18 as silk-screened onto the board. - SW4[8] is the bit labeled 8 on Switch 4. - SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2. - SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3. - SW3[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On" - and bits labeled 8 is set as "Off". - -1.1 There are three type boards for MPC8360E silicon up to now, They are - - * MPC8360E-MDS-PB PROTO (a.k.a 8360SYS PROTOTYPE) - * MPC8360E-MDS-PB PILOT (a.k.a 8360SYS PILOT) - * MPC8360EA-MDS-PB PROTO (a.k.a 8360SYS2 PROTOTYPE) - -1.2 For all the MPC8360EMDS Board - - First, make sure the board default setting is consistent with the - document shipped with your board. Then apply the following setting: - SW3[1-8]= 0000_0100 (HRCW setting value is performed on local bus) - SW4[1-8]= 0011_0000 (Flash boot on local bus) - SW9[1-8]= 0110_0110 (PCI Mode enabled. HRCW is read from FLASH) - SW10[1-8]= 0000_1000 (core PLL setting) - SW11[1-8]= 0000_0100 (SW11 is on the another side of the board) - JP6 1-2 - on board Oscillator: 66M - -1.3 Since different board/chip rev. combinations have AC timing issues, - u-boot forces RGMII-ID (RGMII with Internal Delay) mode on by default - by the patch (mpc83xx: Disable G1TXCLK, G2TXCLK h/w buffers). - - When the rev2.x silicon mount on these boards, and if you are using - u-boot version after this patch, to make the ethernet interfaces usable, - and to enable RGMII-ID on your board, you have to setup the jumpers - correctly. - - * MPC8360E-MDS-PB PROTO - nothing to do - * MPC8360E-MDS-PB PILOT - JP9 and JP8 should be ON - * MPC8360EA-MDS-PB PROTO - JP2 and JP3 should be ON - -2. Memory Map - -2.1. The memory map should look pretty much like this: - - 0x0000_0000 0x7fff_ffff DDR 2G - 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M - 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M - 0xc000_0000 0xdfff_ffff Empty 512M - 0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M - 0xe020_0000 0xe02f_ffff Empty 1M - 0xe030_0000 0xe03f_ffff PCI IO 1M - 0xe040_0000 0xefff_ffff Empty 252M - 0xf000_0000 0xf3ff_ffff Local Bus SDRAM 64M - 0xf400_0000 0xf7ff_ffff Empty 64M - 0xf800_0000 0xf800_7fff BCSR on CS1 32K - 0xf800_8000 0xf800_ffff PIB CS4 32K - 0xf801_0000 0xf801_7fff PIB CS5 32K - 0xfe00_0000 0xfeff_ffff FLASH on CS0 16M - - -3. Definitions - -3.1 Explanation of NEW definitions in: - - include/configs/MPC8360EMDS.h - - CONFIG_MPC83xx MPC83xx family for both MPC8349 and MPC8360 - CONFIG_MPC8360 MPC8360 specific - CONFIG_MPC8360EMDS MPC8360EMDS board specific - -4. Compilation - - MPC8360EMDS shipped with 33.33MHz or 66MHz oscillator(check U41 chip). - - Assuming you're using BASH shell: - - export CROSS_COMPILE=your-cross-compile-prefix - cd u-boot - make distclean - make MPC8360EMDS_XX_config - make - - MPC8360EMDS support ATM, PCI in host and slave mode. - - To make u-boot support ATM : - 1) Make MPC8360EMDS_XX_ATM_config - - To make u-boot support PCI host 66M : - 1) DIP SW support PCI mode as described in Section 1.1. - 2) Make MPC8360EMDS_XX_HOST_66_config - - To make u-boot support PCI host 33M : - 1) DIP SW setting is similar as Section 1.1, except for SW3[4] is 1 - 2) Make MPC8360EMDS_XX_HOST_33_config - - To make u-boot support PCI slave 66M : - 1) DIP SW setting is similar as Section 1.1, except for SW9[3] is 1 - 2) Make MPC8360EMDS_XX_SLAVE_config - - (where XX is: - 33 - 33.33MHz oscillator - 66 - 66MHz oscillator) - -5. Downloading and Flashing Images - -5.0 Download over serial line using Kermit: - - loadb - [Drop to kermit: - ^\c - send - c - ] - - - Or via tftp: - - tftp 10000 u-boot.bin - -5.1 Reflash U-boot Image using U-boot - - tftp 20000 u-boot.bin - protect off fef00000 fef3ffff - erase fef00000 fef3ffff - - cp.b 20000 fef00000 xxxx - - or - - cp.b 20000 fef00000 3ffff - - -You have to supply the correct byte count with 'xxxx' from the TFTP result log. -Maybe 3ffff will work too, that corresponds to the erased sectors. - - -6. Notes - 1) The console baudrate for MPC8360EMDS is 115200bps. diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c deleted file mode 100644 index f0a55f8a8d..0000000000 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ /dev/null @@ -1,453 +0,0 @@ -/* - * Copyright (C) 2006,2010-2011 Freescale Semiconductor, Inc. - * Dave Liu - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#if defined(CONFIG_PCI) -#include -#endif -#include -#include -#include -#include -#if defined(CONFIG_OF_LIBFDT) -#include -#endif -#include -#include -#if defined(CONFIG_PQ_MDS_PIB) -#include "../common/pq-mds-pib.h" -#endif -#include "../../../drivers/qe/uec.h" - -const qe_iop_conf_t qe_iop_conf_tab[] = { - /* GETH1 */ - {0, 3, 1, 0, 1}, /* TxD0 */ - {0, 4, 1, 0, 1}, /* TxD1 */ - {0, 5, 1, 0, 1}, /* TxD2 */ - {0, 6, 1, 0, 1}, /* TxD3 */ - {1, 6, 1, 0, 3}, /* TxD4 */ - {1, 7, 1, 0, 1}, /* TxD5 */ - {1, 9, 1, 0, 2}, /* TxD6 */ - {1, 10, 1, 0, 2}, /* TxD7 */ - {0, 9, 2, 0, 1}, /* RxD0 */ - {0, 10, 2, 0, 1}, /* RxD1 */ - {0, 11, 2, 0, 1}, /* RxD2 */ - {0, 12, 2, 0, 1}, /* RxD3 */ - {0, 13, 2, 0, 1}, /* RxD4 */ - {1, 1, 2, 0, 2}, /* RxD5 */ - {1, 0, 2, 0, 2}, /* RxD6 */ - {1, 4, 2, 0, 2}, /* RxD7 */ - {0, 7, 1, 0, 1}, /* TX_EN */ - {0, 8, 1, 0, 1}, /* TX_ER */ - {0, 15, 2, 0, 1}, /* RX_DV */ - {0, 16, 2, 0, 1}, /* RX_ER */ - {0, 0, 2, 0, 1}, /* RX_CLK */ - {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */ - {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */ - /* GETH2 */ - {0, 17, 1, 0, 1}, /* TxD0 */ - {0, 18, 1, 0, 1}, /* TxD1 */ - {0, 19, 1, 0, 1}, /* TxD2 */ - {0, 20, 1, 0, 1}, /* TxD3 */ - {1, 2, 1, 0, 1}, /* TxD4 */ - {1, 3, 1, 0, 2}, /* TxD5 */ - {1, 5, 1, 0, 3}, /* TxD6 */ - {1, 8, 1, 0, 3}, /* TxD7 */ - {0, 23, 2, 0, 1}, /* RxD0 */ - {0, 24, 2, 0, 1}, /* RxD1 */ - {0, 25, 2, 0, 1}, /* RxD2 */ - {0, 26, 2, 0, 1}, /* RxD3 */ - {0, 27, 2, 0, 1}, /* RxD4 */ - {1, 12, 2, 0, 2}, /* RxD5 */ - {1, 13, 2, 0, 3}, /* RxD6 */ - {1, 11, 2, 0, 2}, /* RxD7 */ - {0, 21, 1, 0, 1}, /* TX_EN */ - {0, 22, 1, 0, 1}, /* TX_ER */ - {0, 29, 2, 0, 1}, /* RX_DV */ - {0, 30, 2, 0, 1}, /* RX_ER */ - {0, 31, 2, 0, 1}, /* RX_CLK */ - {2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */ - {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */ - - {0, 1, 3, 0, 2}, /* MDIO */ - {0, 2, 1, 0, 1}, /* MDC */ - - {5, 0, 1, 0, 2}, /* UART2_SOUT */ - {5, 1, 2, 0, 3}, /* UART2_CTS */ - {5, 2, 1, 0, 1}, /* UART2_RTS */ - {5, 3, 2, 0, 2}, /* UART2_SIN */ - - {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ -}; - -/* Handle "mpc8360ea rev.2.1 erratum 2: RGMII Timing"? */ -static int board_handle_erratum2(void) -{ - const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - - return REVID_MAJOR(immr->sysconf.spridr) == 2 && - REVID_MINOR(immr->sysconf.spridr) == 1; -} - -int board_early_init_f(void) -{ - const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - u8 *bcsr = (u8 *)CONFIG_SYS_BCSR; - - /* Enable flash write */ - bcsr[0xa] &= ~0x04; - - /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */ - if (REVID_MAJOR(immr->sysconf.spridr) == 2) - bcsr[0xe] = 0x30; - - /* Enable second UART */ - bcsr[0x9] &= ~0x01; - - if (board_handle_erratum2()) { - void *immap = (immap_t *)(CONFIG_SYS_IMMR + 0x14a8); - - /* - * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) - * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) - */ - setbits_be32(immap, 0x0c003000); - - /* - * IMMR + 0x14AC[20:27] = 10101010 - * (data delay for both UCC's) - */ - clrsetbits_be32(immap + 4, 0xff0, 0xaa0); - } - return 0; -} - -int board_early_init_r(void) -{ - gd_t *gd; -#ifdef CONFIG_PQ_MDS_PIB - pib_init(); -#endif - /* - * BAT6 is used for SDRAM when DDR size is 512MB or larger than 256MB - * So re-setup PCI MEM space used BAT5 after relocated to DDR - */ - gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { - write_bat(DBAT5, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L); - write_bat(IBAT5, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L); - } - - return 0; -} - -#ifdef CONFIG_UEC_ETH -static uec_info_t uec_info[] = { -#ifdef CONFIG_UEC_ETH1 - STD_UEC_INFO(1), -#endif -#ifdef CONFIG_UEC_ETH2 - STD_UEC_INFO(2), -#endif -}; - -int board_eth_init(bd_t *bd) -{ - if (board_handle_erratum2()) { - int i; - - for (i = 0; i < ARRAY_SIZE(uec_info); i++) { - uec_info[i].enet_interface_type = - PHY_INTERFACE_MODE_RGMII_RXID; - uec_info[i].speed = SPEED_1000; - } - } - return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info)); -} -#endif /* CONFIG_UEC_ETH */ - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif -int fixed_sdram(void); -static int sdram_init(unsigned int base); - -phys_size_t initdram(int board_type) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = 0; - u32 lbc_sdram_size; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) - return -1; - - /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; -#if defined(CONFIG_SPD_EEPROM) - msize = spd_sdram(); -#else - msize = fixed_sdram(); -#endif - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize DDR ECC byte - */ - ddr_enable_ecc(msize * 1024 * 1024); -#endif - /* - * Initialize SDRAM if it is on local bus. - */ - lbc_sdram_size = sdram_init(msize * 1024 * 1024); - if (!msize) - msize = lbc_sdram_size; - - /* return total bus SDRAM size(bytes) -- DDR */ - return (msize * 1024 * 1024); -} - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = CONFIG_SYS_DDR_SIZE; - u32 ddr_size = msize << 20; - u32 ddr_size_log2 = __ilog2(ddr_size); - u32 half_ddr_size = ddr_size >> 1; - - im->sysconf.ddrlaw[0].bar = - CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; - im->sysconf.ddrlaw[0].ar = - LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); -#if (CONFIG_SYS_DDR_SIZE != 256) -#warning Currenly any ddr size other than 256 is not supported -#endif -#ifdef CONFIG_DDR_II - im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; -#else - -#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) -#warning Chip select bounds is only configurable in 16MB increments -#endif - im->ddr.csbnds[0].csbnds = - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size - 1) >> - CSBNDS_EA_SHIFT) & CSBNDS_EA); - im->ddr.csbnds[1].csbnds = - (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size) >> - CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> - CSBNDS_EA_SHIFT) & CSBNDS_EA); - - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; - im->ddr.cs_config[1] = CONFIG_SYS_DDR_CS1_CONFIG; - - im->ddr.cs_config[2] = 0; - im->ddr.cs_config[3] = 0; - - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONTROL; - - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; -#endif - udelay(200); - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - - return msize; -} -#endif /*!CONFIG_SYS_SPD_EEPROM */ - -int checkboard(void) -{ - puts("Board: Freescale MPC8360EMDS\n"); - return 0; -} - -/* - * if MPC8360EMDS is soldered with SDRAM - */ -#ifdef CONFIG_SYS_LB_SDRAM -/* - * Initialize SDRAM memory on the Local Bus. - */ - -static int sdram_init(unsigned int base) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - fsl_lbc_t *lbc = LBC_BASE_ADDR; - const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024; - int rem = base % sdram_size; - uint *sdram_addr; - - /* window base address should be aligned to the window size */ - if (rem) - base = base - rem + sdram_size; - - /* - * Setup BAT6 for SDRAM when DDR size is 512MB or larger than 256MB - * After relocated to DDR, reuse BAT5 for PCI MEM space - */ - if (base > CONFIG_MAX_MEM_MAPPED) { - unsigned long batl = base | BATL_PP_10 | BATL_MEMCOHERENCE; - unsigned long batu = base | BATU_BL_64M | BATU_VS | BATU_VP; - - /* Setup the BAT6 for SDRAM */ - write_bat(DBAT6, batu, batl); - write_bat(IBAT6, batu, batl); - } - - sdram_addr = (uint *)base; - /* - * Setup SDRAM Base and Option Registers - */ - set_lbc_br(2, base | CONFIG_SYS_BR2); - set_lbc_or(2, CONFIG_SYS_OR2); - immap->sysconf.lblaw[2].bar = base; - immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2; - - /*setup mtrpt, lsrt and lbcr for LB bus */ - lbc->lbcr = CONFIG_SYS_LBC_LBCR; - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; - lbc->lsrt = CONFIG_SYS_LBC_LSRT; - asm("sync"); - - /* - * Configure the SDRAM controller Machine Mode Register. - */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* Normal Operation */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* Precharge All Banks */ - asm("sync"); - *sdram_addr = 0xff; - udelay(100); - - /* - * We need do 8 times auto refresh operation. - */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; - asm("sync"); - *sdram_addr = 0xff; /* 1 times */ - udelay(100); - *sdram_addr = 0xff; /* 2 times */ - udelay(100); - *sdram_addr = 0xff; /* 3 times */ - udelay(100); - *sdram_addr = 0xff; /* 4 times */ - udelay(100); - *sdram_addr = 0xff; /* 5 times */ - udelay(100); - *sdram_addr = 0xff; /* 6 times */ - udelay(100); - *sdram_addr = 0xff; /* 7 times */ - udelay(100); - *sdram_addr = 0xff; /* 8 times */ - udelay(100); - - /* Mode register write operation */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; - asm("sync"); - *(sdram_addr + 0xcc) = 0xff; - udelay(100); - - /* Normal operation */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5 | 0x40000000; - asm("sync"); - *sdram_addr = 0xff; - udelay(100); - - /* - * In non-aligned case we don't [normally] use that memory because - * there is a hole. - */ - if (rem) - return 0; - return CONFIG_SYS_LBC_SDRAM_SIZE; -} -#else -static int sdram_init(unsigned int base) { return 0; } -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) -static void ft_board_fixup_qe_usb(void *blob, bd_t *bd) -{ - if (!hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) - return; - - do_fixup_by_compat(blob, "fsl,mpc8323-qe-usb", "mode", - "peripheral", sizeof("peripheral"), 1); -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - ft_board_fixup_qe_usb(blob, bd); - /* - * mpc8360ea pb mds errata 2: RGMII timing - * if on mpc8360ea rev. 2.1, - * change both ucc phy-connection-types from rgmii-id to rgmii-rxid - */ - if (board_handle_erratum2()) { - int nodeoffset; - const char *prop; - int path; - - nodeoffset = fdt_path_offset(blob, "/aliases"); - if (nodeoffset >= 0) { -#if defined(CONFIG_HAS_ETH0) - /* fixup UCC 1 if using rgmii-id mode */ - prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL); - if (prop) { - path = fdt_path_offset(blob, prop); - prop = fdt_getprop(blob, path, - "phy-connection-type", 0); - if (prop && (strcmp(prop, "rgmii-id") == 0)) - fdt_fixup_phy_connection(blob, path, - PHY_INTERFACE_MODE_RGMII_RXID); - } -#endif -#if defined(CONFIG_HAS_ETH1) - /* fixup UCC 2 if using rgmii-id mode */ - prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL); - if (prop) { - path = fdt_path_offset(blob, prop); - prop = fdt_getprop(blob, path, - "phy-connection-type", 0); - if (prop && (strcmp(prop, "rgmii-id") == 0)) - fdt_fixup_phy_connection(blob, path, - PHY_INTERFACE_MODE_RGMII_RXID); - } -#endif - } - } - - return 0; -} -#endif diff --git a/board/freescale/mpc8360emds/pci.c b/board/freescale/mpc8360emds/pci.c deleted file mode 100644 index 71244df079..0000000000 --- a/board/freescale/mpc8360emds/pci.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * PCI Configuration space access support for MPC83xx PCI Bridge - */ - -#include -#include -#include -#include -#include -#include -#include -#include "../common/pq-mds-pib.h" - -DECLARE_GLOBAL_DATA_PTR; - -static struct pci_region pci1_regions[] = { - { - bus_start: CONFIG_SYS_PCI1_MEM_BASE, - phys_start: CONFIG_SYS_PCI1_MEM_PHYS, - size: CONFIG_SYS_PCI1_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI1_IO_BASE, - phys_start: CONFIG_SYS_PCI1_IO_PHYS, - size: CONFIG_SYS_PCI1_IO_SIZE, - flags: PCI_REGION_IO - }, - { - bus_start: CONFIG_SYS_PCI1_MMIO_BASE, - phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, - size: CONFIG_SYS_PCI1_MMIO_SIZE, - flags: PCI_REGION_MEM - }, -}; - -#ifdef CONFIG_MPC83XX_PCI2 -static struct pci_region pci2_regions[] = { - { - bus_start: CONFIG_SYS_PCI2_MEM_BASE, - phys_start: CONFIG_SYS_PCI2_MEM_PHYS, - size: CONFIG_SYS_PCI2_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI2_IO_BASE, - phys_start: CONFIG_SYS_PCI2_IO_PHYS, - size: CONFIG_SYS_PCI2_IO_SIZE, - flags: PCI_REGION_IO - }, - { - bus_start: CONFIG_SYS_PCI2_MMIO_BASE, - phys_start: CONFIG_SYS_PCI2_MMIO_PHYS, - size: CONFIG_SYS_PCI2_MMIO_SIZE, - flags: PCI_REGION_MEM - }, -}; -#endif - -void pci_init_board(void) -#ifdef CONFIG_PCISLAVE -{ - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; - volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0]; - struct pci_region *reg[] = { pci1_regions }; - - /* Configure PCI Local Access Windows */ - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; - - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; - - mpc83xx_pci_init(1, reg); - - /* - * Configure PCI Inbound Translation Windows - */ - pci_ctrl[0].pitar0 = 0x0; - pci_ctrl[0].pibar0 = 0x0; - pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP | - PIWAR_WTT_SNOOP | PIWAR_IWS_4K; - - pci_ctrl[0].pitar1 = 0x0; - pci_ctrl[0].pibar1 = 0x0; - pci_ctrl[0].piebar1 = 0x0; - pci_ctrl[0].piwar1 &= ~PIWAR_EN; - - pci_ctrl[0].pitar2 = 0x0; - pci_ctrl[0].pibar2 = 0x0; - pci_ctrl[0].piebar2 = 0x0; - pci_ctrl[0].piwar2 &= ~PIWAR_EN; - - /* Unlock the configuration bit */ - mpc83xx_pcislave_unlock(0); - printf("PCI: Agent mode enabled\n"); -} -#else -{ - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; -#ifndef CONFIG_MPC83XX_PCI2 - struct pci_region *reg[] = { pci1_regions }; -#else - struct pci_region *reg[] = { pci1_regions, pci2_regions }; -#endif - - /* initialize the PCA9555PW IO expander on the PIB board */ - pib_init(); - -#if defined(CONFIG_PCI_66M) - clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; - printf("PCI clock is 66MHz\n"); -#elif defined(CONFIG_PCI_33M) - clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 | - OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR; - printf("PCI clock is 33MHz\n"); -#else - clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; - printf("PCI clock is 66MHz\n"); -#endif - udelay(2000); - - /* Configure PCI Local Access Windows */ - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; - - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; - - udelay(2000); - -#ifndef CONFIG_MPC83XX_PCI2 - mpc83xx_pci_init(1, reg); -#else - mpc83xx_pci_init(2, reg); -#endif -} -#endif /* CONFIG_PCISLAVE */ diff --git a/board/freescale/mpc8360erdk/Kconfig b/board/freescale/mpc8360erdk/Kconfig deleted file mode 100644 index 5c9be7c9c1..0000000000 --- a/board/freescale/mpc8360erdk/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8360ERDK - -config SYS_BOARD - default "mpc8360erdk" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8360ERDK" - -endif diff --git a/board/freescale/mpc8360erdk/MAINTAINERS b/board/freescale/mpc8360erdk/MAINTAINERS deleted file mode 100644 index e5b5995f78..0000000000 --- a/board/freescale/mpc8360erdk/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -MPC8360ERDK BOARD -#M: Anton Vorontsov -S: Orphan (since 2014-03) -F: board/freescale/mpc8360erdk/ -F: include/configs/MPC8360ERDK.h -F: configs/MPC8360ERDK_defconfig -F: configs/MPC8360ERDK_33_defconfig diff --git a/board/freescale/mpc8360erdk/Makefile b/board/freescale/mpc8360erdk/Makefile deleted file mode 100644 index e2235c28fe..0000000000 --- a/board/freescale/mpc8360erdk/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += mpc8360erdk.o -obj-$(CONFIG_CMD_NAND) += nand.o diff --git a/board/freescale/mpc8360erdk/mpc8360erdk.c b/board/freescale/mpc8360erdk/mpc8360erdk.c deleted file mode 100644 index 478f8205a9..0000000000 --- a/board/freescale/mpc8360erdk/mpc8360erdk.c +++ /dev/null @@ -1,350 +0,0 @@ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * Dave Liu - * - * Copyright (C) 2007 Logic Product Development, Inc. - * Peter Barada - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -const qe_iop_conf_t qe_iop_conf_tab[] = { - /* MDIO */ - {0, 1, 3, 0, 2}, /* MDIO */ - {0, 2, 1, 0, 1}, /* MDC */ - - /* UCC1 - UEC (Gigabit) */ - {0, 3, 1, 0, 1}, /* TxD0 */ - {0, 4, 1, 0, 1}, /* TxD1 */ - {0, 5, 1, 0, 1}, /* TxD2 */ - {0, 6, 1, 0, 1}, /* TxD3 */ - {0, 9, 2, 0, 1}, /* RxD0 */ - {0, 10, 2, 0, 1}, /* RxD1 */ - {0, 11, 2, 0, 1}, /* RxD2 */ - {0, 12, 2, 0, 1}, /* RxD3 */ - {0, 7, 1, 0, 1}, /* TX_EN */ - {0, 8, 1, 0, 1}, /* TX_ER */ - {0, 15, 2, 0, 1}, /* RX_DV */ - {0, 0, 2, 0, 1}, /* RX_CLK */ - {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */ - {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */ - - /* UCC2 - UEC (Gigabit) */ - {0, 17, 1, 0, 1}, /* TxD0 */ - {0, 18, 1, 0, 1}, /* TxD1 */ - {0, 19, 1, 0, 1}, /* TxD2 */ - {0, 20, 1, 0, 1}, /* TxD3 */ - {0, 23, 2, 0, 1}, /* RxD0 */ - {0, 24, 2, 0, 1}, /* RxD1 */ - {0, 25, 2, 0, 1}, /* RxD2 */ - {0, 26, 2, 0, 1}, /* RxD3 */ - {0, 21, 1, 0, 1}, /* TX_EN */ - {0, 22, 1, 0, 1}, /* TX_ER */ - {0, 29, 2, 0, 1}, /* RX_DV */ - {0, 31, 2, 0, 1}, /* RX_CLK */ - {2, 2, 1, 0, 2}, /* GTX_CLK - CLK10 */ - {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */ - - /* UCC7 - UEC */ - {4, 0, 1, 0, 1}, /* TxD0 */ - {4, 1, 1, 0, 1}, /* TxD1 */ - {4, 2, 1, 0, 1}, /* TxD2 */ - {4, 3, 1, 0, 1}, /* TxD3 */ - {4, 6, 2, 0, 1}, /* RxD0 */ - {4, 7, 2, 0, 1}, /* RxD1 */ - {4, 8, 2, 0, 1}, /* RxD2 */ - {4, 9, 2, 0, 1}, /* RxD3 */ - {4, 4, 1, 0, 1}, /* TX_EN */ - {4, 5, 1, 0, 1}, /* TX_ER */ - {4, 12, 2, 0, 1}, /* RX_DV */ - {4, 13, 2, 0, 1}, /* RX_ER */ - {4, 10, 2, 0, 1}, /* COL */ - {4, 11, 2, 0, 1}, /* CRS */ - {2, 18, 2, 0, 1}, /* TX_CLK - CLK19 */ - {2, 19, 2, 0, 1}, /* RX_CLK - CLK20 */ - - /* UCC4 - UEC */ - {1, 14, 1, 0, 1}, /* TxD0 */ - {1, 15, 1, 0, 1}, /* TxD1 */ - {1, 16, 1, 0, 1}, /* TxD2 */ - {1, 17, 1, 0, 1}, /* TxD3 */ - {1, 20, 2, 0, 1}, /* RxD0 */ - {1, 21, 2, 0, 1}, /* RxD1 */ - {1, 22, 2, 0, 1}, /* RxD2 */ - {1, 23, 2, 0, 1}, /* RxD3 */ - {1, 18, 1, 0, 1}, /* TX_EN */ - {1, 19, 1, 0, 2}, /* TX_ER */ - {1, 26, 2, 0, 1}, /* RX_DV */ - {1, 27, 2, 0, 1}, /* RX_ER */ - {1, 24, 2, 0, 1}, /* COL */ - {1, 25, 2, 0, 1}, /* CRS */ - {2, 6, 2, 0, 1}, /* TX_CLK - CLK7 */ - {2, 7, 2, 0, 1}, /* RX_CLK - CLK8 */ - - /* PCI1 */ - {5, 4, 2, 0, 3}, /* PCI_M66EN */ - {5, 5, 1, 0, 3}, /* PCI_INTA */ - {5, 6, 1, 0, 3}, /* PCI_RSTO */ - {5, 7, 3, 0, 3}, /* PCI_C_BE0 */ - {5, 8, 3, 0, 3}, /* PCI_C_BE1 */ - {5, 9, 3, 0, 3}, /* PCI_C_BE2 */ - {5, 10, 3, 0, 3}, /* PCI_C_BE3 */ - {5, 11, 3, 0, 3}, /* PCI_PAR */ - {5, 12, 3, 0, 3}, /* PCI_FRAME */ - {5, 13, 3, 0, 3}, /* PCI_TRDY */ - {5, 14, 3, 0, 3}, /* PCI_IRDY */ - {5, 15, 3, 0, 3}, /* PCI_STOP */ - {5, 16, 3, 0, 3}, /* PCI_DEVSEL */ - {5, 17, 0, 0, 0}, /* PCI_IDSEL */ - {5, 18, 3, 0, 3}, /* PCI_SERR */ - {5, 19, 3, 0, 3}, /* PCI_PERR */ - {5, 20, 3, 0, 3}, /* PCI_REQ0 */ - {5, 21, 2, 0, 3}, /* PCI_REQ1 */ - {5, 22, 2, 0, 3}, /* PCI_GNT2 */ - {5, 23, 3, 0, 3}, /* PCI_GNT0 */ - {5, 24, 1, 0, 3}, /* PCI_GNT1 */ - {5, 25, 1, 0, 3}, /* PCI_GNT2 */ - {5, 26, 0, 0, 0}, /* PCI_CLK0 */ - {5, 27, 0, 0, 0}, /* PCI_CLK1 */ - {5, 28, 0, 0, 0}, /* PCI_CLK2 */ - {5, 29, 0, 0, 3}, /* PCI_SYNC_OUT */ - {6, 0, 3, 0, 3}, /* PCI_AD0 */ - {6, 1, 3, 0, 3}, /* PCI_AD1 */ - {6, 2, 3, 0, 3}, /* PCI_AD2 */ - {6, 3, 3, 0, 3}, /* PCI_AD3 */ - {6, 4, 3, 0, 3}, /* PCI_AD4 */ - {6, 5, 3, 0, 3}, /* PCI_AD5 */ - {6, 6, 3, 0, 3}, /* PCI_AD6 */ - {6, 7, 3, 0, 3}, /* PCI_AD7 */ - {6, 8, 3, 0, 3}, /* PCI_AD8 */ - {6, 9, 3, 0, 3}, /* PCI_AD9 */ - {6, 10, 3, 0, 3}, /* PCI_AD10 */ - {6, 11, 3, 0, 3}, /* PCI_AD11 */ - {6, 12, 3, 0, 3}, /* PCI_AD12 */ - {6, 13, 3, 0, 3}, /* PCI_AD13 */ - {6, 14, 3, 0, 3}, /* PCI_AD14 */ - {6, 15, 3, 0, 3}, /* PCI_AD15 */ - {6, 16, 3, 0, 3}, /* PCI_AD16 */ - {6, 17, 3, 0, 3}, /* PCI_AD17 */ - {6, 18, 3, 0, 3}, /* PCI_AD18 */ - {6, 19, 3, 0, 3}, /* PCI_AD19 */ - {6, 20, 3, 0, 3}, /* PCI_AD20 */ - {6, 21, 3, 0, 3}, /* PCI_AD21 */ - {6, 22, 3, 0, 3}, /* PCI_AD22 */ - {6, 23, 3, 0, 3}, /* PCI_AD23 */ - {6, 24, 3, 0, 3}, /* PCI_AD24 */ - {6, 25, 3, 0, 3}, /* PCI_AD25 */ - {6, 26, 3, 0, 3}, /* PCI_AD26 */ - {6, 27, 3, 0, 3}, /* PCI_AD27 */ - {6, 28, 3, 0, 3}, /* PCI_AD28 */ - {6, 29, 3, 0, 3}, /* PCI_AD29 */ - {6, 30, 3, 0, 3}, /* PCI_AD30 */ - {6, 31, 3, 0, 3}, /* PCI_AD31 */ - - /* NAND */ - {4, 18, 2, 0, 0}, /* NAND_RYnBY */ - - /* DUART - UART2 */ - {5, 0, 1, 0, 2}, /* UART2_SOUT */ - {5, 2, 1, 0, 1}, /* UART2_RTS */ - {5, 3, 2, 0, 2}, /* UART2_SIN */ - {5, 1, 2, 0, 3}, /* UART2_CTS */ - - /* UCC5 - UART3 */ - {3, 0, 1, 0, 1}, /* UART3_TX */ - {3, 4, 1, 0, 1}, /* UART3_RTS */ - {3, 6, 2, 0, 1}, /* UART3_RX */ - {3, 12, 2, 0, 0}, /* UART3_CTS */ - {3, 13, 2, 0, 0}, /* UCC5_CD */ - - /* UCC6 - UART4 */ - {3, 14, 1, 0, 1}, /* UART4_TX */ - {3, 18, 1, 0, 1}, /* UART4_RTS */ - {3, 20, 2, 0, 1}, /* UART4_RX */ - {3, 26, 2, 0, 0}, /* UART4_CTS */ - {3, 27, 2, 0, 0}, /* UCC6_CD */ - - /* Fujitsu MB86277 (MINT) graphics controller */ - {0, 30, 1, 0, 0}, /* nSRESET_GRAPHICS */ - {1, 5, 1, 0, 0}, /* nXRST_GRAPHICS */ - {1, 7, 1, 0, 0}, /* LVDS_BKLT_CTR */ - {2, 16, 1, 0, 0}, /* LVDS_BKLT_EN */ - - /* AD7843 ADC/Touchscreen controller */ - {4, 14, 1, 0, 0}, /* SPI_nCS0 */ - {4, 28, 3, 0, 3}, /* SPI_MOSI */ - {4, 29, 3, 0, 3}, /* SPI_MISO */ - {4, 30, 3, 0, 3}, /* SPI_CLK */ - - /* Freescale QUICC Engine USB Host Controller (FHCI) */ - {1, 2, 1, 0, 3}, /* USBOE */ - {1, 3, 1, 0, 3}, /* USBTP */ - {1, 8, 1, 0, 1}, /* USBTN */ - {1, 9, 2, 1, 3}, /* USBRP */ - {1, 10, 2, 0, 3}, /* USBRXD */ - {1, 11, 2, 1, 3}, /* USBRN */ - {2, 20, 2, 0, 1}, /* CLK21 */ - {4, 20, 1, 0, 0}, /* SPEED */ - {4, 21, 1, 0, 0}, /* SUSPND */ - - /* END of table */ - {0, 0, 0, 0, QE_IOP_TAB_END}, -}; - -int board_early_init_r(void) -{ - void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8); - u32 val; - - /* - * Because of errata in the UCCs, we have to write to the reserved - * registers to slow the clocks down. - */ - val = in_be32(reg); - /* UCC1 */ - val |= 0x00003000; - /* UCC2 */ - val |= 0x0c000000; - out_be32(reg, val); - - return 0; -} - -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - - msize = CONFIG_SYS_DDR_SIZE; - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { - if (ddr_size & 1) - return -1; - } - - im->sysconf.ddrlaw[0].ar = - LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); - - im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; - udelay(200); - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - - return msize; -} - -phys_size_t initdram(int board_type) -{ -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - extern void ddr_enable_ecc(unsigned int dram_size); -#endif - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = 0; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) - return -1; - - /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; - msize = fixed_sdram(); - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize DDR ECC byte - */ - ddr_enable_ecc(msize * 1024 * 1024); -#endif - - /* return total bus SDRAM size(bytes) -- DDR */ - return (msize * 1024 * 1024); -} - -int checkboard(void) -{ - puts("Board: Freescale/Logic MPC8360ERDK\n"); - return 0; -} - -static struct pci_region pci_regions[] = { - { - .bus_start = CONFIG_SYS_PCI1_MEM_BASE, - .phys_start = CONFIG_SYS_PCI1_MEM_PHYS, - .size = CONFIG_SYS_PCI1_MEM_SIZE, - .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH, - }, - { - .bus_start = CONFIG_SYS_PCI1_MMIO_BASE, - .phys_start = CONFIG_SYS_PCI1_MMIO_PHYS, - .size = CONFIG_SYS_PCI1_MMIO_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCI1_IO_BASE, - .phys_start = CONFIG_SYS_PCI1_IO_PHYS, - .size = CONFIG_SYS_PCI1_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -void pci_init_board(void) -{ - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; - struct pci_region *reg[] = { pci_regions, }; - -#if defined(CONFIG_PCI_33M) - clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 | - OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR; - printf("PCI clock is 33MHz\n"); -#else - clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; - printf("PCI clock is 66MHz\n"); -#endif - - udelay(2000); - - /* Configure PCI Local Access Windows */ - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - - mpc83xx_pci_init(1, reg); -} - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - ft_pci_setup(blob, bd); - - return 0; -} -#endif diff --git a/board/freescale/mpc8360erdk/nand.c b/board/freescale/mpc8360erdk/nand.c deleted file mode 100644 index 237c0c42e0..0000000000 --- a/board/freescale/mpc8360erdk/nand.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * MPC8360E-RDK support for the NAND on FSL UPM - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -static struct immap *im = (struct immap *)CONFIG_SYS_IMMR; - -static const u32 upm_array[] = { - 0x0ff03c30, 0x0ff03c30, 0x0ff03c34, 0x0ff33c30, /* Words 0 to 3 */ - 0xfff33c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 4 to 7 */ - 0x0faf3c30, 0x0faf3c30, 0x0faf3c30, 0x0fff3c34, /* Words 8 to 11 */ - 0xffff3c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 12 to 15 */ - 0x0fa3fc30, 0x0fa3fc30, 0x0fa3fc30, 0x0ff3fc34, /* Words 16 to 19 */ - 0xfff3fc31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 20 to 23 */ - 0x0ff33c30, 0x0fa33c30, 0x0fa33c34, 0x0ff33c30, /* Words 24 to 27 */ - 0xfff33c31, 0xfff0fc30, 0xfff0fc30, 0xfff0fc30, /* Words 28 to 31 */ - 0xfff3fc30, 0xfff3fc30, 0xfff6fc30, 0xfffcfc30, /* Words 32 to 35 */ - 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 36 to 39 */ - 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 40 to 43 */ - 0xfffdfc30, 0xfffffc30, 0xfffffc30, 0xfffffc31, /* Words 44 to 47 */ - 0xfffffc30, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 60 to 63 */ -}; - -static void upm_setup(struct fsl_upm *upm) -{ - int i; - - /* write upm array */ - out_be32(upm->mxmr, MxMR_OP_WARR); - - for (i = 0; i < 64; i++) { - out_be32(upm->mdr, upm_array[i]); - out_8(upm->io_addr, 0x0); - } - - /* normal operation */ - out_be32(upm->mxmr, MxMR_OP_NORM); - while (in_be32(upm->mxmr) != MxMR_OP_NORM) - eieio(); -} - -static int dev_ready(int chip_nr) -{ - if (in_be32(&im->qepio.ioport[4].pdat) & 0x00002000) { - debug("nand ready\n"); - return 1; - } - - debug("nand busy\n"); - return 0; -} - -static struct fsl_upm_nand fun = { - .upm = { - .io_addr = (void *)CONFIG_SYS_NAND_BASE, - }, - .width = 8, - .upm_cmd_offset = 8, - .upm_addr_offset = 16, - .dev_ready = dev_ready, - .wait_flags = FSL_UPM_WAIT_RUN_PATTERN, - .chip_delay = 50, -}; - -int board_nand_init(struct nand_chip *nand) -{ - fun.upm.mxmr = &im->im_lbc.mamr; - fun.upm.mdr = &im->im_lbc.mdr; - fun.upm.mar = &im->im_lbc.mar; - - upm_setup(&fun.upm); - - return fsl_upm_nand_init(nand, &fun); -} -- cgit v1.2.1