From 0911af00b09c065444e4f8842a67a11c0d9b03cd Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 13 Sep 2014 08:16:49 +0200 Subject: arm: socfpga: clock: Add missing stubs into board file Add some stub defines, which are used by the clock code, but are missing from the auto-generated header file for the SoCFPGA family. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Dinh Nguyen Acked-by: Pavel Machek --- board/altera/socfpga/pll_config.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'board') diff --git a/board/altera/socfpga/pll_config.h b/board/altera/socfpga/pll_config.h index 9bd044230b..f0f59a9519 100644 --- a/board/altera/socfpga/pll_config.h +++ b/board/altera/socfpga/pll_config.h @@ -94,6 +94,9 @@ /* Info for driver */ #define CONFIG_HPS_CLK_OSC1_HZ (25000000) +#define CONFIG_HPS_CLK_OSC2_HZ 0 +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 #define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000) #define CONFIG_HPS_CLK_PERVCO_HZ (1000000000) #ifdef CONFIG_SOCFPGA_ARRIA5 -- cgit v1.2.1 From 868749a61dcc29456c8b06748b6130de4940369b Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: board: Correctly set ATAG position The bi_boot_params must point to offset 0x100 in DRAM. Make it so. Signed-off-by: Pavel Machek Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek --- board/altera/socfpga/socfpga_cyclone5.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'board') diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c index fb92852d5f..bc8a87c648 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c +++ b/board/altera/socfpga/socfpga_cyclone5.c @@ -35,5 +35,9 @@ int board_early_init_f(void) int board_init(void) { icache_enable(); + + /* Address of boot parameters for ATAG (if ATAG is used) */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + return 0; } -- cgit v1.2.1 From 604364e42cf7dd3c4980901b47ee47eb4b490e4b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: board: Align checkboard() output Cosmetic change to the checkboard() function output. Align the output with the rest of initial output produced by U-Boot. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek --- board/altera/socfpga/socfpga_cyclone5.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c index bc8a87c648..41498421c1 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c +++ b/board/altera/socfpga/socfpga_cyclone5.c @@ -17,7 +17,7 @@ DECLARE_GLOBAL_DATA_PTR; */ int checkboard(void) { - puts("BOARD : Altera SOCFPGA Cyclone5 Board\n"); + puts("BOARD: Altera SoCFPGA Cyclone5 Board\n"); return 0; } -- cgit v1.2.1 From 40e7bcdee72830fa51d9e98428f1a61f9126527e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 Sep 2014 01:29:08 +0200 Subject: arm: socfpga: cache: Enable D-Cache The code is now fixed to the point where we can safely enable the L1 data cache. Enable the D-Cache and set it as write-alloc. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek --- board/altera/socfpga/socfpga_cyclone5.c | 1 + 1 file changed, 1 insertion(+) (limited to 'board') diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c index 41498421c1..6b982778be 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c +++ b/board/altera/socfpga/socfpga_cyclone5.c @@ -35,6 +35,7 @@ int board_early_init_f(void) int board_init(void) { icache_enable(); + dcache_enable(); /* Address of boot parameters for ATAG (if ATAG is used) */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; -- cgit v1.2.1 From 4ab333b765db5cd00b297b4c0e3cd3af5fe320fc Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 21 Sep 2014 13:57:40 +0200 Subject: arm: socfpga: Move cache_enable to CPU code Move icache_enable() and dcache_enable() function calls from board code into the CPU code and into the enable_caches() function. This is how the cache enabling code was designed to work. Signed-off-by: Marek Vasut Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Tom Rini Cc: Albert Aribaud Cc: Wolfgang Denk Acked-by: Pavel Machek --- board/altera/socfpga/socfpga_cyclone5.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'board') diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c index 6b982778be..0f81d899a6 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c +++ b/board/altera/socfpga/socfpga_cyclone5.c @@ -34,9 +34,6 @@ int board_early_init_f(void) */ int board_init(void) { - icache_enable(); - dcache_enable(); - /* Address of boot parameters for ATAG (if ATAG is used) */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; -- cgit v1.2.1 From f885b849681ce0f15c2df313f38ae06a601be506 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Tue, 30 Sep 2014 18:45:32 +0200 Subject: sunxi: Fix gmac not working reliable on the Bananapi In order for the gmac nic to work reliable on the Bananapi, we need to set bits 10-12 GTXDC "GMAC Transmit Clock Delay Chain" of the GMAC clk register (0x01c20164) to 3. Without this about 9 out of 10 ethernet packets get lost, with this setting there is no packet loss. So far setting these bits is only necessary on the Bananapi, so this commit solves this with a bit of #ifdef CONFIG_BANANAPI code. If in the future we need to do something similar for other boards, we can create a specific CONFIG_FOO option for this then. Reported-by: Karsten Merker Signed-off-by: Hans de Goede Tested-by: Karsten Merker Tested-by: Zoltan HERPAI Tested-by: Tony Zhang Acked-by: Ian Campbell --- board/sunxi/gmac.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'board') diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c index e7ff95285c..6348d27282 100644 --- a/board/sunxi/gmac.c +++ b/board/sunxi/gmac.c @@ -24,6 +24,15 @@ int sunxi_gmac_initialize(bd_t *bis) CCM_GMAC_CTRL_GPIT_MII); #endif + /* + * In order for the gmac nic to work reliable on the Bananapi, we + * need to set bits 10-12 GTXDC "GMAC Transmit Clock Delay Chain" + * of the GMAC clk register to 3. + */ +#ifdef CONFIG_BANANAPI + setbits_le32(&ccm->gmac_clk_cfg, 0x3 << 10); +#endif + /* Configure pin mux settings for GMAC */ for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) { #ifdef CONFIG_RGMII -- cgit v1.2.1 From 3160b1b98603cba3c480f70e153b259171d3e4a6 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 23 Sep 2014 18:07:02 +0300 Subject: OMAP5+: sata/scsi: Implement scsi_init() On OMAP platforms, SATA controller provides the SCSI subsystem so implement scsi_init(). Get rid of the unnecessary sata_init() call from dra7xx-evm and omap5-uevm board files. Signed-off-by: Roger Quadros --- board/ti/dra7xx/evm.c | 1 - board/ti/omap5_uevm/evm.c | 6 ------ 2 files changed, 7 deletions(-) (limited to 'board') diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 5592fc5def..37df7b2cad 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -93,7 +93,6 @@ int board_late_init(void) else setenv("board_name", "dra7xx"); #endif - init_sata(0); return 0; } diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c index 4666b38a71..833ffe9943 100644 --- a/board/ti/omap5_uevm/evm.c +++ b/board/ti/omap5_uevm/evm.c @@ -69,12 +69,6 @@ int board_init(void) return 0; } -int board_late_init(void) -{ - init_sata(0); - return 0; -} - int board_eth_init(bd_t *bis) { return 0; -- cgit v1.2.1 From dc9617e0cee28808863cbb21f4528f89bc383923 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 29 Sep 2014 01:37:57 +0900 Subject: powerpc: ppc4xx: remove board support for KAREF and METROBOX These boards have been orphaned for more than 6 months. Signed-off-by: Masahiro Yamada --- board/sandburst/common/flash.c | 493 ---------------- board/sandburst/common/sb_common.c | 349 ------------ board/sandburst/common/sb_common.h | 60 -- board/sandburst/karef/Kconfig | 12 - board/sandburst/karef/MAINTAINERS | 6 - board/sandburst/karef/Makefile | 16 - board/sandburst/karef/config.mk | 21 - board/sandburst/karef/hal_ka_of_auto.h | 324 ----------- board/sandburst/karef/hal_ka_sc_auto.h | 836 ---------------------------- board/sandburst/karef/init.S | 39 -- board/sandburst/karef/karef.c | 595 -------------------- board/sandburst/karef/karef.h | 60 -- board/sandburst/karef/karef_version.h | 10 - board/sandburst/karef/u-boot.lds.debug | 130 ----- board/sandburst/metrobox/Kconfig | 12 - board/sandburst/metrobox/MAINTAINERS | 6 - board/sandburst/metrobox/Makefile | 15 - board/sandburst/metrobox/config.mk | 16 - board/sandburst/metrobox/hal_xc_auto.h | 553 ------------------ board/sandburst/metrobox/init.S | 37 -- board/sandburst/metrobox/metrobox.c | 561 ------------------- board/sandburst/metrobox/metrobox.h | 29 - board/sandburst/metrobox/metrobox_version.h | 11 - board/sandburst/metrobox/u-boot.lds.debug | 130 ----- 24 files changed, 4321 deletions(-) delete mode 100644 board/sandburst/common/flash.c delete mode 100644 board/sandburst/common/sb_common.c delete mode 100644 board/sandburst/common/sb_common.h delete mode 100644 board/sandburst/karef/Kconfig delete mode 100644 board/sandburst/karef/MAINTAINERS delete mode 100644 board/sandburst/karef/Makefile delete mode 100644 board/sandburst/karef/config.mk delete mode 100644 board/sandburst/karef/hal_ka_of_auto.h delete mode 100644 board/sandburst/karef/hal_ka_sc_auto.h delete mode 100644 board/sandburst/karef/init.S delete mode 100644 board/sandburst/karef/karef.c delete mode 100644 board/sandburst/karef/karef.h delete mode 100644 board/sandburst/karef/karef_version.h delete mode 100644 board/sandburst/karef/u-boot.lds.debug delete mode 100644 board/sandburst/metrobox/Kconfig delete mode 100644 board/sandburst/metrobox/MAINTAINERS delete mode 100644 board/sandburst/metrobox/Makefile delete mode 100644 board/sandburst/metrobox/config.mk delete mode 100644 board/sandburst/metrobox/hal_xc_auto.h delete mode 100644 board/sandburst/metrobox/init.S delete mode 100644 board/sandburst/metrobox/metrobox.c delete mode 100644 board/sandburst/metrobox/metrobox.h delete mode 100644 board/sandburst/metrobox/metrobox_version.h delete mode 100644 board/sandburst/metrobox/u-boot.lds.debug (limited to 'board') diff --git a/board/sandburst/common/flash.c b/board/sandburst/common/flash.c deleted file mode 100644 index ad046bed69..0000000000 --- a/board/sandburst/common/flash.c +++ /dev/null @@ -1,493 +0,0 @@ -/* - * (C) Copyright 2002-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 Jun Gu - * Add support for Am29F016D and dynamic switch setting. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* - * Ported from Ebony flash support - * Travis B. Sawyer - * Sandburst Corporation - */ -#include -#include -#include - - -#undef DEBUG -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = { - {0xfff80000} /* Boot Flash */ -}; - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - - -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned char - - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long total_b = 0; - unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; - unsigned short index = 0; - int i; - - - DEBUGF("\n"); - DEBUGF("FLASH: Index: %d\n", index); - - /* Init: no FLASHes known */ - for (i=0; iflash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; kstart[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " " - ); - } - printf ("\n"); - return; - } - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong)addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; - - DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr ); - - /* Write auto select command: read Manufacturer ID */ - udelay(10000); - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - udelay(1000); - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - udelay(1000); - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; - udelay(1000); - - value = addr2[0]; - - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - case (FLASH_WORD_SIZE)AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; /* => 512 kb */ - break; - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (info->flash_id == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* reset to return to reading data */ - addr2[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - } - - return (info->size); -} - -int wait_for_DQ7(flash_info_t *info, int sect) -{ - ulong start, now, last; - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); - - start = get_timer (0); - last = start; - while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - return 0; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); - DEBUGF("Erasing sector %p\n", addr2); - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ - for (i=0; i<50; i++) - udelay(1000); /* wait 1 ms */ - } else { - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - } - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile FLASH_WORD_SIZE *) dest) & - (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { - return (2); - } - - for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c deleted file mode 100644 index c23ef50547..0000000000 --- a/board/sandburst/common/sb_common.c +++ /dev/null @@ -1,349 +0,0 @@ -/* - * Copyright (C) 2005 Sandburst Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include -#include -#include "sb_common.h" - -DECLARE_GLOBAL_DATA_PTR; - -long int fixed_sdram (void); - -/************************************************************************* - * metrobox_get_master - * - * PRI_N - active low signal. If the GPIO pin is low we are the master - * - ************************************************************************/ -int sbcommon_get_master(void) -{ - ppc440_gpio_regs_t *gpio_regs; - - gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; - - if (gpio_regs->in & SBCOMMON_GPIO_PRI_N) { - return 0; - } - else { - return 1; - } -} - -/************************************************************************* - * metrobox_secondary_present - * - * Figure out if secondary/slave board is present - * - ************************************************************************/ -int sbcommon_secondary_present(void) -{ - ppc440_gpio_regs_t *gpio_regs; - - gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; - - if (gpio_regs->in & SBCOMMON_GPIO_SEC_PRES) - return 0; - else - return 1; -} - -/************************************************************************* - * sbcommon_get_serial_number - * - * Retrieve the board serial number via the mac address in eeprom - * - ************************************************************************/ -unsigned short sbcommon_get_serial_number(void) -{ - unsigned char buff[0x100]; - unsigned short sernum; - - /* Get the board serial number from eeprom */ - /* Initialize I2C */ - i2c_set_bus_num(0); - - /* Read 256 bytes in EEPROM */ - i2c_read (0x50, 0, 1, buff, 0x100); - - memcpy(&sernum, &buff[0xF4], 2); - sernum /= 32; - - return (sernum); -} - -/************************************************************************* - * sbcommon_fans - * - * Spin up fans 2 & 3 to get some air moving. OS will take care - * of the rest. This is mostly a precaution... - * - * Assumes i2c bus 1 is ready. - * - ************************************************************************/ -void sbcommon_fans(void) -{ - /* - * Attempt to turn on 2 of the fans... - * Need to go through the bridge - */ - i2c_set_bus_num(1); - puts ("FANS: "); - - /* select fan4 through the bridge */ - i2c_reg_write(0x73, /* addr */ - 0x00, /* reg */ - 0x08); /* val = bus 4 */ - - /* Turn on FAN 4 */ - i2c_reg_write(0x2e, - 1, - 0x80); - - i2c_reg_write(0x2e, - 0, - 0x19); - - /* Deselect bus 4 on the bridge */ - i2c_reg_write(0x73, - 0x00, - 0x00); - - /* select fan3 through the bridge */ - i2c_reg_write(0x73, /* addr */ - 0x00, /* reg */ - 0x04); /* val = bus 3 */ - - /* Turn on FAN 3 */ - i2c_reg_write(0x2e, - 1, - 0x80); - - i2c_reg_write(0x2e, - 0, - 0x19); - - /* Deselect bus 3 on the bridge */ - i2c_reg_write(0x73, - 0x00, - 0x00); - - /* select fan2 through the bridge */ - i2c_reg_write(0x73, /* addr */ - 0x00, /* reg */ - 0x02); /* val = bus 4 */ - - /* Turn on FAN 2 */ - i2c_reg_write(0x2e, - 1, - 0x80); - - i2c_reg_write(0x2e, - 0, - 0x19); - - /* Deselect bus 2 on the bridge */ - i2c_reg_write(0x73, - 0x00, - 0x00); - - /* select fan1 through the bridge */ - i2c_reg_write(0x73, /* addr */ - 0x00, /* reg */ - 0x01); /* val = bus 0 */ - - /* Turn on FAN 1 */ - i2c_reg_write(0x2e, - 1, - 0x80); - - i2c_reg_write(0x2e, - 0, - 0x19); - - /* Deselect bus 1 on the bridge */ - i2c_reg_write(0x73, - 0x00, - 0x00); - - puts ("on\n"); - i2c_set_bus_num(0); - - return; - -} - -/************************************************************************* - * initdram - * - * Initialize sdram - * - ************************************************************************/ -phys_size_t initdram (int board_type) -{ - long dram_size = 0; - -#if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (); -#else - dram_size = fixed_sdram (); -#endif - return dram_size; -} - - -/************************************************************************* - * testdram - * - * - ************************************************************************/ -#if defined(CONFIG_SYS_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; - uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; - uint *p; - - printf("Testing SDRAM: "); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("OK\n"); - return 0; -} -#endif - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - * - * Assumes: 128 MB, non-ECC, non-registered - * PLB @ 133 MHz - * - ************************************************************************/ -long int fixed_sdram (void) -{ - uint reg; - - /*-------------------------------------------------------------------- - * Setup some default - *------------------------------------------------------------------*/ - mtsdram (SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ - mtsdram (SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ - mtsdram (SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram (SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */ - mtsdram (SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ - - /*-------------------------------------------------------------------- - * Setup for board-specific specific mem - *------------------------------------------------------------------*/ - /* - * Following for CAS Latency = 2.5 @ 133 MHz PLB - */ - mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ - mtsdram (SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ - /* RA=10 RD=3 */ - mtsdram (SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ - mtsdram (SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ - mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */ - udelay (400); /* Delay 200 usecs (min) */ - - /*-------------------------------------------------------------------- - * Enable the controller, then wait for DCEN to complete - *------------------------------------------------------------------*/ - mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ - for (;;) { - mfsdram (SDRAM0_MCSTS, reg); - if (reg & 0x80000000) - break; - } - - return (128 * 1024 * 1024); /* 128 MB */ -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - -/************************************************************************* - * board_get_enetaddr - * - * Get the ethernet MAC address for the management ethernet from the - * strap EEPROM. Note that is the BASE address for the range of - * external ethernet MACs on the board. The base + 31 is the actual - * mgmt mac address. - * - ************************************************************************/ - -void board_get_enetaddr(int macaddr_idx, uchar *enet) -{ - int i; - unsigned short tmp; - unsigned char buff[0x100], *cp; - - if (0 == macaddr_idx) { - - /* Initialize I2C */ - i2c_set_bus_num(0); - - /* Read 256 bytes in EEPROM */ - i2c_read (0x50, 0, 1, buff, 0x100); - - cp = &buff[0xF0]; - - for (i = 0; i < 6; i++,cp++) - enet[i] = *cp; - - memcpy(&tmp, &enet[4], 2); - tmp += 31; - memcpy(&enet[4], &tmp, 2); - - } else { - enet[0] = 0x02; - enet[1] = 0x00; - enet[2] = 0x00; - enet[3] = 0x00; - enet[4] = 0x00; - if (1 == sbcommon_get_master() ) { - /* Master/Primary card */ - enet[5] = 0x01; - } else { - /* Slave/Secondary card */ - enet [5] = 0x02; - } - } - - return; -} - -#ifdef CONFIG_POST -/* - * Returns 1 if keys pressed to start the power-on long-running tests - * Called from board_init_f(). - */ -int post_hotkeys_pressed(void) -{ - - return (ctrlc()); -} -#endif diff --git a/board/sandburst/common/sb_common.h b/board/sandburst/common/sb_common.h deleted file mode 100644 index 57406335bf..0000000000 --- a/board/sandburst/common/sb_common.h +++ /dev/null @@ -1,60 +0,0 @@ -#ifndef __SBCOMMON_H__ -#define __SBCOMMON_H__ -/* - * Copyright (C) 2005 Sandburst Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include -#include - -/* - * GPIO Settings - */ -/* Chassis settings */ -#define SBCOMMON_GPIO_PRI_N 0x00001000 /* 0 = Chassis Master, 1 = Slave */ -#define SBCOMMON_GPIO_SEC_PRES 0x00000800 /* 1 = Other board present */ - -/* Debug LEDs */ -#define SBCOMMON_GPIO_DBGLED_0 0x00000400 -#define SBCOMMON_GPIO_DBGLED_1 0x00000200 -#define SBCOMMON_GPIO_DBGLED_2 0x00100000 -#define SBCOMMON_GPIO_DBGLED_3 0x00000100 - -#define SBCOMMON_GPIO_DBGLEDS (SBCOMMON_GPIO_DBGLED_0 | \ - SBCOMMON_GPIO_DBGLED_1 | \ - SBCOMMON_GPIO_DBGLED_2 | \ - SBCOMMON_GPIO_DBGLED_3) - -#define SBCOMMON_GPIO_SYS_FAULT 0x00000080 -#define SBCOMMON_GPIO_SYS_OTEMP 0x00000040 -#define SBCOMMON_GPIO_SYS_STATUS 0x00000020 - -#define SBCOMMON_GPIO_SYS_LEDS (SBCOMMON_GPIO_SYS_STATUS) - -#define SBCOMMON_GPIO_LEDS (SBCOMMON_GPIO_DBGLED_0 | \ - SBCOMMON_GPIO_DBGLED_1 | \ - SBCOMMON_GPIO_DBGLED_2 | \ - SBCOMMON_GPIO_DBGLED_3 | \ - SBCOMMON_GPIO_SYS_STATUS) - -typedef struct ppc440_gpio_regs { - volatile unsigned long out; - volatile unsigned long tri_state; - volatile unsigned long dummy[4]; - volatile unsigned long open_drain; - volatile unsigned long in; -} __attribute__((packed)) ppc440_gpio_regs_t; - -int sbcommon_get_master(void); -int sbcommon_secondary_present(void); -unsigned short sbcommon_get_serial_number(void); -void sbcommon_fans(void); -void board_get_enetaddr(int macaddr_idx, uchar *enet); - -#endif /* __SBCOMMON_H__ */ diff --git a/board/sandburst/karef/Kconfig b/board/sandburst/karef/Kconfig deleted file mode 100644 index 1b04576b9c..0000000000 --- a/board/sandburst/karef/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_KAREF - -config SYS_BOARD - default "karef" - -config SYS_VENDOR - default "sandburst" - -config SYS_CONFIG_NAME - default "KAREF" - -endif diff --git a/board/sandburst/karef/MAINTAINERS b/board/sandburst/karef/MAINTAINERS deleted file mode 100644 index 21510e85c0..0000000000 --- a/board/sandburst/karef/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -KAREF BOARD -#M: Travis Sawyer -S: Orphan (since 2014-03) -F: board/sandburst/karef/ -F: include/configs/KAREF.h -F: configs/KAREF_defconfig diff --git a/board/sandburst/karef/Makefile b/board/sandburst/karef/Makefile deleted file mode 100644 index ce29b4100e..0000000000 --- a/board/sandburst/karef/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2005 -# Sandburst Corporation -# Travis B. Sawyer -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# TBS: add for debugging purposes -ccflags-y += -DBUILDUSER='"$(shell whoami)"' - -obj-y = karef.o ../common/flash.o ../common/sb_common.o -extra-y += init.o diff --git a/board/sandburst/karef/config.mk b/board/sandburst/karef/config.mk deleted file mode 100644 index b73986d3f2..0000000000 --- a/board/sandburst/karef/config.mk +++ /dev/null @@ -1,21 +0,0 @@ -# -# (C) Copyright 2005 -# Sandburst Corporation -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# Sandburst Corporation Metrobox Reference Design -# Travis B. Sawyer -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/sandburst/karef/hal_ka_of_auto.h b/board/sandburst/karef/hal_ka_of_auto.h deleted file mode 100644 index cc501c99d9..0000000000 --- a/board/sandburst/karef/hal_ka_of_auto.h +++ /dev/null @@ -1,324 +0,0 @@ -/* **************************************************************** - * Common defs for reg spec for chip ka_of - * Auto-generated by trex2: DO NOT HAND-EDIT!! - * **************************************************************** - */ - -#ifndef HAL_KA_OF_AUTO_H -#define HAL_KA_OF_AUTO_H - - -/* ---------------------------------------------------------------- - * For block: 'ofem' - */ - -/* ---- Block instance addressing (for block-select) */ -#define OFEM_BLOCK_ADDR_BIT_L 6 -#define OFEM_BLOCK_ADDR_BIT_H 9 -#define OFEM_BLOCK_ADDR_WIDTH 4 - -#define OFEM_ADDR 0x0 - -/* ---- Reg addressing (within block) */ -#define OFEM_REG_ADDR_BIT_L 2 -#define OFEM_REG_ADDR_BIT_H 5 -#define OFEM_REG_ADDR_WIDTH 4 - - -/* ================================================================ - * ---- Register KA_OF_OFEM_REVISION */ -#define SAND_HAL_KA_OF_OFEM_REVISION_OFFSET 0x000 -#ifndef SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_REVISION_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_REVISION_MSB 31 -#define SAND_HAL_KA_OF_OFEM_REVISION_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_RESET */ -#define SAND_HAL_KA_OF_OFEM_RESET_OFFSET 0x004 -#ifndef SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_RESET_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_RESET_MSB 31 -#define SAND_HAL_KA_OF_OFEM_RESET_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_CNTL */ -#define SAND_HAL_KA_OF_OFEM_CNTL_OFFSET 0x018 -#ifndef SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_CNTL_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_CNTL_MSB 31 -#define SAND_HAL_KA_OF_OFEM_CNTL_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_MAC_FLOW_CTL */ -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_OFFSET 0x01c -#ifndef SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MSB 31 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_INTERRUPT */ -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_OFFSET 0x008 -#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MSB 31 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_INTERRUPT_MASK */ -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_OFFSET 0x00c -#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MSB 31 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_SCRATCH */ -#define SAND_HAL_KA_OF_OFEM_SCRATCH_OFFSET 0x010 -#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MSB 31 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_SCRATCH_MASK */ -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_OFFSET 0x014 -#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MSB 31 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_LSB 0 - -/* ================================================================ - * Field info for register KA_OF_OFEM_REVISION */ -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK 0x0000ff00 -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT 8 -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MSB 15 -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_LSB 8 -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_DEFAULT 0x00000024 -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK 0x000000ff -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MSB 7 -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_LSB 0 -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_RESET */ -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK 0x00000004 -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_SHIFT 2 -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MSB 2 -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_LSB 2 -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK 0x00000002 -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_SHIFT 1 -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MSB 1 -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_LSB 1 -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK 0x00000001 -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MSB 0 -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_LSB 0 -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_CNTL */ -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MASK 0x000000c0 -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_SHIFT 6 -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MSB 7 -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_LSB 6 -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK 0x00000030 -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT 4 -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MSB 5 -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_LSB 4 -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MASK 0x0000000c -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_SHIFT 2 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MSB 3 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_LSB 2 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MASK 0x00000003 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MSB 1 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_LSB 0 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_MAC_FLOW_CTL */ -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MASK 0x00000100 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_SHIFT 8 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MSB 8 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_LSB 8 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK 0x00000010 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT 4 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB 4 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB 4 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK 0x0000000f -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB 3 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB 0 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_INTERRUPT */ -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MASK 0x00000100 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_SHIFT 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MSB 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_LSB 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MASK 0x00000080 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_SHIFT 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MSB 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_LSB 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MASK 0x00000040 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_SHIFT 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MSB 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_LSB 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MASK 0x00000020 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_SHIFT 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MSB 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_LSB 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MASK 0x00000010 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_SHIFT 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MSB 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_LSB 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MASK 0x00000008 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_SHIFT 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MSB 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_LSB 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MASK 0x00000004 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_SHIFT 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MSB 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_LSB 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MASK 0x00000002 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_SHIFT 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MSB 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_LSB 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MASK 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MSB 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_LSB 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_INTERRUPT_MASK */ -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK 0x00000100 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK 0x00000080 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK 0x00000040 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK 0x00000020 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK 0x00000010 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK 0x00000008 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK 0x00000004 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK 0x00000002 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT 0x00000001 - -/* ================================================================ - * Field info for register KA_OF_OFEM_SCRATCH */ -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MSB 31 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_LSB 0 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_SCRATCH_MASK */ -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff - -#endif /* matches #ifndef HAL_KA_OF_AUTO_H */ diff --git a/board/sandburst/karef/hal_ka_sc_auto.h b/board/sandburst/karef/hal_ka_sc_auto.h deleted file mode 100644 index db1cec246a..0000000000 --- a/board/sandburst/karef/hal_ka_sc_auto.h +++ /dev/null @@ -1,836 +0,0 @@ -/* **************************************************************** - * Common defs for reg spec for chip ka_sc - * Auto-generated by trex2: DO NOT HAND-EDIT!! - * **************************************************************** - */ - -#ifndef HAL_KA_SC_AUTO_H -#define HAL_KA_SC_AUTO_H - - -/* ---------------------------------------------------------------- - * For block: 'scan' - */ - -/* ---- Block instance addressing (for block-select) */ -#define SCAN_BLOCK_ADDR_BIT_L 7 -#define SCAN_BLOCK_ADDR_BIT_H 9 -#define SCAN_BLOCK_ADDR_WIDTH 3 - -#define SCAN_ADDR 0x0 - -/* ---- Reg addressing (within block) */ -#define SCAN_REG_ADDR_BIT_L 2 -#define SCAN_REG_ADDR_BIT_H 6 -#define SCAN_REG_ADDR_WIDTH 5 - - -/* ================================================================ - * ---- Register KA_SC_SCAN_REVISION */ -#define SAND_HAL_KA_SC_SCAN_REVISION_OFFSET 0x000 -#ifndef SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_REVISION_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_REVISION_MSB 31 -#define SAND_HAL_KA_SC_SCAN_REVISION_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_RESET */ -#define SAND_HAL_KA_SC_SCAN_RESET_OFFSET 0x004 -#ifndef SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_RESET_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_RESET_MSB 31 -#define SAND_HAL_KA_SC_SCAN_RESET_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_STATUS */ -#define SAND_HAL_KA_SC_SCAN_STATUS_OFFSET 0x008 -#ifndef SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_STATUS_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_STATUS_MSB 31 -#define SAND_HAL_KA_SC_SCAN_STATUS_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_CNTL */ -#define SAND_HAL_KA_SC_SCAN_CNTL_OFFSET 0x01c -#ifndef SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_CNTL_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_CNTL_MSB 31 -#define SAND_HAL_KA_SC_SCAN_CNTL_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_BRD_INFO */ -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_OFFSET 0x020 -#ifndef SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MSB 31 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCAN_FROM_0 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_OFFSET 0x024 -#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCAN_FROM_1 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_OFFSET 0x028 -#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCAN_TO_0 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_OFFSET 0x02c -#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCAN_TO_1 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_OFFSET 0x030 -#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCAN_CTRL */ -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_OFFSET 0x034 -#ifndef SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_PLL_CTRL */ -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_OFFSET 0x038 -#ifndef SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MSB 31 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_CORE_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_OFFSET 0x03c -#ifndef SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_DR_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_OFFSET 0x040 -#ifndef SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SPI_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_OFFSET 0x044 -#ifndef SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_BRD_BRD_OUT_DATA */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_OFFSET 0x048 -#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MSB 31 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_OFFSET 0x04c -#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MSB 31 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_BRD_BRD_IN */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_OFFSET 0x050 -#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MSB 31 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_MISC */ -#define SAND_HAL_KA_SC_SCAN_MISC_OFFSET 0x054 -#ifndef SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_MISC_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_MISC_MSB 31 -#define SAND_HAL_KA_SC_SCAN_MISC_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_INTERRUPT */ -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OFFSET 0x00c -#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_INTERRUPT_MASK */ -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OFFSET 0x010 -#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MSB 31 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCRATCH */ -#define SAND_HAL_KA_SC_SCAN_SCRATCH_OFFSET 0x014 -#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCRATCH_MASK */ -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_OFFSET 0x018 -#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_LSB 0 - -/* ================================================================ - * Field info for register KA_SC_SCAN_REVISION */ -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK 0x0000ff00 -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MSB 15 -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_LSB 8 -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_DEFAULT 0x00000023 -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK 0x000000ff -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MSB 7 -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_LSB 0 -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_RESET */ -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK 0x00000200 -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_SHIFT 9 -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MSB 9 -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_LSB 9 -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK 0x00000100 -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MSB 8 -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_LSB 8 -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK 0x00000080 -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_SHIFT 7 -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MSB 7 -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_LSB 7 -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK 0x00000040 -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_SHIFT 6 -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MSB 6 -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_LSB 6 -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK 0x00000020 -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_SHIFT 5 -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MSB 5 -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_LSB 5 -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK 0x00000010 -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MSB 4 -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_LSB 4 -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK 0x00000008 -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MSB 3 -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_LSB 3 -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MSB 1 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_LSB 1 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MSB 0 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_LSB 0 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_STATUS */ -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MASK 0x00000040 -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_SHIFT 6 -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MSB 6 -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_LSB 6 -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MASK 0x00000020 -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_SHIFT 5 -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MSB 5 -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_LSB 5 -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MASK 0x00000010 -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MSB 4 -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_LSB 4 -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MASK 0x00000008 -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MSB 3 -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_LSB 3 -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MASK 0x00000004 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_SHIFT 2 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MSB 2 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_LSB 2 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MSB 1 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_LSB 1 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MSB 0 -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_LSB 0 -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_CNTL */ -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MASK 0x00000400 -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_SHIFT 10 -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MSB 10 -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_LSB 10 -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MASK 0x00000200 -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_SHIFT 9 -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MSB 9 -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_LSB 9 -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MASK 0x00000100 -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MSB 8 -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_LSB 8 -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MASK 0x000000c0 -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_SHIFT 6 -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MSB 7 -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_LSB 6 -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK 0x00000030 -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MSB 5 -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_LSB 4 -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MASK 0x0000000c -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_SHIFT 2 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MSB 3 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_LSB 2 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MASK 0x00000003 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MSB 1 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_LSB 0 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_BRD_INFO */ -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK 0x0000f000 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT 12 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MSB 15 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_LSB 12 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK 0x00000300 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MSB 9 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_LSB 8 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK 0x000000f0 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MSB 7 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_LSB 4 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK 0x00000003 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MSB 1 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_LSB 0 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCAN_FROM_0 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCAN_FROM_1 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCAN_TO_0 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCAN_TO_1 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCAN_CTRL */ -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MASK 0x04000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_SHIFT 26 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MSB 26 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_LSB 26 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MASK 0x03000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_SHIFT 24 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MSB 25 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_LSB 24 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MASK 0x00100000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_SHIFT 20 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MSB 20 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_LSB 20 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MASK 0x00080000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_SHIFT 19 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MSB 19 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_LSB 19 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MASK 0x00040000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_SHIFT 18 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MSB 18 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_LSB 18 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MASK 0x00020000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_SHIFT 17 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MSB 17 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_LSB 17 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MASK 0x00010000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_SHIFT 16 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MSB 16 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_LSB 16 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MASK 0x00001000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_SHIFT 12 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MSB 12 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_LSB 12 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MASK 0x00000800 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SHIFT 11 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MSB 11 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_LSB 11 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MASK 0x00000400 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SHIFT 10 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MSB 10 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_LSB 10 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MASK 0x00000200 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SHIFT 9 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MSB 9 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_LSB 9 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MASK 0x00000100 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MSB 8 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_LSB 8 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MASK 0x00000018 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MSB 4 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_LSB 3 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MASK 0x00000004 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_SHIFT 2 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MSB 2 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_LSB 2 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MSB 1 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_LSB 1 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_PLL_CTRL */ -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MASK 0x00002000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_SHIFT 13 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MSB 13 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_LSB 13 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MASK 0x00001000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_SHIFT 12 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MSB 12 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_LSB 12 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MASK 0x00000800 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_SHIFT 11 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MSB 11 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_LSB 11 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MASK 0x00000400 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_SHIFT 10 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MSB 10 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_LSB 10 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MASK 0x00000200 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_SHIFT 9 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MSB 9 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_LSB 9 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MASK 0x00000100 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MSB 8 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_LSB 8 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MASK 0x00000080 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_SHIFT 7 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MSB 7 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_LSB 7 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MASK 0x00000040 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_SHIFT 6 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MSB 6 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_LSB 6 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MASK 0x00000020 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_SHIFT 5 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MSB 5 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_LSB 5 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MASK 0x00000010 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MSB 4 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_LSB 4 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MASK 0x00000008 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MSB 3 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_LSB 3 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MASK 0x00000007 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MSB 2 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_LSB 0 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_CORE_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MSB 23 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_DR_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MSB 23 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SPI_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MSB 23 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_BRD_BRD_OUT_DATA */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MASK 0x001fffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MSB 20 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MASK 0x001fffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MSB 20 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_LSB 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_BRD_BRD_IN */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MASK 0x001fffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MSB 20 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_LSB 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_MISC */ -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MSB 1 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_LSB 1 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MSB 0 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_LSB 0 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_INTERRUPT */ -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MASK 0x00000010 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MSB 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_LSB 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MASK 0x00000008 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MSB 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_LSB 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MASK 0x00000004 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_SHIFT 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MSB 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_LSB 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MSB 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_LSB 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MSB 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_LSB 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_INTERRUPT_MASK */ -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK 0x00000010 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK 0x00000008 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK 0x00000004 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT 0x00000001 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCRATCH */ -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCRATCH_MASK */ -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff - -#endif /* matches #ifndef HAL_KA_SC_AUTO_H */ diff --git a/board/sandburst/karef/init.S b/board/sandburst/karef/init.S deleted file mode 100644 index 61c5d07964..0000000000 --- a/board/sandburst/karef/init.S +++ /dev/null @@ -1,39 +0,0 @@ -/* -* Copyright (C) 2005 Sandburst Corporation - * SPDX-License-Identifier: GPL-2.0+ -*/ -/* - * Ported from Ebony init.S by Travis B. Sawyer - */ - -#include -#include -#include -#include - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) - tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) - tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG) - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG ) - tlbtab_end diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c deleted file mode 100644 index 96d7dcd8fd..0000000000 --- a/board/sandburst/karef/karef.c +++ /dev/null @@ -1,595 +0,0 @@ -/* - * Copyright (C) 2005 Sandburst Corporation - * Travis B. Sawyer - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "karef.h" -#include "karef_version.h" -#include -#include -#include -#include -#include -#include "../common/sb_common.h" -#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \ - defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) -#include -#endif - -void fpga_init (void); - -KAREF_BOARD_ID_ST board_id_as[] = -{ - {"Undefined"}, /* Not specified */ - {"Kamino Reference Design"}, - {"Reserved"}, /* Reserved for future use */ - {"Reserved"}, /* Reserved for future use */ -}; - -KAREF_BOARD_ID_ST ofem_board_id_as[] = -{ - {"Undefined"}, - {"1x10 + 10x2"}, - {"Reserved"}, - {"Reserved"}, -}; - -/************************************************************************* - * board_early_init_f - * - * Setup chip selects, initialize the Opto-FPGA, initialize - * interrupt polarity and triggers. - ************************************************************************/ -int board_early_init_f (void) -{ - ppc440_gpio_regs_t *gpio_regs; - - /* Enable GPIO interrupts */ - mtsdr(SDR0_PFC0, 0x00103E00); - - /* Setup access for LEDs, and system topology info */ - gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; - gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS; - gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS; - - /* Turn on all the leds for now */ - gpio_regs->out = SBCOMMON_GPIO_LEDS; - - /*--------------------------------------------------------------------+ - | Initialize EBC CONFIG - +-------------------------------------------------------------------*/ - mtebc(EBC0_CFG, - EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | - EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | - EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | - EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | - EBC_CFG_PR_32); - - /*--------------------------------------------------------------------+ - | 1/2 MB FLASH. Initialize bank 0 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB0AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); - /*--------------------------------------------------------------------+ - | 8KB NVRAM/RTC. Initialize bank 1 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB1AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); - - /*--------------------------------------------------------------------+ - | Compact Flash, uses 2 Chip Selects (2 & 6) - +-------------------------------------------------------------------*/ - mtebc(PB2AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); - - /*--------------------------------------------------------------------+ - | KaRef Scan FPGA. Initialize bank 3 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB5AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48200000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - | MAC A & B for Kamino. OFEM FPGA decodes the addresses - | Initialize bank 4 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB4AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) | - EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - | OFEM FPGA Initialize bank 5 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB3AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - - mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48400000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - - /*--------------------------------------------------------------------+ - | Compact Flash, uses 2 Chip Selects (2 & 6) - +-------------------------------------------------------------------*/ - mtebc(PB6AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); - - /*--------------------------------------------------------------------+ - | BME-32. Initialize bank 7 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB7AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - * Setup the interrupt controller polarities, triggers, etc. - +-------------------------------------------------------------------*/ - /* - * Because of the interrupt handling rework to handle 440GX interrupts - * with the common code, we needed to change names of the UIC registers. - * Here the new relationship: - * - * U-Boot name 440GX name - * ----------------------- - * UIC0 UICB0 - * UIC1 UIC0 - * UIC2 UIC1 - * UIC3 UIC2 - */ - mtdcr (UIC1SR, 0xffffffff); /* clear all */ - mtdcr (UIC1ER, 0x00000000); /* disable all */ - mtdcr (UIC1CR, 0x00000000); /* all non- critical */ - mtdcr (UIC1PR, 0xfffffe03); /* polarity */ - mtdcr (UIC1TR, 0x01c00000); /* trigger edge vs level */ - mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC1SR, 0xffffffff); /* clear all */ - - mtdcr (UIC2SR, 0xffffffff); /* clear all */ - mtdcr (UIC2ER, 0x00000000); /* disable all */ - mtdcr (UIC2CR, 0x00000000); /* all non-critical */ - mtdcr (UIC2PR, 0xffffc8ff); /* polarity */ - mtdcr (UIC2TR, 0x00ff0000); /* trigger edge vs level */ - mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC2SR, 0xffffffff); /* clear all */ - - mtdcr (UIC3SR, 0xffffffff); /* clear all */ - mtdcr (UIC3ER, 0x00000000); /* disable all */ - mtdcr (UIC3CR, 0x00000000); /* all non-critical */ - mtdcr (UIC3PR, 0xffff83ff); /* polarity */ - mtdcr (UIC3TR, 0x00ff8c0f); /* trigger edge vs level */ - mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC3SR, 0xffffffff); /* clear all */ - - mtdcr (UIC0SR, 0xfc000000); /* clear all */ - mtdcr (UIC0ER, 0x00000000); /* disable all */ - mtdcr (UIC0CR, 0x00000000); /* all non-critical */ - mtdcr (UIC0PR, 0xfc000000); - mtdcr (UIC0TR, 0x00000000); - mtdcr (UIC0VR, 0x00000001); - - fpga_init(); - - return 0; -} - - -/************************************************************************* - * checkboard - * - * Dump pertinent info to the console - ************************************************************************/ -int checkboard (void) -{ - sys_info_t sysinfo; - unsigned char brd_rev, brd_id; - unsigned short sernum; - unsigned char scan_rev, scan_id, ofem_rev=0, ofem_id=0; - unsigned char ofem_brd_rev, ofem_brd_id; - KAREF_FPGA_REGS_ST *karef_ps; - OFEM_FPGA_REGS_ST *ofem_ps; - - karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE; - ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE; - - scan_id = (unsigned char)((karef_ps->revision_ul & - SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK) - >> SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT); - - scan_rev = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK) - >> SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT); - - brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK) - >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT); - - brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK) - >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT); - - ofem_brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK) - >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT); - - ofem_brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK) - >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT); - - if (0xF != ofem_brd_id) { - ofem_id = (unsigned char)((ofem_ps->revision_ul & - SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK) - >> SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT); - - ofem_rev = (unsigned char)((ofem_ps->revision_ul & - SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK) - >> SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT); - } - - get_sys_info (&sysinfo); - - sernum = sbcommon_get_serial_number(); - - printf ("Board: Sandburst Corporation Kamino Reference Design " - "Serial Number: %d\n", sernum); - printf ("%s\n", KAREF_U_BOOT_REL_STR); - - printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER); - if (sbcommon_get_master()) { - printf("Slot 0 - Master\nSlave board"); - if (sbcommon_secondary_present()) - printf(" present\n"); - else - printf(" not detected\n"); - } else { - printf("Slot 1 - Slave\n\n"); - } - - printf ("ScanFPGA ID:\t0x%02X\tRev: 0x%02X\n", scan_id, scan_rev); - printf ("Board Rev:\t0x%02X\tID: 0x%02X\n", brd_rev, brd_id); - if(0xF != ofem_brd_id) { - printf("OFemFPGA ID:\t0x%02X\tRev: 0x%02X\n", ofem_id, ofem_rev); - printf("OFEM Board Rev:\t0x%02X\tID: 0x%02X\n", ofem_brd_id, ofem_brd_rev); - } - - /* Fix the ack in the bme 32 */ - udelay(5000); - out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001); - asm("eieio"); - - - return (0); -} - -/************************************************************************* - * misc_init_f - * - * Initialize I2C bus one to gain access to the fans - ************************************************************************/ -int misc_init_f (void) -{ - /* Turn on fans 3 & 4 */ - sbcommon_fans(); - - return (0); -} - -/************************************************************************* - * misc_init_r - * - * Do nothing. - ************************************************************************/ -int misc_init_r (void) -{ - unsigned short sernum; - char envstr[255]; - uchar enetaddr[6]; - KAREF_FPGA_REGS_ST *karef_ps; - OFEM_FPGA_REGS_ST *ofem_ps; - - if(NULL != getenv("secondserial")) { - puts("secondserial is set, switching to second serial port\n"); - setenv("stderr", "serial1"); - setenv("stdout", "serial1"); - setenv("stdin", "serial1"); - } - - setenv("ubrelver", KAREF_U_BOOT_REL_STR); - - memset(envstr, 0, 255); - sprintf (envstr, "Built %s %s by %s", - U_BOOT_DATE, U_BOOT_TIME, BUILDUSER); - setenv("bldstr", envstr); - saveenv(); - - if( getenv("autorecover")) { - setenv("autorecover", NULL); - saveenv(); - sernum = sbcommon_get_serial_number(); - - printf("\nSetting up environment for automatic filesystem recovery\n"); - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - - sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " - "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33", - sernum, sernum); - setenv("bootargs", envstr); - - /* - * Setup Default boot command - */ - setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;" - "fatload ide 0 8100000 pramdisk;" - "bootm 8000000 8100000"); - - printf("Done. Please type allow the system to continue to boot\n"); - } - - if( getenv("fakeled")) { - karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE; - ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE; - ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK; - karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK; - setenv("bootdelay", "-1"); - saveenv(); - printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n"); - } - -#ifdef CONFIG_HAS_ETH0 - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { - board_get_enetaddr(0, enetaddr); - eth_setenv_enetaddr("ethaddr", enetaddr); - } -#endif - -#ifdef CONFIG_HAS_ETH1 - if (!eth_getenv_enetaddr("eth1addr", enetaddr)) { - board_get_enetaddr(1, enetaddr); - eth_setenv_enetaddr("eth1addr", enetaddr); - } -#endif - -#ifdef CONFIG_HAS_ETH2 - if (!eth_getenv_enetaddr("eth2addr", enetaddr)) { - board_get_enetaddr(2, enetaddr); - eth_setenv_enetaddr("eth2addr", enetaddr); - } -#endif - -#ifdef CONFIG_HAS_ETH3 - if (!eth_getenv_enetaddr("eth3addr", enetaddr)) { - board_get_enetaddr(3, enetaddr); - eth_setenv_enetaddr("eth3addr", enetaddr); - } -#endif - - return (0); -} - -/************************************************************************* - * ide_set_reset - ************************************************************************/ -#ifdef CONFIG_IDE_RESET -void ide_set_reset(int on) -{ - KAREF_FPGA_REGS_ST *karef_ps; - /* TODO: ide reset */ - karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE; - - if (on) { - karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK; - } else { - karef_ps->reset_ul |= SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK; - } -} -#endif /* CONFIG_IDE_RESET */ - -/************************************************************************* - * fpga_init - ************************************************************************/ -void fpga_init(void) -{ - KAREF_FPGA_REGS_ST *karef_ps; - OFEM_FPGA_REGS_ST *ofem_ps; - unsigned char ofem_id; - unsigned long tmp; - - /* Ensure we have power all around */ - udelay(500); - - karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE; - tmp = - SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK; - - karef_ps->reset_ul = tmp; - - /* - * Wait a bit to allow the ofem fpga to get its brains - */ - udelay(5000); - - /* - * Check to see if the ofem is there - */ - ofem_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK) - >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT); - if(0xF != ofem_id) { - tmp = - SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK | - SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK | - SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK; - - ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE; - ofem_ps->reset_ul = tmp; - - ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT; - } - - karef_ps->control_ul |= 1 << SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT; - - asm("eieio"); - - return; -} - -int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned short sernum; - char envstr[255]; - - sernum = sbcommon_get_serial_number(); - - memset(envstr, 0, 255); - /* - * Setup our ip address - */ - sprintf(envstr, "10.100.70.%d", sernum); - - setenv("ipaddr", envstr); - /* - * Setup the host ip address - */ - setenv("serverip", "10.100.17.10"); - - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - - sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs " - "rw nfsroot=10.100.17.10:/home/metrobox/mbc70.%d " - "nfsaddrs=10.100.70.%d:10.100.17.10:10.100.1.1:" - "255.255.0.0:karef%d.sandburst.com:eth0:none idebus=33", - sernum, sernum, sernum); - - setenv("bootargs_nfs", envstr); - setenv("bootargs", envstr); - - /* - * Setup CF bootargs - */ - memset(envstr, 0, 255); - - sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 " - "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33", - sernum, sernum); - - setenv("bootargs_cf", envstr); - - /* - * Setup Default boot command - */ - setenv("bootcmd_tftp", "tftp 8000000 uImage.karef;bootm 8000000"); - setenv("bootcmd", "tftp 8000000 uImage.karef;bootm 8000000"); - - /* - * Setup compact flash boot command - */ - setenv("bootcmd_cf", "fatload ide 0 8000000 uimage.karef;bootm 8000000"); - - saveenv(); - - return(1); -} - -int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned short sernum; - char envstr[255]; - - sernum = sbcommon_get_serial_number(); - - printf("\nSetting up environment for filesystem recovery\n"); - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - - sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " - "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none", - sernum, sernum); - setenv("bootargs", envstr); - - /* - * Setup Default boot command - */ - - setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;" - "fatload ide 0 8100000 pramdisk;" - "bootm 8000000 8100000"); - - printf("Done. Please type boot.\nWhen the kernel has booted" - " please type fsrecover.sh\n"); - - return(1); -} - -U_BOOT_CMD(kasetup, 1, 1, karefSetupVars, - "Set environment to factory defaults", ""); - -U_BOOT_CMD(karecover, 1, 1, karefRecover, - "Set environment to allow for fs recovery", ""); diff --git a/board/sandburst/karef/karef.h b/board/sandburst/karef/karef.h deleted file mode 100644 index eb9c314aa9..0000000000 --- a/board/sandburst/karef/karef.h +++ /dev/null @@ -1,60 +0,0 @@ -#ifndef __KAREF_H__ -#define __KAREF_H__ -/* - * (C) Copyright 2005 - * Sandburst Corporation - * Travis B. Sawyer - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Ka Reference Design OFEM FPGA Registers & definitions */ -#include "hal_ka_sc_auto.h" -#include "hal_ka_of_auto.h" - -typedef struct karef_board_id_s { - const char name[40]; -} KAREF_BOARD_ID_ST, *KAREF_BOARD_ID_PST; - -/* SCAN FPGA */ -typedef struct karef_fpga_regs_s -{ - volatile unsigned long revision_ul; /* Read Only */ - volatile unsigned long reset_ul; /* Read/Write */ - volatile unsigned long interrupt_ul; /* Read Only */ - volatile unsigned long mask_ul; /* Read/Write */ - volatile unsigned long scratch_ul; /* Read/Write */ - volatile unsigned long scrmask_ul; /* Read/Write */ - volatile unsigned long status_ul; /* Read Only */ - volatile unsigned long control_ul; /* Read/Write */ - volatile unsigned long boardinfo_ul; /* Read Only */ - volatile unsigned long scan_from0_ul; /* Read Only */ - volatile unsigned long scan_from1_ul; /* Read Only */ - volatile unsigned long scan_to0_ul; /* Read/Write */ - volatile unsigned long scan_to1_ul; /* Read/Write */ - volatile unsigned long scan_control_ul; /* Read/Write */ - volatile unsigned long pll_control_ul; /* Read/Write */ - volatile unsigned long core_clock_cnt_ul; /* Read/Write */ - volatile unsigned long dr_clock_cnt_ul; /* Read/Write */ - volatile unsigned long spi_clock_cnt_ul; /* Read/Write */ - volatile unsigned long brdout_data_ul; /* Read/Write */ - volatile unsigned long brdout_enable_ul; /* Read/Write */ - volatile unsigned long brdin_data_ul; /* Read Only */ - volatile unsigned long misc_ul; /* Read/Write */ -} __attribute__((packed)) KAREF_FPGA_REGS_ST , * KAREF_FPGA_REGS_PST; - -/* OFEM FPGA */ -typedef struct ofem_fpga_regs_s -{ - volatile unsigned long revision_ul; /* Read Only */ - volatile unsigned long reset_ul; /* Read/Write */ - volatile unsigned long interrupt_ul; /* Read Only */ - volatile unsigned long mask_ul; /* Read/Write */ - volatile unsigned long scratch_ul; /* Read/Write */ - volatile unsigned long scrmask_ul; /* Read/Write */ - volatile unsigned long control_ul; /* Read/Write */ - volatile unsigned long mac_flow_ctrl_ul; /* Read/Write */ -} __attribute__((packed)) OFEM_FPGA_REGS_ST , * OFEM_FPGA_REGS_PST; - - -#endif /* __KAREF_H__ */ diff --git a/board/sandburst/karef/karef_version.h b/board/sandburst/karef/karef_version.h deleted file mode 100644 index 6c6baee015..0000000000 --- a/board/sandburst/karef/karef_version.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef _KAREF_VERSION_H_ -#define _KAREF_VERSION_H_ -/* - * Copyright (C) 2005 Sandburst Corporation - * Travis B. Sawyer - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#define KAREF_U_BOOT_REL_STR "Release 0.0.7" -#endif diff --git a/board/sandburst/karef/u-boot.lds.debug b/board/sandburst/karef/u-boot.lds.debug deleted file mode 100644 index c17c8b939b..0000000000 --- a/board/sandburst/karef/u-boot.lds.debug +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (C) Copyright 2002-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/ppc4xx/start.o (.text) - board/sandburst/karef/init.o (.text) - arch/powerpc/cpu/ppc4xx/kgdb.o (.text) - arch/powerpc/cpu/ppc4xx/traps.o (.text) - arch/powerpc/cpu/ppc4xx/interrupts.o (.text) - arch/powerpc/cpu/ppc4xx/4xx_uart.o (.text) - arch/powerpc/cpu/ppc4xx/cpu_init.o (.text) - arch/powerpc/cpu/ppc4xx/speed.o (.text) - drivers/net/4xx_enet.o (.text) - common/dlmalloc.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - lib/zlib.o (.text) - -/* common/env_embedded.o(.text) */ - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/sandburst/metrobox/Kconfig b/board/sandburst/metrobox/Kconfig deleted file mode 100644 index 4a771efef4..0000000000 --- a/board/sandburst/metrobox/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_METROBOX - -config SYS_BOARD - default "metrobox" - -config SYS_VENDOR - default "sandburst" - -config SYS_CONFIG_NAME - default "METROBOX" - -endif diff --git a/board/sandburst/metrobox/MAINTAINERS b/board/sandburst/metrobox/MAINTAINERS deleted file mode 100644 index 71d18f9186..0000000000 --- a/board/sandburst/metrobox/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -METROBOX BOARD -#M: Travis Sawyer -S: Orphan (since 2014-03) -F: board/sandburst/metrobox/ -F: include/configs/METROBOX.h -F: configs/METROBOX_defconfig diff --git a/board/sandburst/metrobox/Makefile b/board/sandburst/metrobox/Makefile deleted file mode 100644 index 2c1028bd2b..0000000000 --- a/board/sandburst/metrobox/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2005 -# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# TBS: add for debugging purposes -ccflags-y += -DBUILDUSER='"$(shell whoami)"' - -obj-y = metrobox.o ../common/flash.o ../common/sb_common.o -extra-y += init.o diff --git a/board/sandburst/metrobox/config.mk b/board/sandburst/metrobox/config.mk deleted file mode 100644 index 23190c8673..0000000000 --- a/board/sandburst/metrobox/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2005 -# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/sandburst/metrobox/hal_xc_auto.h b/board/sandburst/metrobox/hal_xc_auto.h deleted file mode 100644 index c99b38ca06..0000000000 --- a/board/sandburst/metrobox/hal_xc_auto.h +++ /dev/null @@ -1,553 +0,0 @@ -/* **************************************************************** - * Common defs for reg spec for chip xc - * Auto-generated by trex2: DO NOT HAND-EDIT!! - * **************************************************************** - */ - -#ifndef HAL_XC_AUTO_H -#define HAL_XC_AUTO_H - -/* ---------------------------------------------------------------- - * For block: 'xcvr_cntl' - */ - -/* ---- Block instance addressing (for block-select) */ -#define XCVR_CNTL_BLOCK_ADDR_BIT_L 6 -#define XCVR_CNTL_BLOCK_ADDR_BIT_H 9 -#define XCVR_CNTL_BLOCK_ADDR_WIDTH 4 - -#define XCVR_CNTL_ADDR 0x0 - -/* ---- Reg addressing (within block) */ -#define XCVR_CNTL_REG_ADDR_BIT_L 2 -#define XCVR_CNTL_REG_ADDR_BIT_H 5 -#define XCVR_CNTL_REG_ADDR_WIDTH 4 - - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_REVISION */ -#define SAND_HAL_XC_XCVR_CNTL_REVISION_OFFSET 0x000 -#ifndef SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_REVISION_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_REVISION_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_RESET */ -#define SAND_HAL_XC_XCVR_CNTL_RESET_OFFSET 0x004 -#ifndef SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_RESET_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_RESET_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_STATUS */ -#define SAND_HAL_XC_XCVR_CNTL_STATUS_OFFSET 0x008 -#ifndef SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_STATUS_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_STATUS_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_CNTL */ -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OFFSET 0x01c -#ifndef SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_CNTL_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_CNTL_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_BRD_INFO */ -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_OFFSET 0x020 -#ifndef SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_MAC_FLOW_CTL */ -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_OFFSET 0x024 -#ifndef SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_INTERRUPT */ -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OFFSET 0x00c -#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_INTERRUPT_MASK */ -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OFFSET 0x010 -#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_SCRATCH */ -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_OFFSET 0x014 -#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_SCRATCH_MASK */ -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_OFFSET 0x018 -#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_LSB 0 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_REVISION */ -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK 0x0000ff00 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MSB 15 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK 0x000000ff -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_RESET */ -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK 0x00020000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_SHIFT 17 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MSB 17 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_LSB 17 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK 0x00010000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_SHIFT 16 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MSB 16 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_LSB 16 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK 0x00008000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_SHIFT 15 -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MSB 15 -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_LSB 15 -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK 0x00004000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_SHIFT 14 -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MSB 14 -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_LSB 14 -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK 0x00002000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_SHIFT 13 -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MSB 13 -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_LSB 13 -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK 0x00001000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_SHIFT 12 -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MSB 12 -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_LSB 12 -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK 0x00000800 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_SHIFT 11 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MSB 11 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_LSB 11 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK 0x00000400 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_SHIFT 10 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MSB 10 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_LSB 10 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK 0x00000200 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_SHIFT 9 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MSB 9 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_LSB 9 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK 0x00000100 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MSB 8 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK 0x00000080 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_SHIFT 7 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_LSB 7 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK 0x00000040 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_SHIFT 6 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MSB 6 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_LSB 6 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK 0x00000020 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_SHIFT 5 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MSB 5 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_LSB 5 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK 0x00000010 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MSB 4 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK 0x00000008 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_SHIFT 3 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MSB 3 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_LSB 3 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK 0x00000004 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_SHIFT 2 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MSB 2 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_LSB 2 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK 0x00000002 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_SHIFT 1 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_LSB 1 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MSB 0 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_STATUS */ -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MASK 0x00000004 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_SHIFT 2 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MSB 2 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_LSB 2 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MASK 0x00000002 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_SHIFT 1 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_LSB 1 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MASK 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MSB 0 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_CNTL */ -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MASK 0x00000400 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_SHIFT 10 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MSB 10 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_LSB 10 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MASK 0x00000300 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MSB 9 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK 0x000000c0 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT 6 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_LSB 6 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MASK 0x00000030 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MSB 5 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MASK 0x0000000c -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_SHIFT 2 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MSB 3 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_LSB 2 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MASK 0x00000002 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_SHIFT 1 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_LSB 1 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MASK 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MSB 0 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_DEFAULT 0x00000001 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_BRD_INFO */ -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK 0x000000f0 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK 0x00000003 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_MAC_FLOW_CTL */ -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MASK 0x00001000 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_SHIFT 12 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MSB 12 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_LSB 12 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MASK 0x00000f00 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MSB 11 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK 0x00000010 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB 4 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK 0x0000000f -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB 3 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_INTERRUPT */ -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MASK 0x00002000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_SHIFT 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MSB 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_LSB 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MASK 0x00001000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_SHIFT 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MSB 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_LSB 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MASK 0x00000800 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_SHIFT 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MSB 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_LSB 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MASK 0x00000400 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_SHIFT 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MSB 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_LSB 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MASK 0x00000200 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_SHIFT 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MSB 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_LSB 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MASK 0x00000100 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MSB 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MASK 0x00000080 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_SHIFT 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_LSB 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MASK 0x00000040 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_SHIFT 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MSB 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_LSB 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MASK 0x00000020 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_SHIFT 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MSB 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_LSB 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MASK 0x00000010 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MSB 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MASK 0x00000008 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_SHIFT 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MSB 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_LSB 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MASK 0x00000004 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_SHIFT 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MSB 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_LSB 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MASK 0x00000002 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_SHIFT 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_LSB 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MASK 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MSB 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_INTERRUPT_MASK */ -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK 0x00002000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK 0x00001000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK 0x00000800 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK 0x00000400 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK 0x00000200 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK 0x00000100 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK 0x00000080 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK 0x00000040 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK 0x00000020 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK 0x00000010 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK 0x00000008 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK 0x00000004 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK 0x00000002 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT 0x00000001 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_SCRATCH */ -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_SCRATCH_MASK */ -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff - -#endif /* matches #ifndef HAL_XC_AUTO_H */ diff --git a/board/sandburst/metrobox/init.S b/board/sandburst/metrobox/init.S deleted file mode 100644 index 13e340eece..0000000000 --- a/board/sandburst/metrobox/init.S +++ /dev/null @@ -1,37 +0,0 @@ -/* -* Copyright (C) 2005 -* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#include -#include -#include -#include - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) - tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) - tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG) - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG ) - tlbtab_end diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c deleted file mode 100644 index 290fa020f8..0000000000 --- a/board/sandburst/metrobox/metrobox.c +++ /dev/null @@ -1,561 +0,0 @@ -/* - * Copyright (c) 2005 - * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include "metrobox.h" -#include "metrobox_version.h" -#include -#include -#include -#include -#include -#include "../common/sb_common.h" -#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \ - defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) -#include -#endif - -void fpga_init (void); - -METROBOX_BOARD_ID_ST board_id_as[] = -{ {"Undefined"}, /* Not specified */ - {"2x10Gb"}, /* 2 ports, 10 GbE */ - {"20x1Gb"}, /* 20 ports, 1 GbE */ - {"Reserved"}, /* Reserved for future use */ -}; - -/************************************************************************* - * board_early_init_f - * - * Setup chip selects, initialize the Opto-FPGA, initialize - * interrupt polarity and triggers. - ************************************************************************/ -int board_early_init_f (void) -{ - ppc440_gpio_regs_t *gpio_regs; - - /* Enable GPIO interrupts */ - mtsdr(SDR0_PFC0, 0x00103E00); - - /* Setup access for LEDs, and system topology info */ - gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; - gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS; - gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS; - - /* Turn on all the leds for now */ - gpio_regs->out = SBCOMMON_GPIO_LEDS; - - /*--------------------------------------------------------------------+ - | Initialize EBC CONFIG - +-------------------------------------------------------------------*/ - mtebc(EBC0_CFG, - EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | - EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | - EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | - EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | - EBC_CFG_PR_32); - - /*--------------------------------------------------------------------+ - | 1/2 MB FLASH. Initialize bank 0 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB0AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); - /*--------------------------------------------------------------------+ - | 8KB NVRAM/RTC. Initialize bank 1 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB1AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); - - /*--------------------------------------------------------------------+ - | Compact Flash, uses 2 Chip Selects (2 & 6) - +-------------------------------------------------------------------*/ - mtebc(PB2AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); - - /*--------------------------------------------------------------------+ - | OPTO & OFEM FPGA. Initialize bank 3 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB3AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48200000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - | MAC A for metrobox - | MAC A & B for Kamino. OFEM FPGA decodes the addresses - | Initialize bank 4 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB4AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - | Metrobox MAC B Initialize bank 5 with default values. - | KA REF FPGA Initialize bank 5 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB5AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48700000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - | Compact Flash, uses 2 Chip Selects (2 & 6) - +-------------------------------------------------------------------*/ - mtebc(PB6AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); - - /*--------------------------------------------------------------------+ - | BME-32. Initialize bank 7 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB7AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - * Setup the interrupt controller polarities, triggers, etc. - +-------------------------------------------------------------------*/ - /* - * Because of the interrupt handling rework to handle 440GX interrupts - * with the common code, we needed to change names of the UIC registers. - * Here the new relationship: - * - * U-Boot name 440GX name - * ----------------------- - * UIC0 UICB0 - * UIC1 UIC0 - * UIC2 UIC1 - * UIC3 UIC2 - */ - mtdcr (UIC1SR, 0xffffffff); /* clear all */ - mtdcr (UIC1ER, 0x00000000); /* disable all */ - mtdcr (UIC1CR, 0x00000000); /* all non- critical */ - mtdcr (UIC1PR, 0xfffffe03); /* polarity */ - mtdcr (UIC1TR, 0x01c00000); /* trigger edge vs level */ - mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC1SR, 0xffffffff); /* clear all */ - - mtdcr (UIC2SR, 0xffffffff); /* clear all */ - mtdcr (UIC2ER, 0x00000000); /* disable all */ - mtdcr (UIC2CR, 0x00000000); /* all non-critical */ - mtdcr (UIC2PR, 0xffffc8ff); /* polarity */ - mtdcr (UIC2TR, 0x00ff0000); /* trigger edge vs level */ - mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC2SR, 0xffffffff); /* clear all */ - - mtdcr (UIC3SR, 0xffffffff); /* clear all */ - mtdcr (UIC3ER, 0x00000000); /* disable all */ - mtdcr (UIC3CR, 0x00000000); /* all non-critical */ - mtdcr (UIC3PR, 0xffff83ff); /* polarity */ - mtdcr (UIC3TR, 0x00ff8c0f); /* trigger edge vs level */ - mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC3SR, 0xffffffff); /* clear all */ - - mtdcr (UIC0SR, 0xfc000000); /* clear all */ - mtdcr (UIC0ER, 0x00000000); /* disable all */ - mtdcr (UIC0CR, 0x00000000); /* all non-critical */ - mtdcr (UIC0PR, 0xfc000000); - mtdcr (UIC0TR, 0x00000000); - mtdcr (UIC0VR, 0x00000001); - - fpga_init(); - - return 0; -} - -/************************************************************************* - * checkboard - * - * Dump pertinent info to the console - ************************************************************************/ -int checkboard (void) -{ - sys_info_t sysinfo; - unsigned char brd_rev, brd_id; - unsigned short sernum; - unsigned char opto_rev, opto_id; - OPTO_FPGA_REGS_ST *opto_ps; - - opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE; - - opto_rev = (unsigned char)((opto_ps->revision_ul & - SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK) - >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT); - - opto_id = (unsigned char)((opto_ps->revision_ul & - SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK) - >> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT); - - brd_rev = (unsigned char)((opto_ps->boardinfo_ul & - SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK) - >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT); - - brd_id = (unsigned char)((opto_ps->boardinfo_ul & - SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK) - >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT); - - get_sys_info (&sysinfo); - - sernum = sbcommon_get_serial_number(); - printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum); - printf ("%s\n", METROBOX_U_BOOT_REL_STR); - - printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER); - if (sbcommon_get_master()) { - printf("Slot 0 - Master\nSlave board"); - if (sbcommon_secondary_present()) - printf(" present\n"); - else - printf(" not detected\n"); - } else { - printf("Slot 1 - Slave\n\n"); - } - - printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev); - printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id].name); - - /* Fix the ack in the bme 32 */ - udelay(5000); - out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001); - asm("eieio"); - - - return (0); -} - -/************************************************************************* - * misc_init_f - * - * Initialize I2C bus one to gain access to the fans - ************************************************************************/ -int misc_init_f (void) -{ - /* Turn on fans */ - sbcommon_fans(); - - return (0); -} - -/************************************************************************* - * misc_init_r - * - * Do nothing. - ************************************************************************/ -int misc_init_r (void) -{ - unsigned short sernum; - char envstr[255]; - uchar enetaddr[6]; - unsigned char opto_rev; - OPTO_FPGA_REGS_ST *opto_ps; - - opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE; - - if(NULL != getenv("secondserial")) { - puts("secondserial is set, switching to second serial port\n"); - setenv("stderr", "serial1"); - setenv("stdout", "serial1"); - setenv("stdin", "serial1"); - } - - setenv("ubrelver", METROBOX_U_BOOT_REL_STR); - - memset(envstr, 0, 255); - sprintf (envstr, "Built %s %s by %s", - U_BOOT_DATE, U_BOOT_TIME, BUILDUSER); - setenv("bldstr", envstr); - saveenv(); - - if( getenv("autorecover")) { - setenv("autorecover", NULL); - saveenv(); - sernum = sbcommon_get_serial_number(); - - printf("\nSetting up environment for automatic filesystem recovery\n"); - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " - "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33", - sernum, sernum); - setenv("bootargs", envstr); - - /* - * Setup Default boot command - */ - setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;" - "fatload ide 0 8100000 pramdisk;" - "bootm 8000000 8100000"); - - printf("Done. Please type allow the system to continue to boot\n"); - } - - if( getenv("fakeled")) { - setenv("bootdelay", "-1"); - saveenv(); - printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n"); - opto_rev = (unsigned char)((opto_ps->revision_ul & - SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK) - >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT); - - if(0x12 <= opto_rev) { - opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK; - } - } - -#ifdef CONFIG_HAS_ETH0 - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { - board_get_enetaddr(0, enetaddr); - eth_setenv_enetaddr("ethaddr", enetaddr); - } -#endif - -#ifdef CONFIG_HAS_ETH1 - if (!eth_getenv_enetaddr("eth1addr", enetaddr)) { - board_get_enetaddr(1, enetaddr); - eth_setenv_enetaddr("eth1addr", enetaddr); - } -#endif - -#ifdef CONFIG_HAS_ETH2 - if (!eth_getenv_enetaddr("eth2addr", enetaddr)) { - board_get_enetaddr(2, enetaddr); - eth_setenv_enetaddr("eth2addr", enetaddr); - } -#endif - -#ifdef CONFIG_HAS_ETH3 - if (!eth_getenv_enetaddr("eth3addr", enetaddr)) { - board_get_enetaddr(3, enetaddr); - eth_setenv_enetaddr("eth3addr", enetaddr); - } -#endif - - return (0); -} - -/************************************************************************* - * ide_set_reset - ************************************************************************/ -#ifdef CONFIG_IDE_RESET -void ide_set_reset(int on) -{ - OPTO_FPGA_REGS_ST *opto_ps; - opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE; - - if (on) { /* assert RESET */ - opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK; - } else { /* release RESET */ - opto_ps->reset_ul |= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK; - } -} -#endif /* CONFIG_IDE_RESET */ - -/************************************************************************* - * fpga_init - ************************************************************************/ -void fpga_init(void) -{ - OPTO_FPGA_REGS_ST *opto_ps; - unsigned char opto_rev; - unsigned long tmp; - - /* Ensure we have power all around */ - udelay(500); - - /* - * Take appropriate hw bits out of reset - */ - opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE; - - tmp = - SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK; - opto_ps->reset_ul = tmp; - /* - * Turn on the 'Slow Blink' for the System Error Led. - * Ensure FPGA rev is up to at least rev 0x12 - */ - opto_rev = (unsigned char)((opto_ps->revision_ul & - SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK) - >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT); - if(0x12 <= opto_rev) { - opto_ps->control_ul |= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT; - } - - asm("eieio"); - - return; -} - -int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned short sernum; - char envstr[255]; - - sernum = sbcommon_get_serial_number(); - - memset(envstr, 0, 255); - /* - * Setup our ip address - */ - sprintf(envstr, "10.100.60.%d", sernum); - - setenv("ipaddr", envstr); - /* - * Setup the host ip address - */ - setenv("serverip", "10.100.17.10"); - - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - - sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs " - "rw nfsroot=10.100.17.10:/home/metrobox/mbc%d " - "nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1" - ":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33", - sernum, sernum, sernum); - - setenv("bootargs_nfs", envstr); - setenv("bootargs", envstr); - - /* - * Setup CF bootargs - */ - memset(envstr, 0, 255); - sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 " - "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33", - sernum, sernum); - - setenv("bootargs_cf", envstr); - - /* - * Setup Default boot command - */ - setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000"); - setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000"); - - /* - * Setup compact flash boot command - */ - setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000"); - - saveenv(); - - - return(1); -} - -int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned short sernum; - char envstr[255]; - - sernum = sbcommon_get_serial_number(); - - printf("\nSetting up environment for filesystem recovery\n"); - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " - "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none", - sernum, sernum); - - setenv("bootargs", envstr); - - /* - * Setup Default boot command - */ - setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;" - "fatload ide 0 8100000 pramdisk;" - "bootm 8000000 8100000"); - - printf("Done. Please type boot.\nWhen the kernel has booted" - " please type fsrecover.sh\n"); - - return(1); -} - -U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars, - "Set environment to factory defaults", ""); - -U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover, - "Set environment to allow for fs recovery", ""); diff --git a/board/sandburst/metrobox/metrobox.h b/board/sandburst/metrobox/metrobox.h deleted file mode 100644 index d64f496c9a..0000000000 --- a/board/sandburst/metrobox/metrobox.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef __METROBOX_H__ -#define __METROBOX_H__ -/* - * (C) Copyright 2005 - * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -typedef struct metrobox_board_id_s { - const char name[40]; -} METROBOX_BOARD_ID_ST, *METROBOX_BOARD_ID_PST; - - -/* Metrobox Opto-FPGA registers and definitions */ -#include "hal_xc_auto.h" -typedef struct opto_fpga_regs_s { - volatile unsigned long revision_ul; /* Read Only */ - volatile unsigned long reset_ul; /* Read/Write */ - volatile unsigned long status_ul; /* Read Only */ - volatile unsigned long interrupt_ul; /* Read Only */ - volatile unsigned long mask_ul; /* Read/Write */ - volatile unsigned long scratch_ul; /* Read/Write */ - volatile unsigned long scrmask_ul; /* Read/Write */ - volatile unsigned long control_ul; /* Read/Write */ - volatile unsigned long boardinfo_ul; /* Read Only */ -} __attribute__ ((packed)) OPTO_FPGA_REGS_ST , *OPTO_FPGA_REGS_PST; - -#endif /* __METROBOX_H__ */ diff --git a/board/sandburst/metrobox/metrobox_version.h b/board/sandburst/metrobox/metrobox_version.h deleted file mode 100644 index 8264f56d6e..0000000000 --- a/board/sandburst/metrobox/metrobox_version.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef _METROBOX_VERSION_H_ -#define _METROBOX_VERSION_H_ -/* - * (C) Copyright 2005 - * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#define METROBOX_U_BOOT_REL_STR "Release 2.0.3" - -#endif diff --git a/board/sandburst/metrobox/u-boot.lds.debug b/board/sandburst/metrobox/u-boot.lds.debug deleted file mode 100644 index 7ff09c0671..0000000000 --- a/board/sandburst/metrobox/u-boot.lds.debug +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (C) Copyright 2002-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/ppc4xx/start.o (.text) - board/sandburst/metrobox/init.o (.text) - arch/powerpc/cpu/ppc4xx/kgdb.o (.text) - arch/powerpc/cpu/ppc4xx/traps.o (.text) - arch/powerpc/cpu/ppc4xx/interrupts.o (.text) - arch/powerpc/cpu/ppc4xx/4xx_uart.o (.text) - arch/powerpc/cpu/ppc4xx/cpu_init.o (.text) - arch/powerpc/cpu/ppc4xx/speed.o (.text) - drivers/net/4xx_enet.o (.text) - common/dlmalloc.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - lib/zlib.o (.text) - -/* common/env_embedded.o(.text) */ - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} -- cgit v1.2.1 From 1521cdc5303db2a3ec5a09231fbaa5831561bf71 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 29 Sep 2014 01:37:58 +0900 Subject: powerpc: ppc4xx: remove board support for CRAYL1 This board has been orphaned for more than 6 months. Signed-off-by: Masahiro Yamada --- board/cray/L1/.gitignore | 2 - board/cray/L1/Kconfig | 12 -- board/cray/L1/L1.c | 350 -------------------------------- board/cray/L1/MAINTAINERS | 6 - board/cray/L1/Makefile | 23 --- board/cray/L1/bootscript.hush | 117 ----------- board/cray/L1/flash.c | 451 ----------------------------------------- board/cray/L1/init.S | 117 ----------- board/cray/L1/patchme | 30 --- board/cray/L1/u-boot.lds.debug | 121 ----------- board/cray/L1/x2c.awk | 6 - 11 files changed, 1235 deletions(-) delete mode 100644 board/cray/L1/.gitignore delete mode 100644 board/cray/L1/Kconfig delete mode 100644 board/cray/L1/L1.c delete mode 100644 board/cray/L1/MAINTAINERS delete mode 100644 board/cray/L1/Makefile delete mode 100644 board/cray/L1/bootscript.hush delete mode 100644 board/cray/L1/flash.c delete mode 100644 board/cray/L1/init.S delete mode 100644 board/cray/L1/patchme delete mode 100644 board/cray/L1/u-boot.lds.debug delete mode 100644 board/cray/L1/x2c.awk (limited to 'board') diff --git a/board/cray/L1/.gitignore b/board/cray/L1/.gitignore deleted file mode 100644 index cd76d660ef..0000000000 --- a/board/cray/L1/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -bootscript.c -bootscript.image diff --git a/board/cray/L1/Kconfig b/board/cray/L1/Kconfig deleted file mode 100644 index 35a290af61..0000000000 --- a/board/cray/L1/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_CRAYL1 - -config SYS_BOARD - default "L1" - -config SYS_VENDOR - default "cray" - -config SYS_CONFIG_NAME - default "CRAYL1" - -endif diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c deleted file mode 100644 index d706ff10d3..0000000000 --- a/board/cray/L1/L1.c +++ /dev/null @@ -1,350 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define L1_MEMSIZE (32*1024*1024) - -/* the std. DHCP stufff */ -#define DHCP_ROUTER 3 -#define DHCP_NETMASK 1 -#define DHCP_BOOTFILE 67 -#define DHCP_ROOTPATH 17 -#define DHCP_HOSTNAME 12 - -/* some extras used by CRAY - * - * on the server this looks like: - * - * option L1-initrd-image code 224 = string; - * option L1-initrd-image "/opt/craysv2/craymcu/l1/flash/initrd.image" - */ -#define DHCP_L1_INITRD 224 - -/* new, [better?] way via official vendor-extensions, defining an option - * space. - * on the server this looks like: - * - * option space CRAYL1; - * option CRAYL1.initrd code 3 = string; - * ..etc... - */ -#define DHCP_VENDOR_SPECX 43 -#define DHCP_VX_INITRD 3 -#define DHCP_VX_BOOTCMD 4 -#define DHCP_VX_BOOTARGS 5 -#define DHCP_VX_ROOTDEV 6 -#define DHCP_VX_FROMFLASH 7 -#define DHCP_VX_BOOTSCRIPT 8 -#define DHCP_VX_RCFILE 9 -#define DHCP_VX_MAGIC 10 - -/* Things DHCP server can tellme about. If there's no flash address, then - * they dont participate in 'update' to flash, and we force their values - * back to '0' every boot to be sure to get them fresh from DHCP. Yes, I - * know this is a pain... - * - * If I get no bootfile, boot from flash. If rootpath, use that. If no - * rootpath use initrd in flash. - */ -typedef struct dhcp_item_s { - u8 dhcp_option; - u8 dhcp_vendor_option; - char *dhcpvalue; - char *envname; -} dhcp_item_t; -static dhcp_item_t Things[] = { - {DHCP_ROUTER, 0, NULL, "gateway"}, - {DHCP_NETMASK, 0, NULL, "netmask"}, - {DHCP_BOOTFILE, 0, NULL, "bootfile"}, - {DHCP_ROOTPATH, 0, NULL, "rootpath"}, - {DHCP_HOSTNAME, 0, NULL, "hostname"}, - {DHCP_L1_INITRD, 0, NULL, "initrd"}, -/* and the other way.. */ - {DHCP_VENDOR_SPECX, DHCP_VX_INITRD, NULL, "initrd"}, - {DHCP_VENDOR_SPECX, DHCP_VX_BOOTCMD, NULL, "bootcmd"}, - {DHCP_VENDOR_SPECX, DHCP_VX_FROMFLASH, NULL, "fromflash"}, - {DHCP_VENDOR_SPECX, DHCP_VX_BOOTSCRIPT, NULL, "bootscript"}, - {DHCP_VENDOR_SPECX, DHCP_VX_RCFILE, NULL, "rcfile"}, - {DHCP_VENDOR_SPECX, DHCP_VX_BOOTARGS, NULL, "xbootargs"}, - {DHCP_VENDOR_SPECX, DHCP_VX_ROOTDEV, NULL, NULL}, - {DHCP_VENDOR_SPECX, DHCP_VX_MAGIC, NULL, NULL} -}; - -#define N_THINGS ((sizeof(Things))/(sizeof(dhcp_item_t))) - -extern char bootscript[]; - -/* Here is the boot logic as HUSH script. Overridden by any TFP provided - * bootscript file. - */ - -static void init_sdram (void); - -/* ------------------------------------------------------------------------- */ -int board_early_init_f (void) -{ - /* Running from ROM: global data is still READONLY */ - init_sdram (); - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */ - mtdcr (UIC0PR, 0xFFFFFFE0); /* set int polarities */ - mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - return 0; -} - -/* ------------------------------------------------------------------------- */ -int checkboard (void) -{ - return (0); -} -/* ------------------------------------------------------------------------- */ - -/* ------------------------------------------------------------------------- */ -int misc_init_r (void) -{ - char *s, *e; - image_header_t *hdr; - time_t timestamp; - struct rtc_time tm; - char bootcmd[32]; - - hdr = (image_header_t *) (CONFIG_SYS_MONITOR_BASE - image_get_header_size ()); -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - timestamp = (time_t)image_get_time (hdr); - to_tm (timestamp, &tm); - printf ("Welcome to U-Boot on Cray L1. Compiled %4d-%02d-%02d %2d:%02d:%02d (UTC)\n", tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec); - -#define FACTORY_SETTINGS 0xFFFC0000 - if ((s = getenv ("ethaddr")) == NULL) { - e = (char *) (FACTORY_SETTINGS); - if (*(e + 0) != '0' - || *(e + 1) != '0' - || *(e + 2) != ':' - || *(e + 3) != '4' || *(e + 4) != '0' || *(e + 17) != '\0') { - printf ("No valid MAC address in flash location 0x3C0000!\n"); - } else { - printf ("Factory MAC: %s\n", e); - setenv ("ethaddr", e); - } - } - sprintf (bootcmd,"source %X",(unsigned)bootscript); - setenv ("bootcmd", bootcmd); - return (0); -} - -/* ------------------------------------------------------------------------- */ -/* stubs so we can print dates w/o any nvram RTC.*/ -int rtc_get (struct rtc_time *tmp) -{ - return 0; -} -int rtc_set (struct rtc_time *tmp) -{ - return 0; -} -void rtc_reset (void) -{ - return; -} - -/* ------------------------------------------------------------------------- */ -/* Do sdram bank init in C so I can read it..no console to print to yet! - */ -static void init_sdram (void) -{ - unsigned long tmp; - - /* write SDRAM bank 0 register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); - mtdcr (SDRAM0_CFGDATA, 0x00062001); - -/* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */ -/* To set the appropriate timings, we need to know the SDRAM speed. */ -/* We can use the PLB speed since the SDRAM speed is the same as */ -/* the PLB speed. The PLB speed is the FBK divider times the */ -/* 405GP reference clock, which on the L1 is 25MHz. */ -/* Thus, if FBK div is 2, SDRAM is 50MHz; if FBK div is 3, SDRAM is */ -/* 150MHz; if FBK is 3, SDRAM is 150MHz. */ - - /* divisor = ((mfdcr(strap)>> 28) & 0x3); */ - -/* write SDRAM timing for 100MHz. */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); - mtdcr (SDRAM0_CFGDATA, 0x0086400D); - -/* write SDRAM refresh interval register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); - mtdcr (SDRAM0_CFGDATA, 0x05F00000); - udelay (200); - -/* sdram controller.*/ - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); - mtdcr (SDRAM0_CFGDATA, 0x90800000); - udelay (200); - -/* initially, disable ECC on all banks */ - udelay (200); - mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); - tmp = mfdcr (SDRAM0_CFGDATA); - tmp &= 0xff0fffff; - mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); - mtdcr (SDRAM0_CFGDATA, tmp); - - return; -} - -extern int memory_post_test (int flags); - -int testdram (void) -{ - unsigned long tmp; - uint *pstart = (uint *) 0x00000000; - uint *pend = (uint *) L1_MEMSIZE; - uint *p; - - if (getenv_f("booted",NULL,0) <= 0) - { - printf ("testdram.."); - /*AA*/ - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x, was %08x expected %08x\n", - (uint) p, *p, 0xaaaaaaaa); - return 1; - } - } - /*55*/ - for (p = pstart; p < pend; p++) - *p = 0x55555555; - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x, was %08x expected %08x\n", - (uint) p, *p, 0x55555555); - return 1; - } - } - /*addr*/ - for (p = pstart; p < pend; p++) - *p = (unsigned)p; - for (p = pstart; p < pend; p++) { - if (*p != (unsigned)p) { - printf ("SDRAM test fails at: %08x, was %08x expected %08x\n", - (uint) p, *p, (uint)p); - return 1; - } - } - printf ("Success. "); - } - printf ("Enable ECC.."); - - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); - tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000; - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); - mtdcr (SDRAM0_CFGDATA, tmp); - udelay (600); - for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE); *p++ = 0L) - ; - udelay (400); - mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); - tmp = mfdcr (SDRAM0_CFGDATA); - tmp |= 0x00800000; - mtdcr (SDRAM0_CFGDATA, tmp); - udelay (400); - printf ("enabled.\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ -static u8 *dhcp_env_update (u8 thing, u8 * pop) -{ - u8 i, oplen; - - oplen = *(pop + 1); - - if ((Things[thing].dhcpvalue = malloc (oplen)) == NULL) { - printf ("Whoops! failed to malloc space for DHCP thing %s\n", - Things[thing].envname); - return NULL; - } - for (i = 0; (i < oplen); i++) - if ((*(Things[thing].dhcpvalue + i) = *(pop + 2 + i)) == ' ') - break; - *(Things[thing].dhcpvalue + i) = '\0'; - -/* set env. */ - if (Things[thing].envname) - { - setenv (Things[thing].envname, Things[thing].dhcpvalue); - } - return ((u8 *)(Things[thing].dhcpvalue)); -} - -/* ------------------------------------------------------------------------- */ -u8 *dhcp_vendorex_prep (u8 * e) -{ - u8 thing; - -/* ask for the things I want. */ - *e++ = 55; /* Parameter Request List */ - *e++ = N_THINGS; - for (thing = 0; thing < N_THINGS; thing++) - *e++ = Things[thing].dhcp_option; - *e++ = 255; - - return e; -} - -/* ------------------------------------------------------------------------- */ -/* .. return NULL means it wasnt mine, non-null means I got it..*/ -u8 *dhcp_vendorex_proc (u8 * pop) -{ - u8 oplen, *sub_op, sub_oplen, *retval; - u8 thing = 0; - - retval = NULL; - oplen = *(pop + 1); -/* if pop is vender spec indicator, there are sub-options. */ - if (*pop == DHCP_VENDOR_SPECX) { - for (sub_op = pop + 2; - oplen && (sub_oplen = *(sub_op + 1)); - oplen -= sub_oplen, sub_op += (sub_oplen + 2)) { - for (thing = 0; thing < N_THINGS; thing++) { - if (*sub_op == Things[thing].dhcp_vendor_option) { - if (!(retval = dhcp_env_update (thing, sub_op))) { - return NULL; - } - } - } - } - } else { - for (thing = 0; thing < N_THINGS; thing++) { - if (*pop == Things[thing].dhcp_option) - if (!(retval = dhcp_env_update (thing, pop))) - return NULL; - } - } - return (pop); -} diff --git a/board/cray/L1/MAINTAINERS b/board/cray/L1/MAINTAINERS deleted file mode 100644 index e43e91febe..0000000000 --- a/board/cray/L1/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -L1 BOARD -#M: David Updegraff -S: Orphan (since 2014-03) -F: board/cray/L1/ -F: include/configs/CRAYL1.h -F: configs/CRAYL1_defconfig diff --git a/board/cray/L1/Makefile b/board/cray/L1/Makefile deleted file mode 100644 index 716a5a316b..0000000000 --- a/board/cray/L1/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = L1.o flash.o -obj-y += init.o -obj-y += bootscript.o - -quiet_cmd_awk = AWK $@ - cmd_awk = od -t x1 -v -A x $< | $(AWK) -f $(filter-out $<,$^) > $@ - -$(obj)/bootscript.c: $(obj)/bootscript.image $(src)/x2c.awk - $(call cmd,awk) - -MKIMAGEFLAGS_bootscript.image := -A ppc -O linux -T script -C none \ - -a 0 -e 0 -n bootscript -$(obj)/bootscript.image: $(src)/bootscript.hush - $(call cmd,mkimage) - -clean-files := bootscript.c bootscript.image diff --git a/board/cray/L1/bootscript.hush b/board/cray/L1/bootscript.hush deleted file mode 100644 index f2f78ad5c3..0000000000 --- a/board/cray/L1/bootscript.hush +++ /dev/null @@ -1,117 +0,0 @@ -# $Header$ -# hush bootscript for PPCBOOT on L1 -# note: all #s are in hex, do _NOT_ prefix it with 0x - -flash_rfs=ffc00000 -flash_krl=fff00000 -tftp_addr=100000 -tftp2_addr=1000000 - -if printenv booted -then - echo already booted before -else - echo first boot in environment, create and save settings - setenv booted OK - saveenv -fi - -setenv autoload no -# clear out stale env stuff, so we get fresh from dhcp. -for setting in initrd fromflash kernel rootfs rootpath -do -setenv $setting -done - -dhcp - -# if host provides us with a different bootscript, us it. -if printenv bootscript - then - tftp $tftp_addr $bootcript - if imi $tftp_addr - then - source $tftp_addr - fi -fi - -# default base kernel arguments. -setenv bootargs $xbootargs devfs=mount ip=$ipaddr:$serverip:$gatewayip:$netmask:L1:eth0:off wdt=120 - -# Have a kernel in flash? -if imi $flash_krl -then - echo ok kernel to boot from $flash_krl - setenv kernel $flash_krl -else - echo no kernel to boot from $flash_krl, need tftp -fi - -# Have a rootfs in flash? -echo test for SQUASHfs at $flash_rfs - -if imi $flash_rfs -then - echo appears to be a good initrd image at base of flash OK - setenv rootfs $flash_rfs -else - echo no image at base of flash, need nfsroot or initrd -fi - -# I boot from flash if told to and I can. -if printenv fromflash && printenv kernel && printenv rootfs -then - echo booting entirely from flash - setenv bootargs root=/dev/ram0 rw $bootargs - bootm $kernel $rootfs - echo oh no failed so I try some other stuff -fi - -# TFTP down a kernel -if printenv bootfile -then - tftp $tftp_addr $bootfile - setenv kernel $tftp_addr - echo I will boot the TFTP kernel -else - if printenv kernel - then - echo no bootfile specified, will use one from flash - else - setenv bootfile /opt/crayx1/craymcu/l1/flash/linux.image - echo OH NO! we have no bootfile,nor flash kernel! try default: $bootfile - tftp $tftp_addr $bootfile - setenv kernel $tftp_addr - fi -fi - -# the rootfs. -if printenv rootpath -then - echo rootpath is $rootpath - if printenv initrd - then - echo initrd is also specified, so use $initrd - tftp $tftp2_addr $initrd - setenv bootargs root=/dev/ram0 rw cwsroot=$serverip:$rootpath $bootargs - bootm $kernel $tftp2_addr - else - echo initrd is not specified, so use NFSROOT $rootpat - setenv bootargs root=/dev/nfs ro nfsroot=$serverip:$rootpath $bootargs - bootm $kernel - fi -else - echo we have no rootpath check for one in flash - if printenv rootfs - then - echo I will use the one in flash - setenv bootargs root=/dev/mtdblock/0 ro rootfstype=squashfs $bootargs - bootm $kernel - else - setenv rootpath /export/crayl1 - echo OH NO! we have no rootpath,nor flash kernel! try default: $rootpath - setenv bootargs root=/dev/mtdblock/0 ro rootfstype=squashfs $bootargs - bootm $kernel - fi -fi -reset diff --git a/board/cray/L1/flash.c b/board/cray/L1/flash.c deleted file mode 100644 index 96a1e474a5..0000000000 --- a/board/cray/L1/flash.c +++ /dev/null @@ -1,451 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -/* - * Modified July 20, 2001 - * Strip down to support ONLY the AMD29F032B. - * Dave Updegraff - Cray, Inc. dave@cray.com - */ - -#include -#include -#include - -/* The flash chip we use... */ -#define AMD_ID_F032B 0x41 /* 29F032B ID 32 Mbit,64 64Kx8 sectors */ -#define FLASH_AM320B 0x0009 - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned char - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; isector_count; i++) - info->start[i] = base + (i * 0x00010000); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM320B:printf ("AM29F032B (32 Mbit 64x64KB uniform sectors)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; kstart[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong)addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; - - /* Write auto select command: read Manufacturer ID */ - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; - - value = addr2[0]; - - switch (value) { - case (FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - - switch (value) { - case (FLASH_WORD_SIZE)AMD_ID_F032B: - info->flash_id += FLASH_AM320B; - info->sector_count = 64; - info->size = 0x0400000; /* => 4 MB */ - break; - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); - info->protect[i] = addr2[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - } - - return (info->size); -} - -int wait_for_DQ7(flash_info_t *info, int sect) -{ - ulong start, now, last; - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); - - start = get_timer (0); - last = start; - while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - return 0; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); - printf("Erasing sector %p\n", addr2); - - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; - ulong start; - int flag; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile FLASH_WORD_SIZE *)dest) & - (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++) - { - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != - (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/cray/L1/init.S b/board/cray/L1/init.S deleted file mode 100644 index d4723c733f..0000000000 --- a/board/cray/L1/init.S +++ /dev/null @@ -1,117 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0 IBM-pibs - */ - -/*----------------------------------------------------------------------------- */ -/* Function: ext_bus_cntlr_init */ -/* Description: Initializes the External Bus Controller for the external */ -/* peripherals. IMPORTANT: For pass1 this code must run from */ -/* cache since you can not reliably change a peripheral banks */ -/* timing register (pbxap) while running code from that bank. */ -/* For ex., since we are running from ROM on bank 0, we can NOT */ -/* execute the code that modifies bank 0 timings from ROM, so */ -/* we run it from cache. */ -/* Bank 0 - Flash and SRAM */ -/* Bank 1 - NVRAM/RTC */ -/* Bank 2 - Keyboard/Mouse controller */ -/* Bank 3 - IR controller */ -/* Bank 4 - not used */ -/* Bank 5 - not used */ -/* Bank 6 - not used */ -/* Bank 7 - FPGA registers */ -/*-----------------------------------------------------------------------------#include */ -#include - -#include -#include - -#include -#include - -/* CRAY - L1: only nominally a 'walnut', since ext.Bus.Cntlr is all empty */ -/* except for #1 which we use for DMA'ing to IOCA-like things, so the */ -/* control registers to set that up are determined by what we've */ -/* empirically discovered work there. */ - - .globl ext_bus_cntlr_init -ext_bus_cntlr_init: - mflr r4 /* save link register */ - bl ..getAddr -..getAddr: - mflr r3 /* get address of ..getAddr */ - mtlr r4 /* restore link register */ - addi r4,0,14 /* set ctr to 10; used to prefetch */ - mtctr r4 /* 10 cache lines to fit this function */ - /* in cache (gives us 8x10=80 instrctns) */ -..ebcloop: - icbt r0,r3 /* prefetch cache line for addr in r3 */ - addi r3,r3,32 /* move to next cache line */ - bdnz ..ebcloop /* continue for 10 cache lines */ - - /*------------------------------------------------------------------- */ - /* Delay to ensure all accesses to ROM are complete before changing */ - /* bank 0 timings. 200usec should be enough. */ - /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ - /*------------------------------------------------------------------- */ - addis r3,0,0x0 - ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ - mtctr r3 -..spinlp: - bdnz ..spinlp /* spin loop */ - - - /*---------------------------------------------------------------------- */ - /* Peripheral Bank 0 (Flash) initialization */ - /*---------------------------------------------------------------------- */ - /* 0x7F8FFE80 slowest boot */ - addi r4,0,PB1AP - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x9B01 - ori r4,r4,0x5480 - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB0CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0xFFC5 /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */ - ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ - mtdcr EBC0_CFGDATA,r4 - - blr - - /*---------------------------------------------------------------------- */ - /* Peripheral Bank 1 (NVRAM/RTC) initialization */ - /* CRAY:the L1 has NOT this bank, it is tied to SV2/IOCA/etc/ instead */ - /* and we do DMA on it. The ConfigurationRegister part is threfore */ - /* almost arbitrary, except that our linux driver needs to know the */ - /* address, but it can query, it.. */ - /* */ - /* The AccessParameter is CRITICAL, */ - /* thouch, since it needs to agree with the electrical timings on the */ - /* IOCA parallel interface. That value is: 0x0185,4380 */ - /* BurstModeEnable BME=0 */ - /* TransferWait TWT=3 */ - /* ChipSelectOnTiming CSN=1 */ - /* OutputEnableOnTimimg OEN=1 */ - /* WriteByteEnableOnTiming WBN=1 */ - /* WriteByteEnableOffTiming WBF=0 */ - /* TransferHold TH=1 */ - /* ReadyEnable RE=1 */ - /* SampleOnReady SOR=1 */ - /* ByteEnableMode BEM=0 */ - /* ParityEnable PEN=0 */ - /* all reserved bits=0 */ - /*---------------------------------------------------------------------- */ - /*---------------------------------------------------------------------- */ - addi r4,0,PB1AP - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x0185 /* hiword */ - ori r4,r4,0x4380 /* loword */ - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB1CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0xF001 /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */ - ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ - mtdcr EBC0_CFGDATA,r4 - - blr diff --git a/board/cray/L1/patchme b/board/cray/L1/patchme deleted file mode 100644 index e77ee7e1f5..0000000000 --- a/board/cray/L1/patchme +++ /dev/null @@ -1,30 +0,0 @@ -# master confi.mk -echo "CROSS_COMPILE = powerpc-linux-" >>include/config.mk - -# patch the examples/Makefile to ignore return value from OBJCOPY -sed -e 's/$(OBJCOPY)/-&/' < examples/Makefile > examples/makefile - -# add a built target for mkimage on the target architecture -sed -e 's/^all:.*$/all: .depend envcrc mkimage mkimage.ppc/' < tools/Makefile > tools/makefile - -cat <>tools/makefile -mkimage.ppc : mkimage.o.ppc crc32.o.ppc - powerpc-linux-gcc -msoft-float -Wall -Wstrict-prototypes -o \$@ \$^ - powerpc-linux-strip $@ - -XFLAGS="-D__KERNEL__ -I../include -DCONFIG_4xx -Wall -Wstict-prototypes" -mkimage.o.ppc: mkimage.c - powerpc-linux-gcc -msoft-float -Wall -I../include -c -o \$@ \$^ - -crc32.o.ppc: crc32.c - powerpc-linux-gcc -msoft-float -Wall -I../include -c -o \$@ \$^ - -EOF - -# make an image by default out of the u-boot image -sed -e 's/^all:.*$/all: u-boot.image /' < Makefile > makefile -cat <>makefile -u-boot.image: u-boot.bin - tools/mkimage -A ppc -O linux -T firmware -C none -a 0 -e 0 -n U-Boot -d \$^ \$@ - -EOF diff --git a/board/cray/L1/u-boot.lds.debug b/board/cray/L1/u-boot.lds.debug deleted file mode 100644 index 890f592e9b..0000000000 --- a/board/cray/L1/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/cray/L1/x2c.awk b/board/cray/L1/x2c.awk deleted file mode 100644 index 9235e6cb36..0000000000 --- a/board/cray/L1/x2c.awk +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/awk -BEGIN { print "unsigned char bootscript[] = { \n"} -{ for (i = 2; i <= NF ; i++ ) printf "0x"$i"," - print "" -} -END { print "\n};\n" } -- cgit v1.2.1 From 9ed3246e19a42392bf0fd676dcbbe3539cc46ec1 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 29 Sep 2014 01:37:59 +0900 Subject: powerpc: ppc4xx: remove board support for bluestone This board has been orphaned for more than 6 months. It is the last board defining CONFIG_APM821XX. The code inside #ifdef CONFIG_APM821XX should be removed too. Signed-off-by: Masahiro Yamada --- board/amcc/bluestone/Kconfig | 12 ----- board/amcc/bluestone/MAINTAINERS | 6 --- board/amcc/bluestone/Makefile | 9 ---- board/amcc/bluestone/bluestone.c | 99 ---------------------------------------- board/amcc/bluestone/config.mk | 18 -------- board/amcc/bluestone/init.S | 45 ------------------ 6 files changed, 189 deletions(-) delete mode 100644 board/amcc/bluestone/Kconfig delete mode 100644 board/amcc/bluestone/MAINTAINERS delete mode 100644 board/amcc/bluestone/Makefile delete mode 100644 board/amcc/bluestone/bluestone.c delete mode 100644 board/amcc/bluestone/config.mk delete mode 100644 board/amcc/bluestone/init.S (limited to 'board') diff --git a/board/amcc/bluestone/Kconfig b/board/amcc/bluestone/Kconfig deleted file mode 100644 index 255e013777..0000000000 --- a/board/amcc/bluestone/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_BLUESTONE - -config SYS_BOARD - default "bluestone" - -config SYS_VENDOR - default "amcc" - -config SYS_CONFIG_NAME - default "bluestone" - -endif diff --git a/board/amcc/bluestone/MAINTAINERS b/board/amcc/bluestone/MAINTAINERS deleted file mode 100644 index 9eb9bbd01b..0000000000 --- a/board/amcc/bluestone/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -BLUESTONE BOARD -#M: Tirumala Marri -S: Orphan (since 2014-03) -F: board/amcc/bluestone/ -F: include/configs/bluestone.h -F: configs/bluestone_defconfig diff --git a/board/amcc/bluestone/Makefile b/board/amcc/bluestone/Makefile deleted file mode 100644 index 07320ce425..0000000000 --- a/board/amcc/bluestone/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright (c) 2010, Applied Micro Circuits Corporation -# Author: Tirumala R Marri -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := bluestone.o -extra-y += init.o diff --git a/board/amcc/bluestone/bluestone.c b/board/amcc/bluestone/bluestone.c deleted file mode 100644 index 6520f75c68..0000000000 --- a/board/amcc/bluestone/bluestone.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Bluestone board support - * - * Copyright (c) 2010, Applied Micro Circuits Corporation - * Author: Tirumala R Marri - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -int board_early_init_f(void) -{ - /* - * Setup the interrupt controller polarities, triggers, etc. - */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - mtdcr(UIC2ER, 0x00000000); /* disable all */ - mtdcr(UIC2CR, 0x00000000); /* all non-critical */ - mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - - mtdcr(UIC3SR, 0xffffffff); /* clear all */ - mtdcr(UIC3ER, 0x00000000); /* disable all */ - mtdcr(UIC3CR, 0x00000000); /* all non-critical */ - mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC3SR, 0xffffffff); /* clear all */ - - /* - * Configure PFC (Pin Function Control) registers - * UART0: 2 pins - */ - mtsdr(SDR0_PFC1, 0x0000000); - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts("Board: Bluestone Evaluation Board"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -int misc_init_r(void) -{ - u32 sdr0_srst1 = 0; - - /* Setup PLB4-AHB bridge based on the system address map */ - mtdcr(AHB_TOP, 0x8000004B); - mtdcr(AHB_BOT, 0x8000004B); - - /* - * The AHB Bridge core is held in reset after power-on or reset - * so enable it now - */ - mfsdr(SDR0_SRST1, sdr0_srst1); - sdr0_srst1 &= ~SDR0_SRST1_AHB; - mtsdr(SDR0_SRST1, sdr0_srst1); - - return 0; -} diff --git a/board/amcc/bluestone/config.mk b/board/amcc/bluestone/config.mk deleted file mode 100644 index a947e82af7..0000000000 --- a/board/amcc/bluestone/config.mk +++ /dev/null @@ -1,18 +0,0 @@ -# -# Copyright (c) 2010, Applied Micro Circuits Corporation -# Author: Tirumala R Marri -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Applied Micro APM821XX Evaluation board. -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/amcc/bluestone/init.S b/board/amcc/bluestone/init.S deleted file mode 100644 index cf22ca6340..0000000000 --- a/board/amcc/bluestone/init.S +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2010, Applied Micro Circuits Corporation - * Author: Tirumala R Marri - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* TLB 0 */ - tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, - 4, AC_RWX | SA_G) - - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, - 0, AC_RWX | SA_G) - - /* TLB-entry for OCM */ - tlbentry(CONFIG_SYS_OCM_BASE, SZ_64K, 0x00040000, 4, - AC_RWX | SA_I) - - /* TLB-entry for Local Configuration registers => peripherals */ - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, - CONFIG_SYS_PERIPHERAL_BASE, 4, AC_RWX | SA_IG) - tlbtab_end -- cgit v1.2.1 From e7a565638a7a727f1a4074c0b39e7de22ff3d6c9 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 29 Sep 2014 01:38:00 +0900 Subject: powerpc: mpc83xx: remove board support for MERGERBOX and MVBLM7 These boards have been orphaned for more than 6 months. Signed-off-by: Masahiro Yamada --- board/matrix_vision/mergerbox/Kconfig | 12 -- board/matrix_vision/mergerbox/MAINTAINERS | 6 - board/matrix_vision/mergerbox/Makefile | 8 - board/matrix_vision/mergerbox/README | 59 -------- board/matrix_vision/mergerbox/fpga.c | 158 -------------------- board/matrix_vision/mergerbox/fpga.h | 13 -- board/matrix_vision/mergerbox/mergerbox.c | 235 ------------------------------ board/matrix_vision/mergerbox/mergerbox.h | 61 -------- board/matrix_vision/mergerbox/pci.c | 128 ---------------- board/matrix_vision/mergerbox/sm107.c | 120 --------------- board/matrix_vision/mvblm7/.gitignore | 1 - board/matrix_vision/mvblm7/Kconfig | 12 -- board/matrix_vision/mvblm7/MAINTAINERS | 6 - board/matrix_vision/mvblm7/Makefile | 14 -- board/matrix_vision/mvblm7/README.mvblm7 | 84 ----------- board/matrix_vision/mvblm7/bootscript | 43 ------ board/matrix_vision/mvblm7/fpga.c | 169 --------------------- board/matrix_vision/mvblm7/fpga.h | 17 --- board/matrix_vision/mvblm7/mvblm7.c | 136 ----------------- board/matrix_vision/mvblm7/mvblm7.h | 20 --- board/matrix_vision/mvblm7/pci.c | 89 ----------- 21 files changed, 1391 deletions(-) delete mode 100644 board/matrix_vision/mergerbox/Kconfig delete mode 100644 board/matrix_vision/mergerbox/MAINTAINERS delete mode 100644 board/matrix_vision/mergerbox/Makefile delete mode 100644 board/matrix_vision/mergerbox/README delete mode 100644 board/matrix_vision/mergerbox/fpga.c delete mode 100644 board/matrix_vision/mergerbox/fpga.h delete mode 100644 board/matrix_vision/mergerbox/mergerbox.c delete mode 100644 board/matrix_vision/mergerbox/mergerbox.h delete mode 100644 board/matrix_vision/mergerbox/pci.c delete mode 100644 board/matrix_vision/mergerbox/sm107.c delete mode 100644 board/matrix_vision/mvblm7/.gitignore delete mode 100644 board/matrix_vision/mvblm7/Kconfig delete mode 100644 board/matrix_vision/mvblm7/MAINTAINERS delete mode 100644 board/matrix_vision/mvblm7/Makefile delete mode 100644 board/matrix_vision/mvblm7/README.mvblm7 delete mode 100644 board/matrix_vision/mvblm7/bootscript delete mode 100644 board/matrix_vision/mvblm7/fpga.c delete mode 100644 board/matrix_vision/mvblm7/fpga.h delete mode 100644 board/matrix_vision/mvblm7/mvblm7.c delete mode 100644 board/matrix_vision/mvblm7/mvblm7.h delete mode 100644 board/matrix_vision/mvblm7/pci.c (limited to 'board') diff --git a/board/matrix_vision/mergerbox/Kconfig b/board/matrix_vision/mergerbox/Kconfig deleted file mode 100644 index 3857535a25..0000000000 --- a/board/matrix_vision/mergerbox/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MERGERBOX - -config SYS_BOARD - default "mergerbox" - -config SYS_VENDOR - default "matrix_vision" - -config SYS_CONFIG_NAME - default "MERGERBOX" - -endif diff --git a/board/matrix_vision/mergerbox/MAINTAINERS b/board/matrix_vision/mergerbox/MAINTAINERS deleted file mode 100644 index 20bd073b90..0000000000 --- a/board/matrix_vision/mergerbox/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MERGERBOX BOARD -#M: Andre Schwarz -S: Orphan (since 2014-03) -F: board/matrix_vision/mergerbox/ -F: include/configs/MERGERBOX.h -F: configs/MERGERBOX_defconfig diff --git a/board/matrix_vision/mergerbox/Makefile b/board/matrix_vision/mergerbox/Makefile deleted file mode 100644 index 11a7fd2c7c..0000000000 --- a/board/matrix_vision/mergerbox/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += mergerbox.o pci.o fpga.o sm107.o diff --git a/board/matrix_vision/mergerbox/README b/board/matrix_vision/mergerbox/README deleted file mode 100644 index 1994b65be1..0000000000 --- a/board/matrix_vision/mergerbox/README +++ /dev/null @@ -1,59 +0,0 @@ -Matrix Vision MergerBox ------------------------ - -1. Board Description - - The MergerBox is a 120x160mm single board computing platform - for 3D Full-HD digital video processing. - - Power Supply is 10-32VDC. - -2 System Components - -2.1 CPU - Freescale MPC8377 CPU running at 800MHz core and 333MHz csb. - 256 MByte DDR-II memory @ 333MHz data rate. - 64 MByte Nor Flash on local bus. - 1 GByte Nand Flash on FCM. - 1 Vitesse VSC8601 RGMII ethernet Phys. - 1 USB host controller over ULPI I/F with 4-Port hub. - 2 serial ports. Console running on ttyS0 @ 115200 8N1. - 1 mPCIe expansion slot (PCIe x1 + USB) used for Wifi/Bt. - 2 PCIe x1 busses on local mPCIe and cutom expansion connector. - 2 SATA host ports. - System configuration (HRCW) is taken from I2C EEPROM. - -2.2 Graphics - SM107 emebedded video controller driving a 5" 800x480 TFT panel. - Connected over 32-Bit/66MHz PCI utilizing 4 MByte embedded memory. - -2.3 FPGA - Altera Cyclone-IV EP4C115 with several PCI DMA engines. - Connects to 7x Gennum 3G-SDI transceivers as video interconnect - as well as a HDMI v1.4 compliant output for 3D monitoring. - Utilizes two more DDR-II controllers providing 256MB memory. - -2.4 I2C - Bus1: - AD7418 @ 0x50 for voltage/temp. monitoring. - SX8650 @ 0x90 touch controller for HMI. - EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics. - Bus2: - mPCIe SMBus - SiI9022A @ 0x72/0xC0 HDMI transmitter. - TCA6416A @ 0x40 + 0x42 16-Bit I/O expander. - LMH1983 @ 0xCA video PLL. - DS1338C @ 0xD0 real-time clock with embedded crystal. - 9FG104 @ 0xDC 4x 100MHz LVDS SerDes reference clock. - -3 Flash layout. - - reset vector is 0x00000100, i.e. low boot. - - 00000000 u-boot binary. - 00100000 FPGA raw bit file. - 00300000 FIT image holding kernel, dtb and rescue squashfs. - 03d00000 u-boot environment. - 03e00000 splash image - - mtd partitions are propagated to linux kernel via device tree blob. diff --git a/board/matrix_vision/mergerbox/fpga.c b/board/matrix_vision/mergerbox/fpga.c deleted file mode 100644 index 57552c1ae6..0000000000 --- a/board/matrix_vision/mergerbox/fpga.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * (C) Copyright 2011 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "mergerbox.h" -#include "fpga.h" - -Altera_CYC2_Passive_Serial_fns altera_fns = { - fpga_null_fn, - fpga_config_fn, - fpga_status_fn, - fpga_done_fn, - fpga_wr_fn, - fpga_null_fn, - fpga_null_fn, -}; - -Altera_desc cyclone2 = { - Altera_CYC2, - passive_serial, - Altera_EP2C20_SIZE, - (void *) &altera_fns, - NULL, - 0 -}; - -DECLARE_GLOBAL_DATA_PTR; - -int mergerbox_init_fpga(void) -{ - debug("Initialize FPGA interface\n"); - fpga_init(); - fpga_add(fpga_altera, &cyclone2); - - return 1; -} - -int fpga_null_fn(int cookie) -{ - return 0; -} - -int fpga_config_fn(int assert, int flush, int cookie) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; - u32 dvo = gpio->dat; - - dvo &= ~FPGA_CONFIG; - gpio->dat = dvo; - udelay(5); - dvo |= FPGA_CONFIG; - gpio->dat = dvo; - - return assert; -} - -int fpga_done_fn(int cookie) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; - int result = 0; - - udelay(10); - debug("CONF_DONE check ... "); - if (gpio->dat & FPGA_CONF_DONE) { - debug("high\n"); - result = 1; - } else - debug("low\n"); - - return result; -} - -int fpga_status_fn(int cookie) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; - int result = 0; - - debug("STATUS check ... "); - if (gpio->dat & FPGA_STATUS) { - debug("high\n"); - result = 1; - } else - debug("low\n"); - - return result; -} - -int fpga_clk_fn(int assert_clk, int flush, int cookie) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; - u32 dvo = gpio->dat; - - debug("CLOCK %s\n", assert_clk ? "high" : "low"); - if (assert_clk) - dvo |= FPGA_CCLK; - else - dvo &= ~FPGA_CCLK; - - if (flush) - gpio->dat = dvo; - - return assert_clk; -} - -static inline int _write_fpga(u8 val, int dump) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; - int i; - u32 dvo = gpio->dat; - - if (dump) - debug(" %02x -> ", val); - for (i = 0; i < 8; i++) { - dvo &= ~FPGA_CCLK; - gpio->dat = dvo; - dvo &= ~FPGA_DIN; - if (dump) - debug("%d ", val&1); - if (val & 1) - dvo |= FPGA_DIN; - gpio->dat = dvo; - dvo |= FPGA_CCLK; - gpio->dat = dvo; - val >>= 1; - } - if (dump) - debug("\n"); - - return 0; -} - -int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) -{ - unsigned char *data = (unsigned char *) buf; - int i; - - debug("fpga_wr: buf %p / size %d\n", buf, len); - for (i = 0; i < len; i++) - _write_fpga(data[i], 0); - debug("\n"); - - return FPGA_SUCCESS; -} diff --git a/board/matrix_vision/mergerbox/fpga.h b/board/matrix_vision/mergerbox/fpga.h deleted file mode 100644 index dbe9bff25f..0000000000 --- a/board/matrix_vision/mergerbox/fpga.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ - */ - -extern int mergerbox_init_fpga(void); - -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int fpga_status_fn(int cookie); -extern int fpga_config_fn(int assert, int flush, int cookie); -extern int fpga_done_fn(int cookie); -extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie); -extern int fpga_null_fn(int cookie); diff --git a/board/matrix_vision/mergerbox/mergerbox.c b/board/matrix_vision/mergerbox/mergerbox.c deleted file mode 100644 index 5c891d1283..0000000000 --- a/board/matrix_vision/mergerbox/mergerbox.c +++ /dev/null @@ -1,235 +0,0 @@ -/* - * Copyright (C) 2007 Freescale Semiconductor, Inc. - * - * Copyright (C) 2011 Matrix Vision GmbH - * Andre Schwarz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "mergerbox.h" -#include "fpga.h" -#include "../common/mv_common.h" - -static void setup_serdes(void) -{ - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); -} - -#if defined(CONFIG_SYS_DRAM_TEST) -int testdram(void) -{ - uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; - uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; - uint *p; - - printf("Testing DRAM from 0x%08x to 0x%08x\n", - CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END); - - printf("DRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test passed.\n"); - return 0; -} -#endif - -phys_size_t initdram(int board_type) -{ - u32 msize; - - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile clk83xx_t *clk = (clk83xx_t *)&immr->clk; - - /* Enable PCI_CLK[0:1] */ - clk->occr |= 0xc0000000; - udelay(2000); - -#if defined(CONFIG_SPD_EEPROM) - msize = spd_sdram(); -#else - immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize_log2; - - msize = CONFIG_SYS_DDR_SIZE; - msize_log2 = __ilog2(msize); - - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; - im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); - - im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; - udelay(50000); - - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; - udelay(1000); - - im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; - udelay(1000); - - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - __asm__ __volatile__("sync"); - udelay(1000); - - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - udelay(2000); -#endif - setup_serdes(); - - return msize << 20; -} - -int checkboard(void) -{ - puts("Board: Matrix Vision MergerBox\n"); - - return 0; -} - -int misc_init_r(void) -{ - u16 dim; - int result; - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&immr->gpio[1]; - unsigned char mac[6], mac_verify[6]; - char *s = getenv("reset_env"); - - for (dim = 10; dim < 180; dim += 5) { - mergerbox_tft_dim(dim); - udelay(100000); - } - - if (s) - mv_reset_environment(); - - i2c_read(SPD_EEPROM_ADDRESS, 0x80, 2, mac, sizeof(mac)); - - /* check if Matrix Vision prefix present and export to env */ - if (mac[0] == 0x00 && mac[1] == 0x0c && mac[2] == 0x8d) { - printf("valid MAC found in eeprom: %pM\n", mac); - eth_setenv_enetaddr("ethaddr", mac); - } else { - printf("no valid MAC found in eeprom.\n"); - - /* no: check the env */ - if (!eth_getenv_enetaddr("ethaddr", mac)) { - printf("no valid MAC found in env either.\n"); - /* TODO: ask for valid MAC */ - } else { - printf("valid MAC found in env: %pM\n", mac); - printf("updating MAC in eeprom.\n"); - - do { - result = test_and_clear_bit(20, &gpio->dat); - if (result) - printf("unprotect EEPROM failed !\n"); - udelay(20000); - } while(result); - - i2c_write(SPD_EEPROM_ADDRESS, 0x80, 2, mac, 6); - udelay(20000); - - do { - result = test_and_set_bit(20, &gpio->dat); - if (result) - printf("protect EEPROM failed !\n"); - udelay(20000); - } while(result); - - printf("verify MAC %pM ... ", mac); - i2c_read(SPD_EEPROM_ADDRESS, 0x80, 2, mac_verify, 6); - - if (!strncmp((char *)mac, (char *)mac_verify, 6)) - printf("ok.\n"); - else - /* TODO: retry or do something useful */ - printf("FAILED (got %pM) !\n", mac_verify); - } - } - - return 0; -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - - iopd->dat &= ~TFT_SPI_CPLD_CS; -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - - iopd->dat |= TFT_SPI_CPLD_CS; -} - -/* control backlight pwm (display brightness). - * allow values 0-250 with 0 = turn off and 250 = max brightness - */ -void mergerbox_tft_dim(u16 value) -{ - struct spi_slave *slave; - u16 din; - u16 dout = 0; - - if (value > 0 && value < 250) - dout = 0x4000 | value; - - slave = spi_setup_slave(0, 0, 1000000, SPI_MODE_0 | SPI_CS_HIGH); - spi_claim_bus(slave); - spi_xfer(slave, 16, &dout, &din, SPI_XFER_BEGIN | SPI_XFER_END); - spi_release_bus(slave); - spi_free_slave(slave); -} - -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - fdt_fixup_dr_usb(blob, bd); - ft_pci_setup(blob, bd); -} diff --git a/board/matrix_vision/mergerbox/mergerbox.h b/board/matrix_vision/mergerbox/mergerbox.h deleted file mode 100644 index 53eab28f3d..0000000000 --- a/board/matrix_vision/mergerbox/mergerbox.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (C) 2011 Matrix Vision GmbH - * Andre Schwarz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MERGERBOX_H__ -#define __MERGERBOX_H__ - -#define MV_GPIO - -/* - * GPIO Bank 1 - */ -#define TFT_SPI_EN (0x80000000>>0) -#define FPGA_CONFIG (0x80000000>>1) -#define FPGA_STATUS (0x80000000>>2) -#define FPGA_CONF_DONE (0x80000000>>3) -#define FPGA_DIN (0x80000000>>4) -#define FPGA_CCLK (0x80000000>>5) -#define MAN_RST (0x80000000>>6) -#define FPGA_SYS_RST (0x80000000>>7) -#define WD_WDI (0x80000000>>8) -#define TFT_RST (0x80000000>>9) -#define HISCON_GPIO1 (0x80000000>>10) -#define HISCON_GPIO2 (0x80000000>>11) -#define B2B_GPIO2 (0x80000000>>12) -#define CCU_GPIN (0x80000000>>13) -#define CCU_GPOUT (0x80000000>>14) -#define TFT_GPIO0 (0x80000000>>15) -#define TFT_GPIO1 (0x80000000>>16) -#define TFT_GPIO2 (0x80000000>>17) -#define TFT_GPIO3 (0x80000000>>18) -#define B2B_GPIO0 (0x80000000>>19) -#define B2B_GPIO1 (0x80000000>>20) -#define TFT_SPI_CPLD_CS (0x80000000>>21) -#define TFT_SPI_CS (0x80000000>>22) -#define CCU_PWR_EN (0x80000000>>23) -#define B2B_GPIO3 (0x80000000>>24) -#define CCU_PWR_STAT (0x80000000>>25) - -#define MV_GPIO1_DAT (FPGA_CONFIG|CCU_PWR_EN|TFT_SPI_CPLD_CS) -#define MV_GPIO1_OUT (TFT_SPI_EN|FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|CCU_PWR_EN| \ - TFT_SPI_CPLD_CS) -#define MV_GPIO1_ODE (FPGA_CONFIG|MAN_RST) - -/* - * GPIO Bank 2 - */ -#define SPI_FLASH_WP (0x80000000>>10) -#define SYS_EEPROM_WP (0x80000000>>11) -#define SPI_FLASH_CS (0x80000000>>22) - -#define MV_GPIO2_DAT (SYS_EEPROM_WP|SPI_FLASH_CS) -#define MV_GPIO2_OUT (SPI_FLASH_WP|SYS_EEPROM_WP|SPI_FLASH_CS) -#define MV_GPIO2_ODE 0 - -void mergerbox_tft_dim(u16 value); - -#endif diff --git a/board/matrix_vision/mergerbox/pci.c b/board/matrix_vision/mergerbox/pci.c deleted file mode 100644 index 480f3ed387..0000000000 --- a/board/matrix_vision/mergerbox/pci.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. - * - * Copyright (C) 2011 Matrix Vision GmbH - * Andre Schwarz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include "mergerbox.h" -#include "fpga.h" -#include "../common/mv_common.h" - -static struct pci_region pci_regions[] = { - { - .bus_start = CONFIG_SYS_PCI_MEM_BASE, - .phys_start = CONFIG_SYS_PCI_MEM_PHYS, - .size = CONFIG_SYS_PCI_MEM_SIZE, - .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - .bus_start = CONFIG_SYS_PCI_MMIO_BASE, - .phys_start = CONFIG_SYS_PCI_MMIO_PHYS, - .size = CONFIG_SYS_PCI_MMIO_SIZE, - .flags = PCI_REGION_MEM - }, - { - .bus_start = CONFIG_SYS_PCI_IO_BASE, - .phys_start = CONFIG_SYS_PCI_IO_PHYS, - .size = CONFIG_SYS_PCI_IO_SIZE, - .flags = PCI_REGION_IO - } -}; - -static struct pci_region pcie_regions_0[] = { - { - .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, - .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, - .size = CONFIG_SYS_PCIE1_MEM_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCIE1_IO_BASE, - .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, - .size = CONFIG_SYS_PCIE1_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -static struct pci_region pcie_regions_1[] = { - { - .bus_start = CONFIG_SYS_PCIE2_MEM_BASE, - .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS, - .size = CONFIG_SYS_PCIE2_MEM_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCIE2_IO_BASE, - .phys_start = CONFIG_SYS_PCIE2_IO_PHYS, - .size = CONFIG_SYS_PCIE2_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -void pci_init_board(void) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile sysconf83xx_t *sysconf = &immr->sysconf; - volatile clk83xx_t *clk = (clk83xx_t *)&immr->clk; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; - volatile law83xx_t *pcie_law = sysconf->pcielaw; - struct pci_region *reg[] = { pci_regions }; - struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, }; - - volatile gpio83xx_t *gpio; - gpio = (gpio83xx_t *)&immr->gpio[0]; - - gpio->dat = MV_GPIO1_DAT; - gpio->odr = MV_GPIO1_ODE; - gpio->dir = MV_GPIO1_OUT; - - gpio = (gpio83xx_t *)&immr->gpio[1]; - - gpio->dat = MV_GPIO2_DAT; - gpio->odr = MV_GPIO2_ODE; - gpio->dir = MV_GPIO2_OUT; - - printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh, - immr->sysconf.sicrl); - - /* Enable PCI_CLK[0:1] */ - clk->occr |= 0xc0000000; - udelay(2000); - - mergerbox_init_fpga(); - mv_load_fpga(); - - mergerbox_tft_dim(0); - - /* Configure PCI Local Access Windows */ - pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - - pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - - udelay(2000); - - mpc83xx_pci_init(1, reg); - - /* Deassert the resets in the control register */ - out_be32(&sysconf->pecr1, 0xE0008000); - out_be32(&sysconf->pecr2, 0xE0008000); - udelay(2000); - - out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); - out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); - - out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); - out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); - - mpc83xx_pcie_init(2, pcie_reg); -} diff --git a/board/matrix_vision/mergerbox/sm107.c b/board/matrix_vision/mergerbox/sm107.c deleted file mode 100644 index d24f926269..0000000000 --- a/board/matrix_vision/mergerbox/sm107.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (C) 2011 Matrix Vision GmbH - * Andre Schwarz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include "../common/mv_common.h" - -#ifdef CONFIG_VIDEO -static const SMI_REGS init_regs_800x480[] = { - /* set endianess to little endian */ - {0x0005c, 0x00000000}, - /* PCI drive 12mA */ - {0x00004, 0x42401001}, - /* current clock */ - {0x0003c, 0x310a1818}, - /* clocks for pm0... */ - {0x00040, 0x0002184f}, - {0x00044, 0x2a1a0a01}, - /* GPIO */ - {0x10008, 0x00000000}, - {0x1000C, 0x00000000}, - /* panel control regs */ - {0x80000, 0x0f017106}, - {0x80004, 0x0}, - {0x80008, 0x0}, - {0x8000C, 0x00000000}, - {0x80010, 0x0c800c80}, - /* width 0x320 */ - {0x80014, 0x03200000}, - /* height 0x1e0 */ - {0x80018, 0x01E00000}, - {0x8001C, 0x0}, - {0x80020, 0x01df031f}, - {0x80024, 0x041f031f}, - {0x80028, 0x00800347}, - {0x8002C, 0x020c01df}, - {0x80030, 0x000201e9}, - {0x80200, 0x00000000}, - /* ZV[0:7] */ - {0x00008, 0x00ff0000}, - /* 24-Bit TFT */ - {0x0000c, 0x3f000000}, - {0, 0} -}; - -/* - * Returns SM107 register base address. First thing called in the driver. - */ -unsigned int board_video_init(void) -{ - pci_dev_t devbusfn; - u32 addr; - - devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); - if (devbusfn != -1) { - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, - (u32 *)&addr); - return addr & 0xfffffffe; - } - - return 0; -} - -/* - * Called after initializing the SM501 and before clearing the screen. - */ -void board_validate_screen(unsigned int base) -{ -} - -/* - * Returns SM107 framebuffer address - */ -unsigned int board_video_get_fb(void) -{ - pci_dev_t devbusfn; - u32 addr; - - devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); - if (devbusfn != -1) { - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, - (u32 *)&addr); - addr &= 0xfffffffe; -#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET - addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET; -#endif - return addr; - } - - printf("board_video_get_fb(): FAILED\n"); - - return 0; -} - -/* - * Return a pointer to the initialization sequence. - */ -const SMI_REGS *board_get_regs(void) -{ - return init_regs_800x480; -} - -int board_get_width(void) -{ - return 800; -} - -int board_get_height(void) -{ - return 480; -} -#endif diff --git a/board/matrix_vision/mvblm7/.gitignore b/board/matrix_vision/mvblm7/.gitignore deleted file mode 100644 index 469f1bc4c1..0000000000 --- a/board/matrix_vision/mvblm7/.gitignore +++ /dev/null @@ -1 +0,0 @@ -bootscript.img diff --git a/board/matrix_vision/mvblm7/Kconfig b/board/matrix_vision/mvblm7/Kconfig deleted file mode 100644 index ea7a6f82c0..0000000000 --- a/board/matrix_vision/mvblm7/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MVBLM7 - -config SYS_BOARD - default "mvblm7" - -config SYS_VENDOR - default "matrix_vision" - -config SYS_CONFIG_NAME - default "MVBLM7" - -endif diff --git a/board/matrix_vision/mvblm7/MAINTAINERS b/board/matrix_vision/mvblm7/MAINTAINERS deleted file mode 100644 index 947a14ed50..0000000000 --- a/board/matrix_vision/mvblm7/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MVBLM7 BOARD -#M: Andre Schwarz -S: Orphan (since 2014-03) -F: board/matrix_vision/mvblm7/ -F: include/configs/MVBLM7.h -F: configs/MVBLM7_defconfig diff --git a/board/matrix_vision/mvblm7/Makefile b/board/matrix_vision/mvblm7/Makefile deleted file mode 100644 index caa6cfd34c..0000000000 --- a/board/matrix_vision/mvblm7/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# -# Copyright (C) Freescale Semiconductor, Inc. 2006. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mvblm7.o pci.o fpga.o - -extra-y := bootscript.img - -MKIMAGEFLAGS_bootscript.image := -T script -C none -n M7_script - -$(obj)/bootscript.img: $(src)/bootscript - $(call cmd,mkimage) diff --git a/board/matrix_vision/mvblm7/README.mvblm7 b/board/matrix_vision/mvblm7/README.mvblm7 deleted file mode 100644 index a0686f7fa5..0000000000 --- a/board/matrix_vision/mvblm7/README.mvblm7 +++ /dev/null @@ -1,84 +0,0 @@ -Matrix Vision mvBlueLYNX-M7 (mvBL-M7) -------------------------------------- - -1. Board Description - - The mvBL-M7 is a 120x120mm single board computing platform - with strong focus on stereo image processing applications. - - Power Supply is either VDC 12-48V or Pover over Ethernet (PoE) - on any port (requires add-on board). - -2 System Components - -2.1 CPU - Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb. - 512MByte DDR-II memory @ 133MHz. - 8 MByte Nor Flash on local bus. - 2 Vitesse VSC8601 RGMII ethernet Phys. - 1 USB host controller over ULPI I/F. - 2 serial ports. Console running on ttyS0 @ 115200 8N1. - 1 SD-Card slot connected to SPI. - System configuration (HRCW) is taken from I2C EEPROM. - -2.2 PCI - A miniPCI Type-III socket is present. PCI clock fixed at 66MHz. - -2.3 FPGA - Altera Cyclone-II EP2C20/35 with PCI DMA engines. - Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces. - Utilizes another 256MB DDR-II memory and 32-128MB Nand Flash. - -2.3.1 I/O @ FPGA - 2x8 Outputs : Infineon High-Side Switches to Main Supply. - 2x8 Inputs : Programmable input threshold + trigger capabilities - 2 dedicated flash interfaces for illuminator boards. - Cross trigger for chaining several boards. - -2.4 I2C - Bus1: - MAX5381 DAC @ 0x60 for 1st digital input threshold. - LM75 @ 0x90 for temperature monitoring. - EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics. - 1st image sensor interface (slave addresses depend on sensor) - Bus2: - MAX5381 DAC @ 0x60 for 2nd digital input threshold. - 2nd image sensor interface (slave addresses depend on sensor) - -3 Flash layout. - - reset vector is 0xFFF00100, i.e. "HIGHBOOT". - - FF800000 environment - FF802000 redundant environment - FF804000 u-boot script image - FF806000 redundant u-boot script image - FF808000 device tree blob - FF80A000 redundant device tree blob - FF80C000 tbd. - FF80E000 tbd. - FF810000 kernel - FFC00000 root FS - FFF00000 u-boot - FFF80000 FPGA raw bit file - - mtd partitions are propagated to linux kernel via device tree blob. - -4 Booting - - On startup the bootscript @ FF804000 is executed. This script can be - exchanged easily. Default boot mode is "boot from flash", i.e. system - works stand-alone. - - This behaviour depends on some environment variables : - - "netboot" : yes ->try dhcp/bootp and boot from network. - A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for - DHCP server configuration, e.g. to provide different images to - different devices. - - During netboot the system tries to get 3 image files: - 1. Kernel - name + data is given during BOOTP. - 2. Initrd - name is stored in "initrd_name" - 3. device tree blob - name is stored in "dtb_name" - Fallback files are the flash versions. diff --git a/board/matrix_vision/mvblm7/bootscript b/board/matrix_vision/mvblm7/bootscript deleted file mode 100644 index dc385fde79..0000000000 --- a/board/matrix_vision/mvblm7/bootscript +++ /dev/null @@ -1,43 +0,0 @@ -echo -echo "==== running autoscript ====" -echo -setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram} -setenv ramkernel setenv kernel_boot \${loadaddr} -setenv flashkernel setenv kernel_boot \${mv_kernel_addr} -setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length} -setenv bootfromflash run flashkernel cpird ramparam addcons bootdtb -setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name} -setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000 -setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup -setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel -if test ${console} = yes; -then -setenv addcons setenv bootargs \${bootargs} console=ttyS\${console_nr},\${baudrate}N8 -else -setenv addcons setenv bootargs \${bootargs} console=tty0 -fi -setenv set_static_ip setenv ipaddr \${static_ipaddr} -setenv set_static_nm setenv netmask \${static_netmask} -setenv set_static_gw setenv gatewayip \${static_gateway} -setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask} -setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs -if test ${autoscript_boot} != no; -then - if test ${netboot} = yes; - then - bootp - if test $? = 0; - then - echo "=== bootp succeeded -> netboot ===" - run set_ip - run getdtb rundtb bootfromnet ramparam addcons bootdtb - else - echo "=== netboot failed ===" - fi - fi - run set_static_ip set_static_nm set_static_gw set_ip - echo "=== bootfromflash ===" - run cpdtb rundtb bootfromflash -else - echo "=== boot stopped with autoscript_boot no ===" -fi diff --git a/board/matrix_vision/mvblm7/fpga.c b/board/matrix_vision/mvblm7/fpga.c deleted file mode 100644 index c0c5bedb2a..0000000000 --- a/board/matrix_vision/mvblm7/fpga.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * (C) Copyright 2008 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "fpga.h" -#include "mvblm7.h" - -#ifdef FPGA_DEBUG -#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args) -#else -#define fpga_debug(fmt, args...) -#endif - -Altera_CYC2_Passive_Serial_fns altera_fns = { - fpga_null_fn, - fpga_config_fn, - fpga_status_fn, - fpga_done_fn, - fpga_wr_fn, - fpga_null_fn, - fpga_null_fn, -}; - -Altera_desc cyclone2 = { - Altera_CYC2, - passive_serial, - Altera_EP2C20_SIZE, - (void *) &altera_fns, - NULL, - 0 -}; - -DECLARE_GLOBAL_DATA_PTR; - -int mvblm7_init_fpga(void) -{ - fpga_debug("Initialize FPGA interface\n"); - fpga_init(); - fpga_add(fpga_altera, &cyclone2); - fpga_config_fn(0, 1, 0); - udelay(60); - - return 1; -} - -int fpga_null_fn(int cookie) -{ - return 0; -} - -int fpga_config_fn(int assert, int flush, int cookie) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - u32 dvo = gpio->dat; - - fpga_debug("SET config : %s\n", assert ? "low" : "high"); - if (assert) - dvo |= FPGA_CONFIG; - else - dvo &= ~FPGA_CONFIG; - - if (flush) - gpio->dat = dvo; - - return assert; -} - -int fpga_done_fn(int cookie) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - int result = 0; - - udelay(10); - fpga_debug("CONF_DONE check ... "); - if (gpio->dat & FPGA_CONF_DONE) { - fpga_debug("high\n"); - result = 1; - } else - fpga_debug("low\n"); - - return result; -} - -int fpga_status_fn(int cookie) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - int result = 0; - - fpga_debug("STATUS check ... "); - if (gpio->dat & FPGA_STATUS) { - fpga_debug("high\n"); - result = 1; - } else - fpga_debug("low\n"); - - return result; -} - -int fpga_clk_fn(int assert_clk, int flush, int cookie) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - u32 dvo = gpio->dat; - - fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low"); - if (assert_clk) - dvo |= FPGA_CCLK; - else - dvo &= ~FPGA_CCLK; - - if (flush) - gpio->dat = dvo; - - return assert_clk; -} - -static inline int _write_fpga(u8 val, int dump) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - int i; - u32 dvo = gpio->dat; - - if (dump) - fpga_debug(" %02x -> ", val); - for (i = 0; i < 8; i++) { - dvo &= ~FPGA_CCLK; - gpio->dat = dvo; - dvo &= ~FPGA_DIN; - if (dump) - fpga_debug("%d ", val&1); - if (val & 1) - dvo |= FPGA_DIN; - gpio->dat = dvo; - dvo |= FPGA_CCLK; - gpio->dat = dvo; - val >>= 1; - } - if (dump) - fpga_debug("\n"); - - return 0; -} - -int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) -{ - unsigned char *data = (unsigned char *) buf; - int i; - - fpga_debug("fpga_wr: buf %p / size %d\n", buf, len); - for (i = 0; i < len; i++) - _write_fpga(data[i], 0); - fpga_debug("\n"); - - return FPGA_SUCCESS; -} diff --git a/board/matrix_vision/mvblm7/fpga.h b/board/matrix_vision/mvblm7/fpga.h deleted file mode 100644 index b480c09b24..0000000000 --- a/board/matrix_vision/mvblm7/fpga.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -extern int mvblm7_init_fpga(void); - -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int fpga_status_fn(int cookie); -extern int fpga_config_fn(int assert, int flush, int cookie); -extern int fpga_done_fn(int cookie); -extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie); -extern int fpga_null_fn(int cookie); diff --git a/board/matrix_vision/mvblm7/mvblm7.c b/board/matrix_vision/mvblm7/mvblm7.c deleted file mode 100644 index f3c16a3e9c..0000000000 --- a/board/matrix_vision/mvblm7/mvblm7.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006. - * - * (C) Copyright 2008 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#if defined(CONFIG_OF_LIBFDT) -#include -#endif - -#include "../common/mv_common.h" -#include "mvblm7.h" - -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - char *s = getenv("ddr_size"); - - msize = CONFIG_SYS_DDR_SIZE; - if (s) { - u32 env_ddr_size = simple_strtoul(s, NULL, 10); - if (env_ddr_size == 512) - msize = 512; - } - - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); - ddr_size = ddr_size >> 1, ddr_size_log2++) { - if (ddr_size & 1) - return -1; - } - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; - im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & - LAWAR_SIZE); - - im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; - - asm("sync;isync"); - udelay(600); - - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - - asm("sync;isync"); - udelay(500); - - return msize; -} - -phys_size_t initdram(int board_type) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = 0; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) - return -1; - - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; - msize = fixed_sdram(); - - /* return total bus RAM size(bytes) */ - return msize * 1024 * 1024; -} - -int misc_init_r(void) -{ - char *s = getenv("reset_env"); - - if (s) { - mv_reset_environment(); - } - - return 0; -} - -int checkboard(void) -{ - puts("Board: Matrix Vision mvBlueLYNX-M7\n"); - - return 0; -} - -#ifdef CONFIG_HARD_SPI -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - - iopd->dat &= ~MVBLM7_MMC_CS; -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - - iopd->dat |= ~MVBLM7_MMC_CS; -} -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif -} - -#endif diff --git a/board/matrix_vision/mvblm7/mvblm7.h b/board/matrix_vision/mvblm7/mvblm7.h deleted file mode 100644 index de9fec7fb8..0000000000 --- a/board/matrix_vision/mvblm7/mvblm7.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef __MVBC_H__ -#define __MVBC_H__ - -#define MV_GPIO - -#define FPGA_CONFIG 0x80000000 -#define FPGA_CCLK 0x40000000 -#define FPGA_DIN 0x20000000 -#define FPGA_STATUS 0x10000000 -#define FPGA_CONF_DONE 0x08000000 - -#define WD_WDI 0x00400000 -#define WD_TS 0x00200000 -#define MAN_RST 0x00100000 - -#define MV_GPIO_DAT (WD_TS) -#define MV_GPIO_OUT (FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|MVBLM7_MMC_CS) -#define MV_GPIO_ODE (FPGA_CONFIG|MAN_RST) - -#endif diff --git a/board/matrix_vision/mvblm7/pci.c b/board/matrix_vision/mvblm7/pci.c deleted file mode 100644 index f14837ad40..0000000000 --- a/board/matrix_vision/mvblm7/pci.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006. - * - * (C) Copyright 2008 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#if defined(CONFIG_OF_LIBFDT) -#include -#endif -#include -#include -#include -#include "mvblm7.h" -#include "fpga.h" -#include "../common/mv_common.h" - -DECLARE_GLOBAL_DATA_PTR; - -static struct pci_region pci_regions[] = { - { - bus_start: CONFIG_SYS_PCI1_MEM_BASE, - phys_start: CONFIG_SYS_PCI1_MEM_PHYS, - size: CONFIG_SYS_PCI1_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI1_MMIO_BASE, - phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, - size: CONFIG_SYS_PCI1_MMIO_SIZE, - flags: PCI_REGION_MEM - }, - { - bus_start: CONFIG_SYS_PCI1_IO_BASE, - phys_start: CONFIG_SYS_PCI1_IO_PHYS, - size: CONFIG_SYS_PCI1_IO_SIZE, - flags: PCI_REGION_IO - } -}; - -void pci_init_board(void) -{ - int i; - volatile immap_t *immr; - volatile pcictrl83xx_t *pci_ctrl; - volatile gpio83xx_t *gpio; - volatile clk83xx_t *clk; - volatile law83xx_t *pci_law; - struct pci_region *reg[] = { pci_regions }; - - immr = (immap_t *) CONFIG_SYS_IMMR; - clk = (clk83xx_t *) &immr->clk; - pci_ctrl = immr->pci_ctrl; - pci_law = immr->sysconf.pcilaw; - gpio = (volatile gpio83xx_t *)&immr->gpio[0]; - - gpio->dat = MV_GPIO_DAT; - gpio->odr = MV_GPIO_ODE; - gpio->dir = MV_GPIO_OUT; - - printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh, - immr->sysconf.sicrl); - - mvblm7_init_fpga(); - mv_load_fpga(); - - gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK); - - /* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */ - clk->occr = 0xc0000000; - - pci_ctrl[0].gcr = 0; - udelay(2000); - pci_ctrl[0].gcr = 1; - - for (i = 0; i < 1000; ++i) - udelay(1000); - - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB; - - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - - mpc83xx_pci_init(1, reg); -} -- cgit v1.2.1 From af55e35d33894295cf0f2f94c050f67d05b50944 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 29 Sep 2014 01:38:01 +0900 Subject: powerpc: mpc5xxx: remove board support for MVBC_P and MVSMR These boards have been orphaned for more than 6 months. Signed-off-by: Masahiro Yamada --- board/matrix_vision/mvbc_p/Kconfig | 12 -- board/matrix_vision/mvbc_p/MAINTAINERS | 6 - board/matrix_vision/mvbc_p/Makefile | 11 -- board/matrix_vision/mvbc_p/README.mvbc_p | 73 -------- board/matrix_vision/mvbc_p/fpga.c | 157 ----------------- board/matrix_vision/mvbc_p/fpga.h | 17 -- board/matrix_vision/mvbc_p/mvbc_p.c | 255 --------------------------- board/matrix_vision/mvbc_p/mvbc_p.h | 43 ----- board/matrix_vision/mvbc_p/mvbc_p_autoscript | 48 ----- board/matrix_vision/mvsmr/.gitignore | 1 - board/matrix_vision/mvsmr/Kconfig | 12 -- board/matrix_vision/mvsmr/MAINTAINERS | 6 - board/matrix_vision/mvsmr/Makefile | 18 -- board/matrix_vision/mvsmr/README.mvsmr | 55 ------ board/matrix_vision/mvsmr/bootscript | 42 ----- board/matrix_vision/mvsmr/fpga.c | 112 ------------ board/matrix_vision/mvsmr/fpga.h | 15 -- board/matrix_vision/mvsmr/mvsmr.c | 248 -------------------------- board/matrix_vision/mvsmr/mvsmr.h | 43 ----- board/matrix_vision/mvsmr/u-boot.lds | 89 ---------- 20 files changed, 1263 deletions(-) delete mode 100644 board/matrix_vision/mvbc_p/Kconfig delete mode 100644 board/matrix_vision/mvbc_p/MAINTAINERS delete mode 100644 board/matrix_vision/mvbc_p/Makefile delete mode 100644 board/matrix_vision/mvbc_p/README.mvbc_p delete mode 100644 board/matrix_vision/mvbc_p/fpga.c delete mode 100644 board/matrix_vision/mvbc_p/fpga.h delete mode 100644 board/matrix_vision/mvbc_p/mvbc_p.c delete mode 100644 board/matrix_vision/mvbc_p/mvbc_p.h delete mode 100644 board/matrix_vision/mvbc_p/mvbc_p_autoscript delete mode 100644 board/matrix_vision/mvsmr/.gitignore delete mode 100644 board/matrix_vision/mvsmr/Kconfig delete mode 100644 board/matrix_vision/mvsmr/MAINTAINERS delete mode 100644 board/matrix_vision/mvsmr/Makefile delete mode 100644 board/matrix_vision/mvsmr/README.mvsmr delete mode 100644 board/matrix_vision/mvsmr/bootscript delete mode 100644 board/matrix_vision/mvsmr/fpga.c delete mode 100644 board/matrix_vision/mvsmr/fpga.h delete mode 100644 board/matrix_vision/mvsmr/mvsmr.c delete mode 100644 board/matrix_vision/mvsmr/mvsmr.h delete mode 100644 board/matrix_vision/mvsmr/u-boot.lds (limited to 'board') diff --git a/board/matrix_vision/mvbc_p/Kconfig b/board/matrix_vision/mvbc_p/Kconfig deleted file mode 100644 index 4a68493fa3..0000000000 --- a/board/matrix_vision/mvbc_p/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MVBC_P - -config SYS_BOARD - default "mvbc_p" - -config SYS_VENDOR - default "matrix_vision" - -config SYS_CONFIG_NAME - default "MVBC_P" - -endif diff --git a/board/matrix_vision/mvbc_p/MAINTAINERS b/board/matrix_vision/mvbc_p/MAINTAINERS deleted file mode 100644 index aad14ed079..0000000000 --- a/board/matrix_vision/mvbc_p/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MVBC_P BOARD -#M: Andre Schwarz -S: Orphan (since 2014-03) -F: board/matrix_vision/mvbc_p/ -F: include/configs/MVBC_P.h -F: configs/MVBC_P_defconfig diff --git a/board/matrix_vision/mvbc_p/Makefile b/board/matrix_vision/mvbc_p/Makefile deleted file mode 100644 index 4c1994156f..0000000000 --- a/board/matrix_vision/mvbc_p/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2004-2008 -# Matrix-Vision GmbH, info@matrix-vision.de -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mvbc_p.o fpga.o diff --git a/board/matrix_vision/mvbc_p/README.mvbc_p b/board/matrix_vision/mvbc_p/README.mvbc_p deleted file mode 100644 index a691137550..0000000000 --- a/board/matrix_vision/mvbc_p/README.mvbc_p +++ /dev/null @@ -1,73 +0,0 @@ -Matrix Vision mvBlueCOUGAR-P (mvBC-P) -------------------------------------- - -1. Board Description - - The mvBC-P is a 70x40x40mm multi board gigabit ethernet network camera - with main focus on GigEVision protocol in combination with local image - preprocessing. - - Power Supply is either VDC 48V or Pover over Ethernet (PoE). - -2 System Components - -2.1 CPU - Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB. - 64MB SDRAM @ 133MHz. - 8 MByte Nor Flash on local bus. - 1 serial ports. Console running on ttyS0 @ 115200 8N1. - -2.2 PCI - PCI clock fixed at 66MHz. Arbitration inside FPGA. - Intel GD82541ER network MAC/PHY and FPGA connected. - -2.3 FPGA - Altera Cyclone-II EP2C8 with PCI DMA engine. - Connects to Matrix Vision specific CCD/CMOS sensor interface. - Utilizes 64MB Nand Flash. - -2.3.1 I/O @ FPGA - 2 Outputs : photo coupler - 2 Inputs : photo coupler - -2.4 I2C - LM75 @ 0x90 for temperature monitoring. - EEPROM @ 0xA0 for vendor specifics. - image sensor interface (slave addresses depend on sensor) - -3 Flash layout. - - reset vector is 0x00000100, i.e. "LOWBOOT". - - FF800000 u-boot - FF840000 u-boot script image - FF850000 redundant u-boot script image - FF860000 FPGA raw bit file - FF8A0000 tbd. - FF900000 root FS - FFC00000 kernel - FFFC0000 device tree blob - FFFD0000 redundant device tree blob - FFFE0000 environment - FFFF0000 redundant environment - - mtd partitions are propagated to linux kernel via device tree blob. - -4 Booting - - On startup the bootscript @ FF840000 is executed. This script can be - exchanged easily. Default boot mode is "boot from flash", i.e. system - works stand-alone. - - This behaviour depends on some environment variables : - - "netboot" : yes ->try dhcp/bootp and boot from network. - A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for - DHCP server configuration, e.g. to provide different images to - different devices. - - During netboot the system tries to get 3 image files: - 1. Kernel - name + data is given during BOOTP. - 2. Initrd - name is stored in "initrd_name" - 3. device tree blob - name is stored in "dtb_name" - Fallback files are the flash versions. diff --git a/board/matrix_vision/mvbc_p/fpga.c b/board/matrix_vision/mvbc_p/fpga.c deleted file mode 100644 index b88f43f3e3..0000000000 --- a/board/matrix_vision/mvbc_p/fpga.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * (C) Copyright 2008 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "fpga.h" -#include "mvbc_p.h" - -#ifdef FPGA_DEBUG -#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args) -#else -#define fpga_debug(fmt, args...) -#endif - -Altera_CYC2_Passive_Serial_fns altera_fns = { - fpga_null_fn, - fpga_config_fn, - fpga_status_fn, - fpga_done_fn, - fpga_wr_fn, - fpga_null_fn, - fpga_null_fn, -}; - -Altera_desc cyclone2 = { - Altera_CYC2, - passive_serial, - Altera_EP2C8_SIZE, - (void *) &altera_fns, - NULL, -}; - -DECLARE_GLOBAL_DATA_PTR; - -int mvbc_p_init_fpga(void) -{ - fpga_debug("Initialize FPGA interface\n"); - fpga_init(); - fpga_add(fpga_altera, &cyclone2); - fpga_config_fn(0, 1, 0); - udelay(60); - - return 1; -} - -int fpga_null_fn(int cookie) -{ - return 0; -} - -int fpga_config_fn(int assert, int flush, int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - u32 dvo = gpio->simple_dvo; - - fpga_debug("SET config : %s\n", assert ? "low" : "high"); - if (assert) - dvo |= FPGA_CONFIG; - else - dvo &= ~FPGA_CONFIG; - - if (flush) - gpio->simple_dvo = dvo; - - return assert; -} - -int fpga_done_fn(int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - int result = 0; - - udelay(10); - fpga_debug("CONF_DONE check ... "); - if (gpio->simple_ival & FPGA_CONF_DONE) { - fpga_debug("high\n"); - result = 1; - } else - fpga_debug("low\n"); - - return result; -} - -int fpga_status_fn(int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - int result = 0; - - fpga_debug("STATUS check ... "); - if (gpio->sint_ival & FPGA_STATUS) { - fpga_debug("high\n"); - result = 1; - } else - fpga_debug("low\n"); - - return result; -} - -int fpga_clk_fn(int assert_clk, int flush, int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - u32 dvo = gpio->simple_dvo; - - fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low"); - if (assert_clk) - dvo |= FPGA_CCLK; - else - dvo &= ~FPGA_CCLK; - - if (flush) - gpio->simple_dvo = dvo; - - return assert_clk; -} - -static inline int _write_fpga(u8 val) -{ - int i; - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - u32 dvo = gpio->simple_dvo; - - for (i=0; i<8; i++) { - dvo &= ~FPGA_CCLK; - gpio->simple_dvo = dvo; - dvo &= ~FPGA_DIN; - if (val & 1) - dvo |= FPGA_DIN; - gpio->simple_dvo = dvo; - dvo |= FPGA_CCLK; - gpio->simple_dvo = dvo; - val >>= 1; - } - - return 0; -} - -int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) -{ - unsigned char *data = (unsigned char *) buf; - int i; - - fpga_debug("fpga_wr: buf %p / size %d\n", buf, len); - for (i = 0; i < len; i++) - _write_fpga(data[i]); - fpga_debug("\n"); - - return FPGA_SUCCESS; -} diff --git a/board/matrix_vision/mvbc_p/fpga.h b/board/matrix_vision/mvbc_p/fpga.h deleted file mode 100644 index 96d34654c9..0000000000 --- a/board/matrix_vision/mvbc_p/fpga.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -extern int mvbc_p_init_fpga(void); - -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int fpga_status_fn(int cookie); -extern int fpga_config_fn(int assert, int flush, int cookie); -extern int fpga_done_fn(int cookie); -extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie); -extern int fpga_null_fn(int cookie); diff --git a/board/matrix_vision/mvbc_p/mvbc_p.c b/board/matrix_vision/mvbc_p/mvbc_p.c deleted file mode 100644 index 8faebeeebe..0000000000 --- a/board/matrix_vision/mvbc_p/mvbc_p.c +++ /dev/null @@ -1,255 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2005-2007 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "fpga.h" -#include "mvbc_p.h" -#include "../common/mv_common.h" - -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 - -DECLARE_GLOBAL_DATA_PTR; - -static void sdram_start (int hi_addr) -{ - long hi_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 | hi_bit); - - /* precharge all banks */ - out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit); - - /* precharge all banks */ - out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit); - - /* auto refresh */ - out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 | hi_bit); - - /* set mode register */ - out_be32((u32*)MPC5XXX_SDRAM_MODE, SDRAM_MODE); - - /* normal operation */ - out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit); -} - -phys_addr_t initdram (int board_type) -{ - ulong dramsize = 0; - ulong test1, - test2; - - /* setup SDRAM chip selects */ - out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); - - /* setup config registers */ - out_be32((u32*)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1); - out_be32((u32*)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2); - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else - dramsize = test2; - - if (dramsize < (1 << 20)) - dramsize = 0; - - if (dramsize > 0) - out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x13 + - __builtin_ffs(dramsize >> 20) - 1); - else - out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0); - - return dramsize; -} - -void mvbc_init_gpio(void) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - - printf("Ports : 0x%08x\n", gpio->port_config); - printf("PORCFG: 0x%08lx\n", *(vu_long*)MPC5XXX_CDM_PORCFG); - - out_be32(&gpio->simple_ddr, SIMPLE_DDR); - out_be32(&gpio->simple_dvo, SIMPLE_DVO); - out_be32(&gpio->simple_ode, SIMPLE_ODE); - out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN); - - out_8(&gpio->sint_ode, SINT_ODE); - out_8(&gpio->sint_ddr, SINT_DDR); - out_8(&gpio->sint_dvo, SINT_DVO); - out_8(&gpio->sint_inten, SINT_INTEN); - out_be16(&gpio->sint_itype, SINT_ITYPE); - out_8(&gpio->sint_gpioe, SINT_GPIOEN); - - out_8((u8*)MPC5XXX_WU_GPIO_ODE, WKUP_ODE); - out_8((u8*)MPC5XXX_WU_GPIO_DIR, WKUP_DIR); - out_8((u8*)MPC5XXX_WU_GPIO_DATA_O, WKUP_DO); - out_8((u8*)MPC5XXX_WU_GPIO_ENABLE, WKUP_EN); - - printf("simple_gpioe: 0x%08x\n", gpio->simple_gpioe); - printf("sint_gpioe : 0x%08x\n", gpio->sint_gpioe); -} - -int misc_init_r(void) -{ - char *s = getenv("reset_env"); - - if (!s) { - if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6) - return 0; - udelay(50000); - if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6) - return 0; - udelay(50000); - if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6) - return 0; - } - printf(" === FACTORY RESET ===\n"); - mv_reset_environment(); - saveenv(); - - return -1; -} - -int checkboard(void) -{ - mvbc_init_gpio(); - printf("Board: Matrix Vision mvBlueCOUGAR-P\n"); - - return 0; -} - -void flash_preinit(void) -{ - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - clrbits_be32((u32*)MPC5XXX_BOOTCS_CFG, 0x1); -} - -void flash_afterinit(ulong size) -{ - out_be32((u32*)MPC5XXX_BOOTCS_START, START_REG(CONFIG_SYS_BOOTCS_START | - size)); - out_be32((u32*)MPC5XXX_CS0_START, START_REG(CONFIG_SYS_BOOTCS_START | - size)); - out_be32((u32*)MPC5XXX_BOOTCS_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size, - size)); - out_be32((u32*)MPC5XXX_CS0_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size, - size)); -} - -void pci_mvbc_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char line = 0xff; - char *s = getenv("pci_latency"); - u32 base; - u8 val = 0; - - if (s) - val = simple_strtoul(s, NULL, 16); - - if (PCI_BUS(dev) == 0) { - switch (PCI_DEV (dev)) { - case 0xa: /* FPGA */ - line = 3; - pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &base); - printf("found FPGA - enable arbitration\n"); - writel(0x03, (u32*)(base + 0x80c0)); - writel(0xf0, (u32*)(base + 0x8080)); - if (val) - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val); - break; - case 0xb: /* LAN */ - line = 2; - if (val) - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val); - break; - case 0x1a: - break; - default: - printf ("***pci_scan: illegal dev = 0x%08x\n", PCI_DEV (dev)); - break; - } - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line); - } -} - -struct pci_controller hose = { - fixup_irq:pci_mvbc_fixup_irq -}; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - mvbc_p_init_fpga(); - mv_load_fpga(); - pci_mpc5xxx_init(&hose); -} - -void show_boot_progress(int val) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - - switch(val) { - case BOOTSTAGE_ID_START: /* FPGA ok */ - setbits_be32(&gpio->simple_dvo, LED_G0); - break; - case BOOTSTAGE_ID_NET_ETH_INIT: - setbits_be32(&gpio->simple_dvo, LED_G1); - break; - case BOOTSTAGE_ID_COPY_RAMDISK: - setbits_be32(&gpio->simple_dvo, LED_Y); - break; - case BOOTSTAGE_ID_RUN_OS: - setbits_be32(&gpio->simple_dvo, LED_R); - break; - default: - break; - } - -} - -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -} - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); /* Built in FEC comes first */ - return pci_eth_init(bis); -} diff --git a/board/matrix_vision/mvbc_p/mvbc_p.h b/board/matrix_vision/mvbc_p/mvbc_p.h deleted file mode 100644 index be1542b773..0000000000 --- a/board/matrix_vision/mvbc_p/mvbc_p.h +++ /dev/null @@ -1,43 +0,0 @@ -#ifndef __MVBC_H__ -#define __MVBC_H__ - -#define LED_G0 MPC5XXX_GPIO_SIMPLE_PSC2_0 -#define LED_G1 MPC5XXX_GPIO_SIMPLE_PSC2_1 -#define LED_Y MPC5XXX_GPIO_SIMPLE_PSC2_2 -#define LED_R MPC5XXX_GPIO_SIMPLE_PSC2_3 -#define ARB_X_EN MPC5XXX_GPIO_WKUP_PSC2_4 - -#define FPGA_DIN MPC5XXX_GPIO_SIMPLE_PSC3_0 -#define FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_1 -#define FPGA_CONF_DONE MPC5XXX_GPIO_SIMPLE_PSC3_2 -#define FPGA_CONFIG MPC5XXX_GPIO_SIMPLE_PSC3_3 -#define FPGA_STATUS MPC5XXX_GPIO_SINT_PSC3_4 - -#define MAN_RST MPC5XXX_GPIO_WKUP_PSC6_0 -#define WD_TS MPC5XXX_GPIO_WKUP_PSC6_1 -#define WD_WDI MPC5XXX_GPIO_SIMPLE_PSC6_2 -#define COP_PRESENT MPC5XXX_GPIO_SIMPLE_PSC6_3 -#define FACT_RST MPC5XXX_GPIO_WKUP_6 -#define FLASH_RBY MPC5XXX_GPIO_WKUP_7 - -#define SIMPLE_DDR (LED_G0 | LED_G1 | LED_Y | LED_R | \ - FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI) -#define SIMPLE_DVO (FPGA_CONFIG) -#define SIMPLE_ODE (FPGA_CONFIG | LED_G0 | LED_G1 | LED_Y | LED_R) -#define SIMPLE_GPIOEN (LED_G0 | LED_G1 | LED_Y | LED_R | \ - FPGA_DIN | FPGA_CCLK | FPGA_CONF_DONE | FPGA_CONFIG |\ - WD_WDI | COP_PRESENT) - -#define SINT_ODE 0 -#define SINT_DDR 0 -#define SINT_DVO 0 -#define SINT_INTEN 0 -#define SINT_ITYPE 0 -#define SINT_GPIOEN (FPGA_STATUS) - -#define WKUP_ODE (MAN_RST) -#define WKUP_DIR (ARB_X_EN|MAN_RST|WD_TS) -#define WKUP_DO (ARB_X_EN|MAN_RST|WD_TS) -#define WKUP_EN (ARB_X_EN|MAN_RST|WD_TS|FACT_RST|FLASH_RBY) - -#endif diff --git a/board/matrix_vision/mvbc_p/mvbc_p_autoscript b/board/matrix_vision/mvbc_p/mvbc_p_autoscript deleted file mode 100644 index 9b21f30ece..0000000000 --- a/board/matrix_vision/mvbc_p/mvbc_p_autoscript +++ /dev/null @@ -1,48 +0,0 @@ -echo -echo "==== running autoscript ====" -echo -setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram} -setenv ramkernel setenv kernel_boot \${loadaddr} -setenv flashkernel setenv kernel_boot \${mv_kernel_addr} -setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length} -setenv bootfromflash run flashkernel cpird ramparam addcons e1000para addprofile bootdtb -setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name} -setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000 -setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup -setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel -if test ${console} = yes; -then -setenv addcons setenv bootargs \${bootargs} console=ttyPSC\${console_nr},\${baudrate}N8 -else -setenv addcons setenv bootargs \${bootargs} console=tty0 -fi -setenv e1000para setenv bootargs \${bootargs} e1000.TxDescriptors=256 e1000.SmartPowerDownEnable=1 -setenv set_static_ip setenv ipaddr \${static_ipaddr} -setenv set_static_nm setenv netmask \${static_netmask} -setenv set_static_gw setenv gatewayip \${static_gateway} -setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask} -setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs -if test ${oprofile} = yes; -then -setenv addprofile setenv bootargs \${bootargs} profile=\${profile} -fi -if test ${autoscript_boot} != no; -then - if test ${netboot} = yes; - then - bootp - if test $? = 0; - then - echo "=== bootp succeeded -> netboot ===" - run set_ip - run getdtb rundtb bootfromnet ramparam addcons e1000para addprofile bootdtb - else - echo "=== netboot failed ===" - fi - fi - run set_static_ip set_static_nm set_static_gw set_ip - echo "=== bootfromflash ===" - run cpdtb rundtb bootfromflash -else - echo "=== boot stopped with autoscript_boot no ===" -fi diff --git a/board/matrix_vision/mvsmr/.gitignore b/board/matrix_vision/mvsmr/.gitignore deleted file mode 100644 index 469f1bc4c1..0000000000 --- a/board/matrix_vision/mvsmr/.gitignore +++ /dev/null @@ -1 +0,0 @@ -bootscript.img diff --git a/board/matrix_vision/mvsmr/Kconfig b/board/matrix_vision/mvsmr/Kconfig deleted file mode 100644 index d725c5ac49..0000000000 --- a/board/matrix_vision/mvsmr/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MVSMR - -config SYS_BOARD - default "mvsmr" - -config SYS_VENDOR - default "matrix_vision" - -config SYS_CONFIG_NAME - default "MVSMR" - -endif diff --git a/board/matrix_vision/mvsmr/MAINTAINERS b/board/matrix_vision/mvsmr/MAINTAINERS deleted file mode 100644 index ae3cf9c0b2..0000000000 --- a/board/matrix_vision/mvsmr/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MVSMR BOARD -#M: Andre Schwarz -S: Orphan (since 2014-03) -F: board/matrix_vision/mvsmr/ -F: include/configs/MVSMR.h -F: configs/MVSMR_defconfig diff --git a/board/matrix_vision/mvsmr/Makefile b/board/matrix_vision/mvsmr/Makefile deleted file mode 100644 index cef1b7664c..0000000000 --- a/board/matrix_vision/mvsmr/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2004-2008 -# Matrix-Vision GmbH, info@matrix-vision.de -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mvsmr.o fpga.o - -extra-y := bootscript.img - -MKIMAGEFLAGS_bootscript.image := -T script -C none -n mvSMR_Script - -$(obj)/bootscript.img: $(src)/bootscript - $(call cmd,mkimage) diff --git a/board/matrix_vision/mvsmr/README.mvsmr b/board/matrix_vision/mvsmr/README.mvsmr deleted file mode 100644 index 8e34cb7838..0000000000 --- a/board/matrix_vision/mvsmr/README.mvsmr +++ /dev/null @@ -1,55 +0,0 @@ -Matrix Vision mvSMR -------------------- - -1. Board Description - - The mvSMR is a 75x130mm single image processing board used - in automation. Power Supply is 24VDC. - -2 System Components - -2.1 CPU - Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB. - 64MB DDR-I @ 133MHz. - 8 MByte Nor Flash on local bus. - 2 serial ports. Console running on ttyS0 @ 115200 8N1. - -2.2 PCI - PCI clock fixed at 33MHz due to old'n'slow Xilinx PCI core. - -2.3 FPGA - Xilinx Spartan-3 XC3S200 with PCI DMA engine. - Connects to Matrix Vision specific CCD/CMOS sensor interface. - -2.4 I2C - EEPROM @ 0xA0 for vendor specifics. - image sensor interface (slave addresses depend on sensor) - -3 Flash layout. - - reset vector is 0x00000100, i.e. "LOWBOOT". - - FF800000 u-boot - FF806000 u-boot script image - FF808000 u-boot environment - FF840000 FPGA raw bit file - FF880000 root FS - FFF00000 kernel - -4 Booting - - On startup the bootscript @ FF806000 is executed. This script can be - exchanged easily. Default boot mode is "boot from flash", i.e. system - works stand-alone. - - This behaviour depends on some environment variables : - - "netboot" : yes ->try dhcp/bootp and boot from network. - A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for - DHCP server configuration, e.g. to provide different images to - different devices. - - During netboot the system tries to get 3 image files: - 1. Kernel - name + data is given during BOOTP. - 2. Initrd - name is stored in "initrd_name" - Fallback files are the flash versions. diff --git a/board/matrix_vision/mvsmr/bootscript b/board/matrix_vision/mvsmr/bootscript deleted file mode 100644 index 02c802c8c7..0000000000 --- a/board/matrix_vision/mvsmr/bootscript +++ /dev/null @@ -1,42 +0,0 @@ -echo -echo "==== running autoscript ====" -echo -setenv boot24 'bootm ${kernel_boot} ${mv_initrd_addr_ram}' -setenv ramkernel 'setenv kernel_boot ${loadaddr}' -setenv flashkernel 'setenv kernel_boot ${mv_kernel_addr}' -setenv cpird 'cp ${mv_initrd_addr} ${mv_initrd_addr_ram} ${mv_initrd_length}' -setenv bootfromflash run flashkernel cpird addcons boot24 -setenv bootfromnet 'tftp ${mv_initrd_addr_ram} ${initrd_name};run ramkernel' -if test ${console} = yes; -then -setenv addcons 'setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8' -else -setenv addcons 'setenv bootargs ${bootargs} console=tty0' -fi -setenv set_static_ip 'setenv ipaddr ${static_ipaddr}' -setenv set_static_nm 'setenv netmask ${static_netmask}' -setenv set_static_gw 'setenv gatewayip ${static_gateway}' -setenv set_ip 'setenv ip ${ipaddr}::${gatewayip}:${netmask}' -if test ${servicemode} != yes; -then - echo "=== forced flash mode ===" - run set_static_ip set_static_nm set_static_gw set_ip bootfromflash -fi -if test ${autoscript_boot} != no; -then - if test ${netboot} = yes; - then - bootp - if test $? = 0; - then - echo "=== bootp succeeded -> netboot ===" - run set_ip bootfromnet addcons boot24 - else - echo "=== netboot failed ===" - fi - fi - echo "=== bootfromflash ===" - run set_static_ip set_static_nm set_static_gw set_ip bootfromflash -else - echo "=== boot stopped with autoscript_boot no ===" -fi diff --git a/board/matrix_vision/mvsmr/fpga.c b/board/matrix_vision/mvsmr/fpga.c deleted file mode 100644 index 518992578c..0000000000 --- a/board/matrix_vision/mvsmr/fpga.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * (C) Copyright 2010 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include "fpga.h" -#include "mvsmr.h" - -xilinx_spartan3_slave_serial_fns fpga_fns = { - fpga_pre_config_fn, - fpga_pgm_fn, - fpga_clk_fn, - fpga_init_fn, - fpga_done_fn, - fpga_wr_fn, - 0 -}; - -xilinx_desc spartan3 = { - xilinx_spartan2, - slave_serial, - XILINX_XC3S200_SIZE, - (void *) &fpga_fns, - 0, -}; - -DECLARE_GLOBAL_DATA_PTR; - -int mvsmr_init_fpga(void) -{ - fpga_init(); - fpga_add(fpga_xilinx, &spartan3); - - return 1; -} - -int fpga_init_fn(int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - - if (in_be32(&gpio->simple_ival) & FPGA_CONFIG) - return 0; - - return 1; -} - -int fpga_done_fn(int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - int result = 0; - - udelay(10); - if (in_be32(&gpio->simple_ival) & FPGA_DONE) - result = 1; - - return result; -} - -int fpga_pgm_fn(int assert, int flush, int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - - if (!assert) - setbits_8(&gpio->sint_dvo, FPGA_STATUS); - else - clrbits_8(&gpio->sint_dvo, FPGA_STATUS); - - return assert; -} - -int fpga_clk_fn(int assert_clk, int flush, int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - - if (assert_clk) - setbits_be32(&gpio->simple_dvo, FPGA_CCLK); - else - clrbits_be32(&gpio->simple_dvo, FPGA_CCLK); - - return assert_clk; -} - -int fpga_wr_fn(int assert_write, int flush, int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - - if (assert_write) - setbits_be32(&gpio->simple_dvo, FPGA_DIN); - else - clrbits_be32(&gpio->simple_dvo, FPGA_DIN); - - return assert_write; -} - -int fpga_pre_config_fn(int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - - setbits_8(&gpio->sint_dvo, FPGA_STATUS); - - return 0; -} diff --git a/board/matrix_vision/mvsmr/fpga.h b/board/matrix_vision/mvsmr/fpga.h deleted file mode 100644 index 7ef878bd44..0000000000 --- a/board/matrix_vision/mvsmr/fpga.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * (C) Copyright 2008 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -extern int mvsmr_init_fpga(void); - -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int fpga_init_fn(int cookie); -extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_wr_fn(int assert_write, int flush, int cookie); -extern int fpga_done_fn(int cookie); -extern int fpga_pre_config_fn(int cookie); diff --git a/board/matrix_vision/mvsmr/mvsmr.c b/board/matrix_vision/mvsmr/mvsmr.c deleted file mode 100644 index 2c513897f8..0000000000 --- a/board/matrix_vision/mvsmr/mvsmr.c +++ /dev/null @@ -1,248 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2005-2010 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "fpga.h" -#include "mvsmr.h" -#include "../common/mv_common.h" - -#define SDRAM_DDR 1 -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x715f0f00 -#define SDRAM_CONFIG1 0xd3722930 -#define SDRAM_CONFIG2 0x46770000 - -DECLARE_GLOBAL_DATA_PTR; - -static void sdram_start(int hi_addr) -{ - long hi_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 | - hi_bit); - - /* precharge all banks */ - out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | - hi_bit); - - /* set mode register: extended mode */ - out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE); - - /* set mode register: reset DLL */ - out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000); - - /* precharge all banks */ - out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | - hi_bit); - - /* auto refresh */ - out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 | - hi_bit); - - /* set mode register */ - out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE); - - /* normal operation */ - out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit); -} - -phys_addr_t initdram(int board_type) -{ - ulong dramsize = 0; - ulong test1, - test2; - - /* setup SDRAM chip selects */ - out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); - - /* setup config registers */ - out_be32((u32 *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1); - out_be32((u32 *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2); - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else - dramsize = test2; - - if (dramsize < (1 << 20)) - dramsize = 0; - - if (dramsize > 0) - out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x13 + - __builtin_ffs(dramsize >> 20) - 1); - else - out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0); - - return dramsize; -} - -void mvsmr_init_gpio(void) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - struct mpc5xxx_wu_gpio *wu_gpio = - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; - struct mpc5xxx_gpt_0_7 *timers = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; - - printf("Ports : 0x%08x\n", gpio->port_config); - printf("PORCFG: 0x%08x\n", in_be32((unsigned *)MPC5XXX_CDM_PORCFG)); - - out_be32(&gpio->simple_ddr, SIMPLE_DDR); - out_be32(&gpio->simple_dvo, SIMPLE_DVO); - out_be32(&gpio->simple_ode, SIMPLE_ODE); - out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN); - - out_8(&gpio->sint_ode, SINT_ODE); - out_8(&gpio->sint_ddr, SINT_DDR); - out_8(&gpio->sint_dvo, SINT_DVO); - out_8(&gpio->sint_inten, SINT_INTEN); - out_be16(&gpio->sint_itype, SINT_ITYPE); - out_8(&gpio->sint_gpioe, SINT_GPIOEN); - - out_8(&wu_gpio->ode, WKUP_ODE); - out_8(&wu_gpio->ddr, WKUP_DIR); - out_8(&wu_gpio->dvo, WKUP_DO); - out_8(&wu_gpio->enable, WKUP_EN); - - out_be32(&timers->gpt0.emsr, 0x00000234); /* OD output high */ - out_be32(&timers->gpt1.emsr, 0x00000234); - out_be32(&timers->gpt2.emsr, 0x00000234); - out_be32(&timers->gpt3.emsr, 0x00000234); - out_be32(&timers->gpt4.emsr, 0x00000234); - out_be32(&timers->gpt5.emsr, 0x00000234); - out_be32(&timers->gpt6.emsr, 0x00000024); /* push-pull output low */ - out_be32(&timers->gpt7.emsr, 0x00000024); -} - -int misc_init_r(void) -{ - char *s = getenv("reset_env"); - - if (s) { - printf(" === FACTORY RESET ===\n"); - mv_reset_environment(); - saveenv(); - } - - return -1; -} - -void mvsmr_get_dbg_present(void) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)MPC5XXX_PSC1; - - if (in_be32(&gpio->simple_ival) & COP_PRESENT) { - setenv("dbg_present", "no\0"); - setenv("bootstopkey", "abcdefghijklmnopqrstuvwxyz\0"); - } else { - setenv("dbg_present", "yes\0"); - setenv("bootstopkey", "s\0"); - setbits_8(&psc->command, PSC_RX_ENABLE); - } -} - -void mvsmr_get_service_mode(void) -{ - struct mpc5xxx_wu_gpio *wu_gpio = - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; - - if (in_8(&wu_gpio->ival) & SERVICE_MODE) - setenv("servicemode", "no\0"); - else - setenv("servicemode", "yes\0"); -} - -int mvsmr_get_mac(void) -{ - unsigned char mac[6]; - struct mpc5xxx_wu_gpio *wu_gpio = - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; - - if (in_8(&wu_gpio->ival) & LAN_PRSNT) { - setenv("lan_present", "no\0"); - return -1; - } else - setenv("lan_present", "yes\0"); - - i2c_read(0x50, 0, 1, mac, 6); - - eth_setenv_enetaddr("ethaddr", mac); - - return 0; -} - -int checkboard(void) -{ - mvsmr_init_gpio(); - printf("Board: Matrix Vision mvSMR\n"); - - return 0; -} - -void flash_preinit(void) -{ - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - clrbits_be32((u32 *)MPC5XXX_BOOTCS_CFG, 0x1); -} - -void flash_afterinit(ulong size) -{ - out_be32((u32 *)MPC5XXX_BOOTCS_START, - START_REG(CONFIG_SYS_BOOTCS_START | size)); - out_be32((u32 *)MPC5XXX_CS0_START, - START_REG(CONFIG_SYS_BOOTCS_START | size)); - out_be32((u32 *)MPC5XXX_BOOTCS_STOP, - STOP_REG(CONFIG_SYS_BOOTCS_START | size, size)); - out_be32((u32 *)MPC5XXX_CS0_STOP, - STOP_REG(CONFIG_SYS_BOOTCS_START | size, size)); -} - -struct pci_controller hose; - -void pci_init_board(void) -{ - mvsmr_get_dbg_present(); - mvsmr_get_service_mode(); - mvsmr_init_fpga(); - mv_load_fpga(); - pci_mpc5xxx_init(&hose); -} - -int board_eth_init(bd_t *bis) -{ - if (!mvsmr_get_mac()) - return cpu_eth_init(bis); - - return pci_eth_init(bis); -} diff --git a/board/matrix_vision/mvsmr/mvsmr.h b/board/matrix_vision/mvsmr/mvsmr.h deleted file mode 100644 index b8320f1e6e..0000000000 --- a/board/matrix_vision/mvsmr/mvsmr.h +++ /dev/null @@ -1,43 +0,0 @@ -#include - -extern void pci_mpc5xxx_init(struct pci_controller *); - -#define FPGA_DIN MPC5XXX_GPIO_SIMPLE_PSC3_0 -#define FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_1 -#define FPGA_DONE MPC5XXX_GPIO_SIMPLE_PSC3_2 -#define FPGA_CONFIG MPC5XXX_GPIO_SIMPLE_PSC3_3 -#define FPGA_STATUS MPC5XXX_GPIO_SINT_PSC3_4 -#define S_FPGA_DIN MPC5XXX_GPIO_SINT_PSC3_5 -#define S_FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_6 -#define S_FPGA_DONE MPC5XXX_GPIO_SIMPLE_PSC3_7 -#define S_FPGA_CONFIG MPC5XXX_GPIO_SINT_PSC3_8 -#define S_FPGA_STATUS MPC5XXX_GPIO_WKUP_PSC3_9 - -#define MAN_RST MPC5XXX_GPIO_WKUP_PSC6_0 -#define WD_TS MPC5XXX_GPIO_WKUP_PSC6_1 -#define WD_WDI MPC5XXX_GPIO_SIMPLE_PSC6_2 -#define COP_PRESENT MPC5XXX_GPIO_SIMPLE_PSC6_3 -#define SERVICE_MODE MPC5XXX_GPIO_WKUP_6 -#define FLASH_RBY MPC5XXX_GPIO_WKUP_7 -#define UART_EN1 MPC5XXX_GPIO_WKUP_PSC1_4 -#define LAN_PRSNT MPC5XXX_GPIO_WKUP_PSC2_4 - -#define SIMPLE_DDR (FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI |\ - S_FPGA_CCLK) -#define SIMPLE_DVO (FPGA_CONFIG) -#define SIMPLE_ODE (FPGA_CONFIG) -#define SIMPLE_GPIOEN (FPGA_DIN | FPGA_CCLK | FPGA_DONE | FPGA_CONFIG |\ - S_FPGA_CCLK | S_FPGA_DONE | WD_WDI | COP_PRESENT) - -#define SINT_ODE 0x1 -#define SINT_DDR 0x3 -#define SINT_DVO 0x1 -#define SINT_INTEN 0 -#define SINT_ITYPE 0 -#define SINT_GPIOEN (FPGA_STATUS | S_FPGA_DIN | S_FPGA_CONFIG) - -#define WKUP_ODE (MAN_RST | S_FPGA_STATUS) -#define WKUP_DIR (MAN_RST | WD_TS | S_FPGA_STATUS) -#define WKUP_DO (MAN_RST | WD_TS | S_FPGA_STATUS) -#define WKUP_EN (MAN_RST | WD_TS | S_FPGA_STATUS | SERVICE_MODE |\ - FLASH_RBY | UART_EN1 | LAN_PRSNT) diff --git a/board/matrix_vision/mvsmr/u-boot.lds b/board/matrix_vision/mvsmr/u-boot.lds deleted file mode 100644 index e885b7c160..0000000000 --- a/board/matrix_vision/mvsmr/u-boot.lds +++ /dev/null @@ -1,89 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * (C) Copyright 2010 - * André Schwarz, Matrix Vision GmbH, as@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the first two sectors (=8KB) of our S29GL flash chip */ - arch/powerpc/cpu/mpc5xxx/start.o (.text*) - arch/powerpc/cpu/mpc5xxx/traps.o (.text*) - board/matrix_vision/common/built-in.o (.text*) - - /* This is only needed to force failure if size of above code will ever */ - /* increase and grow into reserved space. */ - . = ALIGN(0x2000); /* location counter has to be 0x4000 now */ - . += 0x4000; /* ->0x8000, i.e. move to env_offset */ - - . = env_offset; /* ld error as soon as above ALIGN misplaces lc */ - common/env_embedded.o (.ppcenv) - - *(.text*) - . = ALIGN(16); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} -- cgit v1.2.1 From 04e2a13336f0e507ef416bbede3be92b79c46594 Mon Sep 17 00:00:00 2001 From: Alexander Kochetkov Date: Mon, 29 Sep 2014 21:46:48 +0400 Subject: beagleboard: Remove side effects of i2c2 pullup resisters initialization code Fix typo of commit d4e53f063dd25e071444b87303573e7440deeb89. i2c2 pullup resisters are controlled by bit 0 of CONTROL_PROG_IO1. It's value after reset is 0x00100001. In order to clear bit 0, original code write 0xfffffffe to CONTROL_PROG_IO1 and toggle almost all default values. Original code affect following: * disable i2c1 pullup resisters * increase far end load setting for many modules * setup invalid SC/LB combination Signed-off-by: Alexander Kochetkov CC: Tom Rini CC: Steve Kipisz --- board/ti/beagle/beagle.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 0674afdc09..94b99bf537 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -317,9 +317,12 @@ int misc_init_r(void) struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE; struct control_prog_io *prog_io_base = (struct control_prog_io *)OMAP34XX_CTRL_BASE; bool generate_fake_mac = false; + u32 value; /* Enable i2c2 pullup resisters */ - writel(~(PRG_I2C2_PULLUPRESX), &prog_io_base->io1); + value = readl(&prog_io_base->io1); + value &= ~(PRG_I2C2_PULLUPRESX); + writel(value, &prog_io_base->io1); switch (get_board_revision()) { case REVISION_AXBX: -- cgit v1.2.1 From cf7d4505e3403a4ce039dc28c3a473414e7ea6a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?David=20M=C3=BCller=20=28ELSOFT=20AG=29?= Date: Tue, 30 Sep 2014 13:23:54 +0200 Subject: PATI: fix broken SPI access MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fix broken SPI access by adding/activating BOARD_EARLY_INIT_F functionality and calling spi_init_f() from there. Signed-off-by: David Müller --- board/mpl/pati/pati.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'board') diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c index 5d701a7931..b9d88ee17e 100644 --- a/board/mpl/pati/pati.c +++ b/board/mpl/pati/pati.c @@ -311,6 +311,11 @@ void user_led1(int led_on) sysconf->sc_sgpiodt2=reg; /* Data register */ } +int board_early_init_f(void) +{ + spi_init_f(); + return 0; +} /**************************************************************** * Last Stage Init -- cgit v1.2.1 From 207828e215f7e8331ea3c304b922de9d155fb68e Mon Sep 17 00:00:00 2001 From: Hannes Petermaier Date: Fri, 3 Oct 2014 07:30:15 +0200 Subject: board/BuR: fix pinmux for MII Ethernet Interface The lines COL (collision detect) and CRS (carrier sense) needs to be connected and muxed to the CPSW MAC for a proper function in half-duplex Mode of the interface. Signed-off-by: Hannes Petermaier Cc: Tom Rini --- board/BuR/kwb/mux.c | 2 ++ board/BuR/tseries/mux.c | 3 +++ 2 files changed, 5 insertions(+) (limited to 'board') diff --git a/board/BuR/kwb/mux.c b/board/BuR/kwb/mux.c index 1a5ffd5709..ecb2e7a427 100644 --- a/board/BuR/kwb/mux.c +++ b/board/BuR/kwb/mux.c @@ -105,6 +105,8 @@ static struct module_pin_mux i2c0_pin_mux[] = { }; static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */ + {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */ {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ diff --git a/board/BuR/tseries/mux.c b/board/BuR/tseries/mux.c index 210ac71738..0ba25ee318 100644 --- a/board/BuR/tseries/mux.c +++ b/board/BuR/tseries/mux.c @@ -64,6 +64,8 @@ static struct module_pin_mux spi0_pin_mux[] = { }; static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */ + {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */ {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ @@ -96,6 +98,7 @@ static struct module_pin_mux mii2_pin_mux[] = { {OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */ {OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */ {OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */ + {OFFSET(gpmc_wait0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* * MII2_CRS is shared with * NAND_WAIT0 -- cgit v1.2.1