From 086511fc96a8a9bb56e5e19a3d84c40f4dba80cc Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Thu, 17 Jul 2008 12:47:09 +0200 Subject: ppc4xx: ML507 Board Support The Xilinx ML507 Board is a Virtex 5 prototyping board that includes, among others: -Virtex 5 FX FPGA (With a ppc440x5 in it) -256MB of SDRAM2 -32MB of Flash -I2C Eeprom -System ACE chip -Serial ATA connectors -RS232 Level Conversors -Ethernet Transceiver This patch gives support to a standard design produced by EDK for this board: ppc440, uartlite, xilinx_int and flash - Includes Changes propossed by Stefan Roese and Michal Simek Signed-off-by: Ricardo Ribalda Delgado Acked-by: Stefan Roese --- board/xilinx/ml507/xparameters.h | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 board/xilinx/ml507/xparameters.h (limited to 'board/xilinx/ml507/xparameters.h') diff --git a/board/xilinx/ml507/xparameters.h b/board/xilinx/ml507/xparameters.h new file mode 100644 index 0000000000..1542e84580 --- /dev/null +++ b/board/xilinx/ml507/xparameters.h @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * based on xparameters-ml507.h by Xilinx + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . +*/ + +#ifndef XPARAMETER_H +#define XPARAMETER_H + +#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 +#define XPAR_INTC_0_BASEADDR 0x81800000 +#define XPAR_UARTLITE_0_BASEADDR 0x84000000 +#define XPAR_IIC_EEPROM_BASEADDR 0x81600000 +#define XPAR_LLTEMAC_0_BASEADDR 0x81c00000 +#define XPAR_FLASH_MEM0_BASEADDR 0xFC000000 +#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 +#define XPAR_CORE_CLOCK_FREQ_HZ 400000000 +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 + +#endif -- cgit v1.2.1