From 7b50e1599f4e6551a3348ca5f061a596f6f6896e Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 28 Jul 2015 14:16:44 +0530 Subject: ARM: keystone2: Fix dev and arm speed detection Use common devspeed and armspeed definitions. Also fix reading efuse bootrom register. Reviewed-by: Tom Rini Reviewed-by: Vitaly Andrianov Signed-off-by: Lokesh Vutla --- board/ti/ks2_evm/board_k2e.c | 32 ++++++++++++++++++++++++-------- 1 file changed, 24 insertions(+), 8 deletions(-) (limited to 'board/ti/ks2_evm/board_k2e.c') diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c index 98acc96e1c..2043759533 100644 --- a/board/ti/ks2_evm/board_k2e.c +++ b/board/ti/ks2_evm/board_k2e.c @@ -26,14 +26,30 @@ unsigned int external_clk[ext_clk_count] = { [usb_clk] = 100000000, }; -static struct pll_init_data core_pll_config[] = { - CORE_PLL_800, - CORE_PLL_850, - CORE_PLL_1000, - CORE_PLL_1250, - CORE_PLL_1350, - CORE_PLL_1400, - CORE_PLL_1500, +static struct pll_init_data core_pll_config[NUM_SPDS] = { + [SPD800] = CORE_PLL_800, + [SPD850] = CORE_PLL_850, + [SPD1000] = CORE_PLL_1000, + [SPD1250] = CORE_PLL_1250, + [SPD1350] = CORE_PLL_1350, + [SPD1400] = CORE_PLL_1400, + [SPD1500] = CORE_PLL_1500, +}; + +/* DEV and ARM speed definitions as specified in DEVSPEED register */ +int speeds[DEVSPEED_NUMSPDS] = { + SPD850, + SPD1000, + SPD1250, + SPD1350, + SPD1400, + SPD1500, + SPD1400, + SPD1350, + SPD1250, + SPD1000, + SPD850, + SPD800, }; s16 divn_val[16] = { -- cgit v1.2.1