From 76cff2b10857c86211ef60024e672ce178cb6d69 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 13 Aug 2015 09:51:00 -0500 Subject: ARM: DRA74-evm: Use SMA_1 spare register to workaround DP83865 phy on SR2.0 DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet provided IODELAY values for standard RGMII phys do not work. Silicon Revision(SR) 2.0 provides an alternative bit configuration that allows us to do a "gross adjustment" to launch the data off a different internal clock edge. Manual IO Delay overrides are still necessary to fine tune the clock-to-data delays. This is a necessary workaround for the quirky ethernet Phy we have on the platform. NOTE: SMA registers are spare "kitchen sink" registers that does contain bits for other workaround as necessary as well. Hence the control for the same is introduced in a generic SoC specific, board generic location. Signed-off-by: Nishanth Menon Reviewed-by: Tom Rini --- board/ti/dra7xx/evm.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'board/ti/dra7xx') diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 9603f10f8a..6e3c85513f 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -104,6 +104,9 @@ void recalibrate_iodelay(void) npads = ARRAY_SIZE(dra74x_core_padconf_array); iodelay = dra742_es2_0_iodelay_cfg_array; niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array); + /* Setup port1 and port2 for rgmii with 'no-id' mode */ + clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK | + RGMII1_ID_MODE_N_MASK); break; } __recalibrate_iodelay(pads, npads, iodelay, niodelays); -- cgit v1.2.1