From ad008299712bbcaf822ebac0f4ab88069e1a1372 Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Thu, 23 Jul 2015 14:33:01 +0200 Subject: sunxi: nand: Add pinmux and clock settings for NAND support To enable NAND flash in sunxi SPL, pins 0-6, 8-22 and 24 on port C are configured. Signed-off-by: Karol Gugala Signed-off-by: Piotr Zierhoffer Acked-by: Hans de Goede Signed-off-by: Hans de Goede --- board/sunxi/board.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'board/sunxi') diff --git a/board/sunxi/board.c b/board/sunxi/board.c index afed6a31ca..f85e825891 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -107,6 +107,28 @@ int dram_init(void) return 0; } +#if defined(CONFIG_SPL_NAND_SUNXI) && defined(CONFIG_SPL_BUILD) +static void nand_pinmux_setup(void) +{ + unsigned int pin; + for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(6); pin++) + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); + + for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(22); pin++) + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); + + sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND); +} + +static void nand_clock_setup(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); + setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); +} +#endif + #ifdef CONFIG_GENERIC_MMC static void mmc_pinmux_setup(int sdc) { @@ -431,6 +453,11 @@ void sunxi_board_init(void) power_failed |= axp221_set_eldo(3, CONFIG_AXP221_ELDO3_VOLT); #endif +#ifdef CONFIG_SPL_NAND_SUNXI + nand_pinmux_setup(); + nand_clock_setup(); +#endif + printf("DRAM:"); ramsize = sunxi_dram_init(); printf(" %lu MiB\n", ramsize >> 20); -- cgit v1.2.1