From a2cd50ed6ef0ac6b127b3d6db756979a8336718d Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Tue, 11 Nov 2008 10:17:10 -0600 Subject: 85xx: Add CPU 2 errata workaround to all 8548 boards All mpc8548-based boards should implement the suggested workaround to CPU 2 errata. Without the workaround, its possible for the 8548's core to hang while executing a msync or mbar 0 instruction and a snoopable transaction from an I/O master tagged to make quick forward progress is present. Signed-off-by: Peter Tyser Acked-by: Andy Fleming --- board/sbc8548/sbc8548.c | 7 ------- 1 file changed, 7 deletions(-) (limited to 'board/sbc8548') diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index cfb9ce5144..017f6b35cf 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -61,13 +61,6 @@ int checkboard (void) */ local_bus_init (); - /* - * Fix CPU2 errata: A core hang possible while executing a - * msync instruction and a snoopable transaction from an I/O - * master tagged to make quick forward progress is present. - */ - ecm->eebpcr |= (1 << 16); - /* * Hack TSEC 3 and 4 IO voltages. */ -- cgit v1.2.1