From 3c945542dad99b1ec4a324ad6b69b8de8829827b Mon Sep 17 00:00:00 2001 From: Xiangfu Liu Date: Wed, 12 Oct 2011 12:24:06 +0800 Subject: MIPS: Jz4740: Add qi_lb60 board support Add support for the qi_lb60 (a.k.a QI Ben NanoNote) clamshell device from Qi hardware: http://en.qi-hardware.com/wiki/Ben_NanoNote http://en.qi-hardware.com/wiki/Main_Page http://en.wikipedia.org/wiki/Qi_hardware This Jz4740-based clamshell device does not use NOR flash to boot. The initial bring-up assumes that U-Boot is directly loaded into SDRAM using USB boot tool, and starts from 0x80100000. About USB boot tool ------------------- Jz4740 is one of the XBurst processors with USB boot functionality supported. The CPU can boot from a small ROM in the LSI, initialize CPU and USB module, then wait for USB commands from the USB host. We can send 8 KB binary data to the CPU cache using USB boot tool. USB boot tool is available to the public at Ingenic website. Also there is an alternative Debian package named xburst-tools. Signed-off-by: Xiangfu Liu Acked-by: Daniel Signed-off-by: Shinya Kuribayashi --- board/qi/qi_lb60/qi_lb60.c | 104 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) create mode 100644 board/qi/qi_lb60/qi_lb60.c (limited to 'board/qi/qi_lb60/qi_lb60.c') diff --git a/board/qi/qi_lb60/qi_lb60.c b/board/qi/qi_lb60/qi_lb60.c new file mode 100644 index 0000000000..3583d01c76 --- /dev/null +++ b/board/qi/qi_lb60/qi_lb60.c @@ -0,0 +1,104 @@ +/* + * Authors: Xiangfu Liu + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 3 of the License, or (at your option) any later version. + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static void gpio_init(void) +{ + unsigned int i; + + /* Initialize NAND Flash Pins */ + __gpio_as_nand(); + + /* Initialize SDRAM pins */ + __gpio_as_sdram_16bit_4720(); + + /* Initialize LCD pins */ + __gpio_as_lcd_18bit(); + + /* Initialize MSC pins */ + __gpio_as_msc(); + + /* Initialize Other pins */ + for (i = 0; i < 7; i++) { + __gpio_as_input(GPIO_KEYIN_BASE + i); + __gpio_enable_pull(GPIO_KEYIN_BASE + i); + } + + for (i = 0; i < 8; i++) { + __gpio_as_output(GPIO_KEYOUT_BASE + i); + __gpio_clear_pin(GPIO_KEYOUT_BASE + i); + } + + __gpio_as_input(GPIO_KEYIN_8); + __gpio_enable_pull(GPIO_KEYIN_8); + + /* enable the TP4, TP5 as UART0 */ + __gpio_jtag_to_uart0(); + + __gpio_as_output(GPIO_AUDIO_POP); + __gpio_set_pin(GPIO_AUDIO_POP); + + __gpio_as_output(GPIO_LCD_CS); + __gpio_clear_pin(GPIO_LCD_CS); + + __gpio_as_output(GPIO_AMP_EN); + __gpio_clear_pin(GPIO_AMP_EN); + + __gpio_as_output(GPIO_SDPW_EN); + __gpio_disable_pull(GPIO_SDPW_EN); + __gpio_clear_pin(GPIO_SDPW_EN); + + __gpio_as_input(GPIO_SD_DETECT); + __gpio_disable_pull(GPIO_SD_DETECT); + + __gpio_as_input(GPIO_USB_DETECT); + __gpio_enable_pull(GPIO_USB_DETECT); +} + +static void cpm_init(void) +{ + struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE; + uint32_t reg = readw(&cpm->clkgr); + + reg |= CPM_CLKGR_IPU | + CPM_CLKGR_CIM | + CPM_CLKGR_I2C | + CPM_CLKGR_SSI | + CPM_CLKGR_UART1 | + CPM_CLKGR_SADC | + CPM_CLKGR_UHC | + CPM_CLKGR_UDC | + CPM_CLKGR_AIC1; + + writew(reg, &cpm->clkgr); +} + +int board_early_init_f(void) +{ + gpio_init(); + cpm_init(); + calc_clocks(); /* calc the clocks */ + rtc_init(); /* init rtc on any reset */ + + return 0; +} + +/* U-Boot common routines */ +int checkboard(void) +{ + printf("Board: Qi LB60 (Ingenic XBurst Jz4740 SoC, Speed %ld MHz)\n", + gd->cpu_clk / 1000000); + + return 0; +} -- cgit v1.2.1