From 79fa88f3ede051ca860667d5397e6cdc7e74a6d0 Mon Sep 17 00:00:00 2001
From: wdenk <wdenk>
Date: Mon, 7 Jun 2004 23:46:25 +0000
Subject: Patch by Pantelis Antoniou, 5 May 2004: - Intracom board update. -
 Add Codec POST.

---
 board/netta/netta.c | 29 ++++++++++++++++++++++++-----
 1 file changed, 24 insertions(+), 5 deletions(-)

(limited to 'board/netta/netta.c')

diff --git a/board/netta/netta.c b/board/netta/netta.c
index afb3fe1833..e7024e52d3 100644
--- a/board/netta/netta.c
+++ b/board/netta/netta.c
@@ -63,6 +63,11 @@ int checkboard(void)
 	printf ("Intracom NETTA"
 #if defined(CONFIG_NETTA_ISDN)
 			" with ISDN support"
+#endif
+#if defined(CONFIG_NETTA_6412)
+			" (DSP:TI6412)"
+#else
+			" (DSP:TI6711)"
 #endif
 			"\n"
 			);
@@ -462,10 +467,10 @@ int last_stage_init(void)
 #define PA_SP_DIRVAL	0
 
 #define PB_GP_INMASK	(_B(28) | _B(31))
-#define PB_GP_OUTMASK	(_BR(16, 19) | _BR(26, 27) | _BR(29, 30))
+#define PB_GP_OUTMASK	(_BR(15, 19) | _BR(26, 27) | _BR(29, 30))
 #define PB_SP_MASK	(_BR(22, 25))
 #define PB_ODR_VAL	0
-#define PB_GP_OUTVAL	(_BR(16, 19) | _BR(26, 27) | _BR(29, 31))
+#define PB_GP_OUTVAL	(_BR(15, 19) | _BR(26, 27) | _BR(29, 31))
 #define PB_SP_DIRVAL	0
 
 #define PC_GP_INMASK	(_BW(5) | _BW(7) | _BW(8) | _BWR(9, 11) | _BWR(13, 15))
@@ -479,7 +484,17 @@ int last_stage_init(void)
 #define PD_GP_INMASK	0
 #define PD_GP_OUTMASK	_BWR(3, 15)
 #define PD_SP_MASK	0
+
+#if defined(CONFIG_NETTA_6412)
+
+#define PD_GP_OUTVAL	(_BWR(5, 7) | _BW(9) | _BW(11) | _BW(15))
+
+#else
+
 #define PD_GP_OUTVAL	(_BWR(5, 7) | _BW(9) | _BW(11))
+
+#endif
+
 #define PD_SP_DIRVAL	0
 
 int board_early_init_f(void)
@@ -492,11 +507,15 @@ int board_early_init_f(void)
 	/* CS1: NAND chip select */
 	memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_SCY_2_CLK | OR_TRLX | OR_ACS_DIV2) ;
 	memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
-
+#if !defined(CONFIG_NETTA_6412)
 	/* CS2: DSP */
 	memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2);
 	memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
-
+#else
+	/* CS6: DSP */
+	memctl->memc_or6 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2);
+	memctl->memc_br6 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
+#endif
 	/* CS4: External register chip select */
 	memctl->memc_or4 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK);
 	memctl->memc_br4 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
@@ -525,7 +544,7 @@ int board_early_init_f(void)
 	ioport->iop_pddir	= PD_GP_OUTMASK | PD_SP_DIRVAL;
 	ioport->iop_pdpar	= PD_SP_MASK;
 
-	ioport->iop_pddat |=  (1 << (15 - 6)) | (1 << (15 - 7));
+	/* ioport->iop_pddat |=  (1 << (15 - 6)) | (1 << (15 - 7)); */
 
 	return 0;
 }
-- 
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