From 5527024fdb10798d2975197f287457b29e2d4084 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Wed, 8 Aug 2012 03:55:32 +0000 Subject: KARO TX25: Fix NAND Flash R/W cycle times MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The NAND Flash of the KARO TX25 board is a Samsung K9F1G08U0B with 25-ns R/W cycle times. However, the NFC clock for this board was set to 66.5 MHz, so using the NFC driver in symmetric mode (i.e. 1 NFC clock cycle = 1 NF R/W cycle) resulted in NF R/W cycle times of 15 ns, hence corrupted NF accesses. This patch fixes this issue by setting the NFC clock to the highest frequency complying to the 25-ns NF R/W cycle times specification, i.e. 33.25 MHz. Signed-off-by: Benoît Thébaudeau Cc: John Rigby Cc: Scott Wood Cc: Stefano Babic Cc: Daniel Gachet Acked-by: Stefano Babic --- board/karo/tx25/lowlevel_init.S | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'board/karo/tx25') diff --git a/board/karo/tx25/lowlevel_init.S b/board/karo/tx25/lowlevel_init.S index 823df10701..eb3f187806 100644 --- a/board/karo/tx25/lowlevel_init.S +++ b/board/karo/tx25/lowlevel_init.S @@ -66,6 +66,14 @@ write32 0x53f80064, 0x45600000 write32 0x53f80008, 0x20034000 + /* + * PCDR2: NFC = 33.25 MHz + * This is required for the NAND Flash of this board, which is a Samsung + * K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with + * the NFC driver in symmetric (i.e. one-cycle) mode. + */ + write32 0x53f80020, 0x01010103 + /* * enable all implemented clocks in all three * clock control registers -- cgit v1.2.1