From 952e7760bfc5b0e3b142b9ce34e7fbb7d008c900 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 24 Sep 2009 09:55:50 +0200 Subject: ppc4xx: Convert PPC4xx UIC defines from lower case to upper case The latest PPC4xx register cleanup patch missed the UIC defines. This patch now changes lower case UIC defines to upper case. Signed-off-by: Stefan Roese --- board/gdsys/dlvision/dlvision.c | 14 ++++---- board/gdsys/gdppc440etx/gdppc440etx.c | 30 ++++++++--------- board/gdsys/intip/intip.c | 62 +++++++++++++++++------------------ board/gdsys/neo/neo.c | 14 ++++---- 4 files changed, 60 insertions(+), 60 deletions(-) (limited to 'board/gdsys') diff --git a/board/gdsys/dlvision/dlvision.c b/board/gdsys/dlvision/dlvision.c index 5246bc8c4f..ff5f183235 100644 --- a/board/gdsys/dlvision/dlvision.c +++ b/board/gdsys/dlvision/dlvision.c @@ -36,13 +36,13 @@ enum { int board_early_init_f(void) { - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest prio */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c index 27c159bec6..7cc1bf2678 100644 --- a/board/gdsys/gdppc440etx/gdppc440etx.c +++ b/board/gdsys/gdppc440etx/gdppc440etx.c @@ -83,21 +83,21 @@ int board_early_init_f(void) /* * Setup the interrupt controller polarities, triggers, etc. */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ - mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */ + mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ /* * Setup other serial configuration diff --git a/board/gdsys/intip/intip.c b/board/gdsys/intip/intip.c index 0de1be8579..2cd2e6d450 100644 --- a/board/gdsys/intip/intip.c +++ b/board/gdsys/intip/intip.c @@ -44,37 +44,37 @@ int board_early_init_f(void) /* * Setup the interrupt controller polarities, triggers, etc. */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - - mtdcr(uic2sr, 0xffffffff); /* clear all */ - mtdcr(uic2er, 0x00000000); /* disable all */ - mtdcr(uic2cr, 0x00000000); /* all non-critical */ - mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ - - mtdcr(uic3sr, 0xffffffff); /* clear all */ - mtdcr(uic3er, 0x00000000); /* disable all */ - mtdcr(uic3cr, 0x00000000); /* all non-critical */ - mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic3tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic3sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + + mtdcr(UIC3SR, 0xffffffff); /* clear all */ + mtdcr(UIC3ER, 0x00000000); /* disable all */ + mtdcr(UIC3CR, 0x00000000); /* all non-critical */ + mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC3SR, 0xffffffff); /* clear all */ /* * Configure PFC (Pin Function Control) registers diff --git a/board/gdsys/neo/neo.c b/board/gdsys/neo/neo.c index 628ce3dc90..a56c2cc987 100644 --- a/board/gdsys/neo/neo.c +++ b/board/gdsys/neo/neo.c @@ -31,13 +31,13 @@ int board_early_init_f(void) { - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest prio */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -- cgit v1.2.1