From ddd8a08052052561af38ecbe30930001a2ae940b Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Fri, 3 Jun 2016 18:41:30 +0530 Subject: armv8: fsl-layerscape: Organize SoC overview at common location SoC overviews are getting repeated across board folders. So, Organize SoC overview at common location i.e. fsl-layerscape/doc Also move README.lsch2 and README.lsch3 in same folder. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- board/freescale/ls1043aqds/README | 37 ++------------------------------ board/freescale/ls1043ardb/README | 37 ++------------------------------ board/freescale/ls2080aqds/README | 45 +++------------------------------------ board/freescale/ls2080ardb/README | 45 +++------------------------------------ 4 files changed, 10 insertions(+), 154 deletions(-) (limited to 'board/freescale') diff --git a/board/freescale/ls1043aqds/README b/board/freescale/ls1043aqds/README index a6fd7a35f5..913537d451 100644 --- a/board/freescale/ls1043aqds/README +++ b/board/freescale/ls1043aqds/README @@ -8,41 +8,8 @@ debugging environment. LS1043A SoC Overview -------------------- -The LS1043A integrated multicore processor combines four ARM Cortex-A53 -processor cores with datapath acceleration optimized for L2/3 packet -processing, single pass security offload and robust traffic management -and quality of service. - -The LS1043A SoC includes the following function and features: - - Four 64-bit ARM Cortex-A53 CPUs - - 1 MB unified L2 Cache - - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving - support - - Data Path Acceleration Architecture (DPAA) incorporating acceleration the - the following functions: - - Packet parsing, classification, and distribution (FMan) - - Queue management for scheduling, packet sequencing, and congestion - management (QMan) - - Hardware buffer management for buffer allocation and de-allocation (BMan) - - Cryptography acceleration (SEC) - - Ethernet interfaces by FMan - - Up to 1 x XFI supporting 10G interface - - Up to 1 x QSGMII - - Up to 4 x SGMII supporting 1000Mbps - - Up to 2 x SGMII supporting 2500Mbps - - Up to 2 x RGMII supporting 1000Mbps - - High-speed peripheral interfaces - - Three PCIe 2.0 controllers, one supporting x4 operation - - One serial ATA (SATA 3.0) controllers - - Additional peripheral interfaces - - Three high-speed USB 3.0 controllers with integrated PHY - - Enhanced secure digital host controller (eSDXC/eMMC) - - Quad Serial Peripheral Interface (QSPI) Controller - - Serial peripheral interface (SPI) controller - - Four I2C controllers - - Two DUARTs - - Integrated flash controller supporting NAND and NOR flash - - QorIQ platform's trust architecture 2.1 +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A +SoC overview. LS1043AQDS board Overview ----------------------- diff --git a/board/freescale/ls1043ardb/README b/board/freescale/ls1043ardb/README index 0556e73b3a..709ddbbef3 100644 --- a/board/freescale/ls1043ardb/README +++ b/board/freescale/ls1043ardb/README @@ -8,41 +8,8 @@ debugging environment. The LS1043A RDB is lead-free and RoHS-compliant. LS1043A SoC Overview -------------------- -The LS1043A integrated multicore processor combines four ARM Cortex-A53 -processor cores with datapath acceleration optimized for L2/3 packet -processing, single pass security offload and robust traffic management -and quality of service. - -The LS1043A SoC includes the following function and features: - - Four 64-bit ARM Cortex-A53 CPUs - - 1 MB unified L2 Cache - - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving - support - - Data Path Acceleration Architecture (DPAA) incorporating acceleration the - the following functions: - - Packet parsing, classification, and distribution (FMan) - - Queue management for scheduling, packet sequencing, and congestion - management (QMan) - - Hardware buffer management for buffer allocation and de-allocation (BMan) - - Cryptography acceleration (SEC) - - Ethernet interfaces by FMan - - Up to 1 x XFI supporting 10G interface - - Up to 1 x QSGMII - - Up to 4 x SGMII supporting 1000Mbps - - Up to 2 x SGMII supporting 2500Mbps - - Up to 2 x RGMII supporting 1000Mbps - - High-speed peripheral interfaces - - Three PCIe 2.0 controllers, one supporting x4 operation - - One serial ATA (SATA 3.0) controllers - - Additional peripheral interfaces - - Three high-speed USB 3.0 controllers with integrated PHY - - Enhanced secure digital host controller (eSDXC/eMMC) - - Quad Serial Peripheral Interface (QSPI) Controller - - Serial peripheral interface (SPI) controller - - Four I2C controllers - - Two DUARTs - - Integrated flash controller supporting NAND and NOR flash - - QorIQ platform's trust architecture 2.1 +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A +SoC overview. LS1043ARDB board Overview ----------------------- diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README index 6ddad92f2c..5c98866712 100644 --- a/board/freescale/ls2080aqds/README +++ b/board/freescale/ls2080aqds/README @@ -7,48 +7,9 @@ SW development platform for the Freescale LS2080A processor series, with a complete debugging environment. LS2080A SoC Overview ------------------- -The LS2080A integrated multicore processor combines eight ARM Cortex-A57 -processor cores with high-performance data path acceleration logic and network -and peripheral bus interfaces required for networking, telecom/datacom, -wireless infrastructure, and mil/aerospace applications. - -The LS2080A SoC includes the following function and features: - - - Eight 64-bit ARM Cortex-A57 CPUs - - 1 MB platform cache with ECC - - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support - - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by - the AIOP - - Data path acceleration architecture (DPAA2) incorporating acceleration for - the following functions: - - Packet parsing, classification, and distribution (WRIOP) - - Queue and Hardware buffer management for scheduling, packet sequencing, and - congestion management, buffer allocation and de-allocation (QBMan) - - Cryptography acceleration (SEC) at up to 10 Gbps - - RegEx pattern matching acceleration (PME) at up to 10 Gbps - - Decompression/compression acceleration (DCE) at up to 20 Gbps - - Accelerated I/O processing (AIOP) at up to 20 Gbps - - QDMA engine - - 16 SerDes lanes at up to 10.3125 GHz - - Ethernet interfaces - - Up to eight 10 Gbps Ethernet MACs - - Up to eight 1 / 2.5 Gbps Ethernet MACs - - High-speed peripheral interfaces - - Four PCIe 3.0 controllers, one supporting SR-IOV - - Additional peripheral interfaces - - Two serial ATA (SATA 3.0) controllers - - Two high-speed USB 3.0 controllers with integrated PHY - - Enhanced secure digital host controller (eSDXC/eMMC) - - Serial peripheral interface (SPI) controller - - Quad Serial Peripheral Interface (QSPI) Controller - - Four I2C controllers - - Two DUARTs - - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash - - Support for hardware virtualization and partitioning enforcement - - QorIQ platform's trust architecture 3.0 - - Service processor (SP) provides pre-boot initialization and secure-boot - capabilities +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A +SoC overview. LS2080AQDS board Overview ----------------------- diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README index 6708ca9cc7..b1613ba680 100644 --- a/board/freescale/ls2080ardb/README +++ b/board/freescale/ls2080ardb/README @@ -5,48 +5,9 @@ evaluation, and development platform that supports the QorIQ LS2080A Layerscape Architecture processor. LS2080A SoC Overview ------------------- -The LS2080A integrated multicore processor combines eight ARM Cortex-A57 -processor cores with high-performance data path acceleration logic and network -and peripheral bus interfaces required for networking, telecom/datacom, -wireless infrastructure, and mil/aerospace applications. - -The LS2080A SoC includes the following function and features: - - - Eight 64-bit ARM Cortex-A57 CPUs - - 1 MB platform cache with ECC - - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support - - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by - the AIOP - - Data path acceleration architecture (DPAA2) incorporating acceleration for - the following functions: - - Packet parsing, classification, and distribution (WRIOP) - - Queue and Hardware buffer management for scheduling, packet sequencing, and - congestion management, buffer allocation and de-allocation (QBMan) - - Cryptography acceleration (SEC) at up to 10 Gbps - - RegEx pattern matching acceleration (PME) at up to 10 Gbps - - Decompression/compression acceleration (DCE) at up to 20 Gbps - - Accelerated I/O processing (AIOP) at up to 20 Gbps - - QDMA engine - - 16 SerDes lanes at up to 10.3125 GHz - - Ethernet interfaces - - Up to eight 10 Gbps Ethernet MACs - - Up to eight 1 / 2.5 Gbps Ethernet MACs - - High-speed peripheral interfaces - - Four PCIe 3.0 controllers, one supporting SR-IOV - - Additional peripheral interfaces - - Two serial ATA (SATA 3.0) controllers - - Two high-speed USB 3.0 controllers with integrated PHY - - Enhanced secure digital host controller (eSDXC/eMMC) - - Serial peripheral interface (SPI) controller - - Quad Serial Peripheral Interface (QSPI) Controller - - Four I2C controllers - - Two DUARTs - - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash - - Support for hardware virtualization and partitioning enforcement - - QorIQ platform's trust architecture 3.0 - - Service processor (SP) provides pre-boot initialization and secure-boot - capabilities +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A +SoC overview. LS2080ARDB board Overview ----------------------- -- cgit v1.2.1