From 64917ca38933d10b3763f61df7a1e58e1e127b52 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Sun, 17 Jan 2010 15:38:26 -0600 Subject: PCIe, USB: Replace 'end point' references with 'endpoint' When referring to PCIe and USB 'endpoint' is the standard naming convention. Signed-off-by: Peter Tyser Acked-by: Stefan Roese Acked-by: Remy Bohmer --- board/freescale/mpc8536ds/mpc8536ds.c | 6 +++--- board/freescale/mpc8544ds/mpc8544ds.c | 6 +++--- board/freescale/mpc8548cds/mpc8548cds.c | 2 +- board/freescale/mpc8568mds/mpc8568mds.c | 2 +- board/freescale/mpc8569mds/mpc8569mds.c | 2 +- board/freescale/mpc8572ds/mpc8572ds.c | 6 +++--- board/freescale/mpc8610hpcd/mpc8610hpcd.c | 4 ++-- board/freescale/p1_p2_rdb/pci.c | 4 ++-- board/freescale/p2020ds/p2020ds.c | 6 +++--- 9 files changed, 19 insertions(+), 19 deletions(-) (limited to 'board/freescale') diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index f8292cf378..81a56b55e0 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -226,7 +226,7 @@ void pci_init_board(void) SET_STD_PCIE_INFO(pci_info[num], 3); pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); printf (" PCIE3 connected to Slot3 as %s (base address %lx)\n", - pcie_ep ? "End Point" : "Root Complex", + pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie3_hose, first_free_busno); @@ -246,7 +246,7 @@ void pci_init_board(void) SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); printf (" PCIE1 connected to Slot1 as %s (base address %lx)\n", - pcie_ep ? "End Point" : "Root Complex", + pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); @@ -266,7 +266,7 @@ void pci_init_board(void) SET_STD_PCIE_INFO(pci_info[num], 2); pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); printf (" PCIE2 connected to Slot 2 as %s (base address %lx)\n", - pcie_ep ? "End Point" : "Root Complex", + pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie2_hose, first_free_busno); diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 35a8063c9b..b35e02f685 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -144,7 +144,7 @@ void pci_init_board(void) pcie3_hose.region_count = 1; #endif printf (" PCIE3 connected to ULI as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", + pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie3_hose, first_free_busno); @@ -179,7 +179,7 @@ void pci_init_board(void) pcie1_hose.region_count = 1; #endif printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", + pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], @@ -210,7 +210,7 @@ void pci_init_board(void) pcie2_hose.region_count = 1; #endif printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", + pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie2_hose, first_free_busno); diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 38cbc8bac1..aa3f32bf67 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -343,7 +343,7 @@ void pci_init_board(void) SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); printf (" PCIE1 connected to Slot as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", + pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index 60e22de4b9..4ec13a9691 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -408,7 +408,7 @@ void pci_init_board(void) SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); printf (" PCIE1 connected to Slot as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", + pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 56854caa8d..1c76b84efc 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -552,7 +552,7 @@ void pci_init_board(void) SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); printf (" PCIE1 connected to Slot as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", + pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 64e164b1a0..74085c3260 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -194,7 +194,7 @@ void pci_init_board(void) SET_STD_PCIE_INFO(pci_info[num], 3); pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); printf (" PCIE3 connected to ULI as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", + pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie3_hose, first_free_busno); @@ -226,7 +226,7 @@ void pci_init_board(void) SET_STD_PCIE_INFO(pci_info[num], 2); pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", + pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie2_hose, first_free_busno); @@ -246,7 +246,7 @@ void pci_init_board(void) SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", + pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index 2d4b9addb6..784a2ed686 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -249,7 +249,7 @@ void pci_init_board(void) SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); printf (" PCIE1 connected to ULI as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", + pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], @@ -270,7 +270,7 @@ void pci_init_board(void) SET_STD_PCIE_INFO(pci_info[num], 2); pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); printf (" PCIE2 connected to Slot as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", + pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie2_hose, first_free_busno); diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c index 6fd6963f0c..aa2f64ca91 100644 --- a/board/freescale/p1_p2_rdb/pci.c +++ b/board/freescale/p1_p2_rdb/pci.c @@ -66,7 +66,7 @@ void pci_init_board(void) SET_STD_PCIE_INFO(pci_info[num], 2); pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); printf(" PCIE2 connected to Slot 1 as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", + pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie2_hose, first_free_busno); @@ -85,7 +85,7 @@ void pci_init_board(void) SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", + pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index 599caa235d..f6eae55d1d 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -222,7 +222,7 @@ void pci_init_board(void) SET_STD_PCIE_INFO(pci_info[num], 2); pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); printf(" PCIE2 connected to ULI as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", + pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie2_hose, first_free_busno); @@ -262,7 +262,7 @@ void pci_init_board(void) SET_STD_PCIE_INFO(pci_info[num], 3); pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); printf(" PCIE3 connected to Slot 1 as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", + pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie3_hose, first_free_busno); @@ -281,7 +281,7 @@ void pci_init_board(void) SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", + pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); -- cgit v1.2.1