From 29bc24ec4f9f159b3fdaf9c85cce89504a54782a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 23 Nov 2015 16:18:02 -0200 Subject: mx6sxsabresd: Fix Ethernet PHY reset sequence MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since commit 59370f3fcd1350 ("net: phy: delay only if reset handler is registered") Ethernet is no longer functional. This commit does not have an issue in itself, but it revelead a problem with the Ethernet initialization. Fix this by calling enable_fec_anatop_clock() earlier and also by adding a 10ms reset delay as recommended in the AR8031 datasheet. Suggested-by: Jörg Krause Signed-off-by: Fabio Estevam Reviewed-by: Stefano Babic --- board/freescale/mx6sxsabresd/mx6sxsabresd.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'board/freescale') diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 3ee46629ee..56dc0208c7 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -150,11 +150,15 @@ static int setup_fec(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; - int reg; + int reg, ret; /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); + ret = enable_fec_anatop_clock(0, ENET_125MHZ); + if (ret) + return ret; + imx_iomux_v3_setup_multiple_pads(phy_control_pads, ARRAY_SIZE(phy_control_pads)); @@ -163,14 +167,14 @@ static int setup_fec(void) /* Reset AR8031 PHY */ gpio_direction_output(IMX_GPIO_NR(2, 7) , 0); - udelay(500); + mdelay(10); gpio_set_value(IMX_GPIO_NR(2, 7), 1); reg = readl(&anatop->pll_enet); reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; writel(reg, &anatop->pll_enet); - return enable_fec_anatop_clock(0, ENET_125MHZ); + return 0; } int board_eth_init(bd_t *bis) -- cgit v1.2.1