From 10795f42cb94e71bcb262b615084f69dd886399a Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 2 Dec 2008 16:08:36 -0600 Subject: 85xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boards Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead of _MEM_BASE so we are more explicit. Signed-off-by: Kumar Gala Acked-by: Andy Fleming --- board/freescale/mpc8536ds/mpc8536ds.c | 20 ++++++++++---------- board/freescale/mpc8540ads/law.c | 2 +- board/freescale/mpc8540ads/tlb.c | 4 ++-- board/freescale/mpc8544ds/mpc8544ds.c | 26 +++++++++++++------------- board/freescale/mpc8548cds/mpc8548cds.c | 4 ++-- board/freescale/mpc8548cds/tlb.c | 4 ++-- board/freescale/mpc8560ads/law.c | 2 +- board/freescale/mpc8560ads/tlb.c | 4 ++-- board/freescale/mpc8568mds/law.c | 2 +- board/freescale/mpc8568mds/mpc8568mds.c | 4 ++-- board/freescale/mpc8572ds/mpc8572ds.c | 6 +++--- 11 files changed, 39 insertions(+), 39 deletions(-) (limited to 'board/freescale') diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index e369d090cc..280ae1a317 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -192,7 +192,7 @@ pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE3_MEM_BASE, + CONFIG_SYS_PCIE3_MEM_BUS, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_SIZE, PCI_REGION_MEM); @@ -247,7 +247,7 @@ pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); @@ -259,10 +259,10 @@ pci_init_board(void) CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); -#ifdef CONFIG_SYS_PCIE1_MEM_BASE2 +#ifdef CONFIG_SYS_PCIE1_MEM_BUS2 /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BASE2, + CONFIG_SYS_PCIE1_MEM_BUS2, CONFIG_SYS_PCIE1_MEM_PHYS2, CONFIG_SYS_PCIE1_MEM_SIZE2, PCI_REGION_MEM); @@ -310,7 +310,7 @@ pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BASE, + CONFIG_SYS_PCIE2_MEM_BUS, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_SIZE, PCI_REGION_MEM); @@ -322,10 +322,10 @@ pci_init_board(void) CONFIG_SYS_PCIE2_IO_SIZE, PCI_REGION_IO); -#ifdef CONFIG_SYS_PCIE2_MEM_BASE2 +#ifdef CONFIG_SYS_PCIE2_MEM_BUS2 /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BASE2, + CONFIG_SYS_PCIE2_MEM_BUS2, CONFIG_SYS_PCIE2_MEM_PHYS2, CONFIG_SYS_PCIE2_MEM_SIZE2, PCI_REGION_MEM); @@ -378,7 +378,7 @@ pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_BUS, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); @@ -390,10 +390,10 @@ pci_init_board(void) CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); -#ifdef CONFIG_SYS_PCI1_MEM_BASE2 +#ifdef CONFIG_SYS_PCI1_MEM_BUS2 /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BASE2, + CONFIG_SYS_PCI1_MEM_BUS2, CONFIG_SYS_PCI1_MEM_PHYS2, CONFIG_SYS_PCI1_MEM_SIZE2, PCI_REGION_MEM); diff --git a/board/freescale/mpc8540ads/law.c b/board/freescale/mpc8540ads/law.c index 7dd8f29588..ff56e87dd7 100644 --- a/board/freescale/mpc8540ads/law.c +++ b/board/freescale/mpc8540ads/law.c @@ -52,7 +52,7 @@ struct law_entry law_table[] = { /* This is not so much the SDRAM map as it is the whole localbus map. */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_RIO_MEM_BUS, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c index 2ec3ccce97..758bd70065 100644 --- a/board/freescale/mpc8540ads/tlb.c +++ b/board/freescale/mpc8540ads/tlb.c @@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0xc0000000 256M Rapid IO MEM First half */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS, CONFIG_SYS_RIO_MEM_BUS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), @@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xd0000000 256M Rapid IO MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 977731289b..c3bf60a46d 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -139,7 +139,7 @@ pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE3_MEM_BASE, + CONFIG_SYS_PCIE3_MEM_BUS, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_SIZE, PCI_REGION_MEM); @@ -151,10 +151,10 @@ pci_init_board(void) CONFIG_SYS_PCIE3_IO_SIZE, PCI_REGION_IO); -#ifdef CONFIG_SYS_PCIE3_MEM_BASE2 +#ifdef CONFIG_SYS_PCIE3_MEM_BUS2 /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE3_MEM_BASE2, + CONFIG_SYS_PCIE3_MEM_BUS2, CONFIG_SYS_PCIE3_MEM_PHYS2, CONFIG_SYS_PCIE3_MEM_SIZE2, PCI_REGION_MEM); @@ -173,7 +173,7 @@ pci_init_board(void) * Activate ULI1575 legacy chip by performing a fake * memory access. Needed to make ULI RTC work. */ - in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BASE); + in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS); } else { printf (" PCIE3: disabled\n"); } @@ -206,7 +206,7 @@ pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); @@ -218,10 +218,10 @@ pci_init_board(void) CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); -#ifdef CONFIG_SYS_PCIE1_MEM_BASE2 +#ifdef CONFIG_SYS_PCIE1_MEM_BUS2 /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BASE2, + CONFIG_SYS_PCIE1_MEM_BUS2, CONFIG_SYS_PCIE1_MEM_PHYS2, CONFIG_SYS_PCIE1_MEM_SIZE2, PCI_REGION_MEM); @@ -269,7 +269,7 @@ pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BASE, + CONFIG_SYS_PCIE2_MEM_BUS, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_SIZE, PCI_REGION_MEM); @@ -281,10 +281,10 @@ pci_init_board(void) CONFIG_SYS_PCIE2_IO_SIZE, PCI_REGION_IO); -#ifdef CONFIG_SYS_PCIE2_MEM_BASE2 +#ifdef CONFIG_SYS_PCIE2_MEM_BUS2 /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BASE2, + CONFIG_SYS_PCIE2_MEM_BUS2, CONFIG_SYS_PCIE2_MEM_PHYS2, CONFIG_SYS_PCIE2_MEM_SIZE2, PCI_REGION_MEM); @@ -337,7 +337,7 @@ pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_BUS, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); @@ -349,10 +349,10 @@ pci_init_board(void) CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); -#ifdef CONFIG_SYS_PCIE3_MEM_BASE2 +#ifdef CONFIG_SYS_PCIE3_MEM_BUS2 /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE3_MEM_BASE2, + CONFIG_SYS_PCIE3_MEM_BUS2, CONFIG_SYS_PCIE3_MEM_PHYS2, CONFIG_SYS_PCIE3_MEM_SIZE2, PCI_REGION_MEM); diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 90e89bc719..ff8d26fb9c 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -306,7 +306,7 @@ pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_BUS, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); @@ -390,7 +390,7 @@ pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c index eab212a4c5..e96c9a7fca 100644 --- a/board/freescale/mpc8548cds/tlb.c +++ b/board/freescale/mpc8548cds/tlb.c @@ -62,14 +62,14 @@ struct fsl_e_tlb_entry tlb_table[] = { /* * TLB 2: 256M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS, CONFIG_SYS_RIO_MEM_BUS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), /* * TLB 3: 256M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), #endif diff --git a/board/freescale/mpc8560ads/law.c b/board/freescale/mpc8560ads/law.c index 7dd8f29588..ff56e87dd7 100644 --- a/board/freescale/mpc8560ads/law.c +++ b/board/freescale/mpc8560ads/law.c @@ -52,7 +52,7 @@ struct law_entry law_table[] = { /* This is not so much the SDRAM map as it is the whole localbus map. */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_RIO_MEM_BUS, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c index 2ec3ccce97..758bd70065 100644 --- a/board/freescale/mpc8560ads/tlb.c +++ b/board/freescale/mpc8560ads/tlb.c @@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0xc0000000 256M Rapid IO MEM First half */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS, CONFIG_SYS_RIO_MEM_BUS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), @@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xd0000000 256M Rapid IO MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c index da7b6dcb72..a06ac2a0e1 100644 --- a/board/freescale/mpc8568mds/law.c +++ b/board/freescale/mpc8568mds/law.c @@ -54,7 +54,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI), SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_SRIO_MEM_BUS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), /* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index 7a23b338a5..20f70fb520 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -397,7 +397,7 @@ pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_BUS, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); @@ -450,7 +450,7 @@ pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 88ab06d789..01143ec89f 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -185,7 +185,7 @@ void pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE3_MEM_BASE, + CONFIG_SYS_PCIE3_MEM_BUS, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_SIZE, PCI_REGION_MEM); @@ -252,7 +252,7 @@ void pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BASE, + CONFIG_SYS_PCIE2_MEM_BUS, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_SIZE, PCI_REGION_MEM); @@ -307,7 +307,7 @@ void pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); -- cgit v1.2.1