From 449372148f6d9b5b8bded88ed8eee5c581a4bf81 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Mon, 9 Nov 2015 16:42:07 +0530 Subject: armv8: LS2080A: Rename LS2085A to reflect LS2080A MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava Signed-off-by: Prabhakar Kushwaha [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun --- board/freescale/ls2080ardb/eth_ls2080rdb.c | 147 +++++++++++++++++++++++++++++ 1 file changed, 147 insertions(+) create mode 100644 board/freescale/ls2080ardb/eth_ls2080rdb.c (limited to 'board/freescale/ls2080ardb/eth_ls2080rdb.c') diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c new file mode 100644 index 0000000000..db50e4efa9 --- /dev/null +++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c @@ -0,0 +1,147 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int load_firmware_cortina(struct phy_device *phy_dev) +{ + if (phy_dev->drv->config) + return phy_dev->drv->config(phy_dev); + + return 0; +} + +void load_phy_firmware(void) +{ + int i; + u8 phy_addr; + struct phy_device *phy_dev; + struct mii_dev *dev; + phy_interface_t interface; + + /*Initialize and upload firmware for all the PHYs*/ + for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC8; i++) { + interface = wriop_get_enet_if(i); + if (interface == PHY_INTERFACE_MODE_XGMII) { + dev = wriop_get_mdio(i); + phy_addr = wriop_get_phy_address(i); + phy_dev = phy_find_by_mask(dev, 1 << phy_addr, + interface); + if (!phy_dev) { + printf("No phydev for phyaddr %d\n", phy_addr); + continue; + } + + /*Flash firmware for All CS4340 PHYS */ + if (phy_dev->phy_id == PHY_UID_CS4340) + load_firmware_cortina(phy_dev); + } + } +} + +int board_eth_init(bd_t *bis) +{ +#if defined(CONFIG_FSL_MC_ENET) + int i, interface; + struct memac_mdio_info mdio_info; + struct mii_dev *dev; + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 srds_s1; + struct memac_mdio_controller *reg; + + srds_s1 = in_le32(&gur->rcwsr[28]) & + FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + + reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1; + mdio_info.regs = reg; + mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME; + + /* Register the EMI 1 */ + fm_memac_mdio_init(bis, &mdio_info); + + reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2; + mdio_info.regs = reg; + mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; + + /* Register the EMI 2 */ + fm_memac_mdio_init(bis, &mdio_info); + + switch (srds_s1) { + case 0x2A: + wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2); + wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3); + wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4); + wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2); + wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3); + wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4); + + break; + default: + printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n", + srds_s1); + break; + } + + for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) { + interface = wriop_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_XGMII: + dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); + wriop_set_mdio(i, dev); + break; + default: + break; + } + } + + for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) { + switch (wriop_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); + wriop_set_mdio(i, dev); + break; + default: + break; + } + } + + /* Load CORTINA CS4340 PHY firmware */ + load_phy_firmware(); + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + +#ifdef CONFIG_PHY_AQUANTIA + /* + * Export functions to be used by AQ firmware + * upload application + */ + gd->jt->strcpy = strcpy; + gd->jt->mdelay = mdelay; + gd->jt->mdio_get_current_dev = mdio_get_current_dev; + gd->jt->phy_find_by_mask = phy_find_by_mask; + gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; + gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; +#endif + return pci_eth_init(bis); +} -- cgit v1.2.1