From 449372148f6d9b5b8bded88ed8eee5c581a4bf81 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Mon, 9 Nov 2015 16:42:07 +0530 Subject: armv8: LS2080A: Rename LS2085A to reflect LS2080A MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava Signed-off-by: Prabhakar Kushwaha [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun --- board/freescale/ls2080a/Kconfig | 31 ++++++ board/freescale/ls2080a/MAINTAINERS | 8 ++ board/freescale/ls2080a/Makefile | 8 ++ board/freescale/ls2080a/README | 27 +++++ board/freescale/ls2080a/ddr.c | 207 ++++++++++++++++++++++++++++++++++++ board/freescale/ls2080a/ddr.h | 86 +++++++++++++++ board/freescale/ls2080a/ls2080a.c | 152 ++++++++++++++++++++++++++ 7 files changed, 519 insertions(+) create mode 100644 board/freescale/ls2080a/Kconfig create mode 100644 board/freescale/ls2080a/MAINTAINERS create mode 100644 board/freescale/ls2080a/Makefile create mode 100644 board/freescale/ls2080a/README create mode 100644 board/freescale/ls2080a/ddr.c create mode 100644 board/freescale/ls2080a/ddr.h create mode 100644 board/freescale/ls2080a/ls2080a.c (limited to 'board/freescale/ls2080a') diff --git a/board/freescale/ls2080a/Kconfig b/board/freescale/ls2080a/Kconfig new file mode 100644 index 0000000000..0b938ffb54 --- /dev/null +++ b/board/freescale/ls2080a/Kconfig @@ -0,0 +1,31 @@ +if TARGET_LS2080A_EMU + +config SYS_BOARD + default "ls2080a" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls2080a_emu" + +endif + +if TARGET_LS2080A_SIMU + +config SYS_BOARD + default "ls2080a" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls2080a_simu" + +endif diff --git a/board/freescale/ls2080a/MAINTAINERS b/board/freescale/ls2080a/MAINTAINERS new file mode 100644 index 0000000000..bb25084576 --- /dev/null +++ b/board/freescale/ls2080a/MAINTAINERS @@ -0,0 +1,8 @@ +LS2080A BOARD +M: York Sun +S: Maintained +F: board/freescale/ls2080a/ +F: include/configs/ls2080a_emu.h +F: configs/ls2080a_emu_defconfig +F: include/configs/ls2080a_simu.h +F: configs/ls2080a_simu_defconfig diff --git a/board/freescale/ls2080a/Makefile b/board/freescale/ls2080a/Makefile new file mode 100644 index 0000000000..47c7c748ea --- /dev/null +++ b/board/freescale/ls2080a/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2014-15 Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls2080a.o +obj-y += ddr.o diff --git a/board/freescale/ls2080a/README b/board/freescale/ls2080a/README new file mode 100644 index 0000000000..7e53f1f1e4 --- /dev/null +++ b/board/freescale/ls2080a/README @@ -0,0 +1,27 @@ +Freescale ls2080a_emu + +This is a emulator target with limited peripherals. + +Memory map from core's view + +0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom +0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR +0x00_1800_0000 .. 0x00_181F_FFFF OCRAM +0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1 +0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1 +0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2 +0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2 + +Other addresses are either reserved, or not used directly by u-boot. +This list should be updated when more addresses are used. + +Booting Linux flavors which do not support 48-bit VA (< Linux 3.18) +------------------------------------------------------------------- +One needs to use appropriate bootargs to boot Linux flavors which do +not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown +below: + +=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram + earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m + hugepages=16 mem=2048M' + diff --git a/board/freescale/ls2080a/ddr.c b/board/freescale/ls2080a/ddr.c new file mode 100644 index 0000000000..47d73ef75a --- /dev/null +++ b/board/freescale/ls2080a/ddr.c @@ -0,0 +1,207 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 3) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + /* + * we use identical timing for all slots. If needed, change the code + * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; + */ + if (popts->registered_dimm_en) + pbsp = rdimms[ctrl_num]; + else + pbsp = udimms[ctrl_num]; + + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks && + (pdimm->rank_density >> 30) >= pbsp->rank_gb) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for data rate %lu MT/s\n" + "Trying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, + pbsp->wrlvl_ctl_3); +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR + if (ctrl_num == CONFIG_DP_DDR_CTRL) { + /* force DDR bus width to 32 bits */ + popts->data_bus_width = 1; + popts->otf_burst_chop_en = 0; + popts->burst_length = DDR_BL8; + popts->bstopre = 0; /* enable auto precharge */ + } +#endif + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 1; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + +#ifdef CONFIG_SYS_FSL_DDR4 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ +#else + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +#endif +} + +#ifdef CONFIG_SYS_DDR_RAW_TIMING +dimm_params_t ddr_raw_timing = { + .n_ranks = 2, + .rank_density = 1073741824u, + .capacity = 2147483648, + .primary_sdram_width = 64, + .ec_sdram_width = 0, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 14, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + + .tckmin_x_ps = 937, + .caslat_x = 0x6FC << 4, /* 14,13,11,10,9,8,7,6 */ + .taa_ps = 13090, + .twr_ps = 15000, + .trcd_ps = 13090, + .trrd_ps = 5000, + .trp_ps = 13090, + .tras_ps = 33000, + .trc_ps = 46090, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, + .refresh_rate_ps = 7800000, + .tfaw_ps = 25000, +}; + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "Fixed DDR on board"; + + if (((controller_number == 0) && (dimm_number == 0)) || + ((controller_number == 1) && (dimm_number == 0))) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} +#endif +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + + puts("Initializing DDR...."); + + puts("using SPD\n"); + dram_size = fsl_ddr_sdram(); + + return dram_size; +} + +void dram_init_banksize(void) +{ +#ifdef CONFIG_SYS_DP_DDR_BASE_PHY + phys_size_t dp_ddr_size; +#endif + + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) { + gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; + gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; + gd->bd->bi_dram[1].size = gd->ram_size - + CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; + } else { + gd->bd->bi_dram[0].size = gd->ram_size; + } + +#ifdef CONFIG_SYS_DP_DDR_BASE_PHY + /* initialize DP-DDR here */ + puts("DP-DDR: "); + /* + * DDR controller use 0 as the base address for binding. + * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. + */ + dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, + CONFIG_DP_DDR_CTRL, + CONFIG_DP_DDR_NUM_CTRLS, + CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, + NULL, NULL, NULL); + if (dp_ddr_size) { + gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; + gd->bd->bi_dram[2].size = dp_ddr_size; + } else { + puts("Not detected"); + } +#endif +} diff --git a/board/freescale/ls2080a/ddr.h b/board/freescale/ls2080a/ddr.h new file mode 100644 index 0000000000..9958a68e3e --- /dev/null +++ b/board/freescale/ls2080a/ddr.h @@ -0,0 +1,86 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ + +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {2, 2140, 0, 4, 4, 0x0, 0x0}, + {1, 2140, 0, 4, 4, 0x0, 0x0}, + {} +}; + +/* DP-DDR DIMM */ +static const struct board_specific_parameters udimm2[] = { + /* + * memory controller 2 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {2, 2140, 0, 4, 4, 0x0, 0x0}, + {1, 2140, 0, 4, 4, 0x0, 0x0}, + {} +}; + +static const struct board_specific_parameters rdimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {4, 2140, 0, 5, 4, 0x0, 0x0}, + {2, 2140, 0, 5, 4, 0x0, 0x0}, + {1, 2140, 0, 4, 4, 0x0, 0x0}, + {} +}; + +/* DP-DDR DIMM */ +static const struct board_specific_parameters rdimm2[] = { + /* + * memory controller 2 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {4, 2140, 0, 5, 4, 0x0, 0x0}, + {2, 2140, 0, 5, 4, 0x0, 0x0}, + {1, 2140, 0, 4, 4, 0x0, 0x0}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, + udimm0, + udimm2, +}; + +static const struct board_specific_parameters *rdimms[] = { + rdimm0, + rdimm0, + rdimm2, +}; + + +#endif diff --git a/board/freescale/ls2080a/ls2080a.c b/board/freescale/ls2080a/ls2080a.c new file mode 100644 index 0000000000..827fbf0835 --- /dev/null +++ b/board/freescale/ls2080a/ls2080a.c @@ -0,0 +1,152 @@ +/* + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + init_final_memctl_regs(); + +#ifdef CONFIG_ENV_IS_NOWHERE + gd->env_addr = (ulong)&default_environment[0]; +#endif + + return 0; +} + +int board_early_init_f(void) +{ + fsl_lsch3_early_init_f(); + return 0; +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); + print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_ddr_info(0); +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR + if (gd->bd->bi_dram[2].size) { + puts("\nDP-DDR "); + print_size(gd->bd->bi_dram[2].size, ""); + print_ddr_info(CONFIG_DP_DDR_CTRL); + } +#endif +} + +int dram_init(void) +{ + gd->ram_size = initdram(0); + + return 0; +} + +#if defined(CONFIG_ARCH_MISC_INIT) +int arch_misc_init(void) +{ +#ifdef CONFIG_FSL_DEBUG_SERVER + debug_server_init(); +#endif + + return 0; +} +#endif + +unsigned long get_dram_size_to_hide(void) +{ + unsigned long dram_to_hide = 0; + +/* Carve the Debug Server private DRAM block from the end of DRAM */ +#ifdef CONFIG_FSL_DEBUG_SERVER + dram_to_hide += debug_server_get_dram_block_size(); +#endif + +/* Carve the MC private DRAM block from the end of DRAM */ +#ifdef CONFIG_FSL_MC_ENET + dram_to_hide += mc_get_dram_block_size(); +#endif + + return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN); +} + +int board_eth_init(bd_t *bis) +{ + int error = 0; + +#ifdef CONFIG_SMC91111 + error = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + +#ifdef CONFIG_FSL_MC_ENET + error = cpu_eth_init(bis); +#endif + return error; +} + +#ifdef CONFIG_FSL_MC_ENET +void fdt_fixup_board_enet(void *fdt) +{ + int offset; + + offset = fdt_path_offset(fdt, "/fsl-mc"); + + /* + * TODO: Remove this when backward compatibility + * with old DT node (fsl,dprc@0) is no longer needed. + */ + if (offset < 0) + offset = fdt_path_offset(fdt, "/fsl,dprc@0"); + + if (offset < 0) { + printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", + __func__, offset); + return; + } + + if (get_mc_boot_status() == 0) + fdt_status_okay(fdt, offset); + else + fdt_status_fail(fdt, offset); +} +#endif + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + ft_cpu_setup(blob, bd); + + /* fixup DT for the two GPP DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + + fdt_fixup_memory_banks(blob, base, size, 2); + +#ifdef CONFIG_FSL_MC_ENET + fdt_fixup_board_enet(blob); + fsl_mc_ldpaa_exit(bd); +#endif + + return 0; +} +#endif -- cgit v1.2.1