From ea339205a94706d8b9170bbd89e8c1373df9a92f Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 8 Nov 2005 09:00:09 +0100 Subject: Updated PCI mapping for esd CPCI2DP board. Add support for error LED. Patch by Matthias Fuchs, 07 Nov 2005 --- board/esd/cpci2dp/cpci2dp.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) (limited to 'board/esd') diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c index 727640e9b5..b463f0e389 100644 --- a/board/esd/cpci2dp/cpci2dp.c +++ b/board/esd/cpci2dp/cpci2dp.c @@ -31,14 +31,17 @@ int board_early_init_f (void) unsigned long cntrl0Reg; /* - * Setup GPIO pins (CS4 as GPIO) + * Setup GPIO pins (CS4+CS7 as GPIO) */ cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00800000); - - out32(GPIO0_OR, CFG_INTA_FAKE | CFG_EEPROM_WP); /* set output pins to high */ - out32(GPIO0_ODR, CFG_INTA_FAKE); /* INTA# is open drain */ - out32(GPIO0_TCR, CFG_INTA_FAKE | CFG_EEPROM_WP); /* setup for output */ + mtdcr(cntrl0, cntrl0Reg | 0x00900000); + + /* set output pins to high */ + out32(GPIO0_OR, CFG_INTA_FAKE | CFG_EEPROM_WP | CFG_PB_LED); + /* INTA# is open drain */ + out32(GPIO0_ODR, CFG_INTA_FAKE); + /* setup for output */ + out32(GPIO0_TCR, CFG_INTA_FAKE | CFG_EEPROM_WP); /* * IRQ 0-15 405GP internally generated; active high; level sensitive -- cgit v1.2.1