From 9453967e28c5e3abbf856f95735ea69bae1e77fa Mon Sep 17 00:00:00 2001 From: Albin Tonnerre Date: Mon, 24 Aug 2009 18:03:26 +0200 Subject: Add support for the Calao SBC35-A9G20 board The Calao SBC35-A9G20 board is manufactured and sold by Calao Systems . It is built around an AT91SAM9G20 ARM SoC running at 400MHz. It features an Ethernet port, an SPI RTC backed by an onboard battery , an SD/MMC slot, a CompactFlash slot, 64Mo of SDRAM, 256Mo of NAND flash, two USB host ports, and an USB device port. More informations can be found at Signed-off-by: Albin Tonnerre --- board/calao/sbc35_a9g20/Makefile | 55 ++++++++++ board/calao/sbc35_a9g20/config.mk | 1 + board/calao/sbc35_a9g20/sbc35_a9g20.c | 197 ++++++++++++++++++++++++++++++++++ board/calao/sbc35_a9g20/spi.c | 57 ++++++++++ 4 files changed, 310 insertions(+) create mode 100644 board/calao/sbc35_a9g20/Makefile create mode 100644 board/calao/sbc35_a9g20/config.mk create mode 100644 board/calao/sbc35_a9g20/sbc35_a9g20.c create mode 100644 board/calao/sbc35_a9g20/spi.c (limited to 'board/calao/sbc35_a9g20') diff --git a/board/calao/sbc35_a9g20/Makefile b/board/calao/sbc35_a9g20/Makefile new file mode 100644 index 0000000000..8b4a9116b2 --- /dev/null +++ b/board/calao/sbc35_a9g20/Makefile @@ -0,0 +1,55 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop +# Lead Tech Design +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += sbc35_a9g20.o +COBJS-$(CONFIG_ATMEL_SPI) += spi.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/calao/sbc35_a9g20/config.mk b/board/calao/sbc35_a9g20/config.mk new file mode 100644 index 0000000000..ff2cfd170b --- /dev/null +++ b/board/calao/sbc35_a9g20/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x23f00000 diff --git a/board/calao/sbc35_a9g20/sbc35_a9g20.c b/board/calao/sbc35_a9g20/sbc35_a9g20.c new file mode 100644 index 0000000000..da34b40e50 --- /dev/null +++ b/board/calao/sbc35_a9g20/sbc35_a9g20.c @@ -0,0 +1,197 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * Copyright (C) 2009 + * Albin Tonnerre, Free-Electrons + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) +#include +#endif +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +#ifdef CONFIG_CMD_NAND +static void sbc35_a9g20_nand_hw_init(void) +{ + unsigned long csa; + + /* Enable CS3 */ + csa = at91_sys_read(AT91_MATRIX_EBICSA); + at91_sys_write(AT91_MATRIX_EBICSA, + csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + + /* Configure SMC CS3 for NAND/SmartMedia */ + at91_sys_write(AT91_SMC_SETUP(3), + AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(3), + AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); + at91_sys_write(AT91_SMC_CYCLE(3), + AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); + at91_sys_write(AT91_SMC_MODE(3), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_DBW_8 | +#endif + AT91_SMC_TDF_(2)); + + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} +#endif + +#ifdef CONFIG_MACB +static void sbc35_a9g20_macb_hw_init(void) +{ + unsigned long rstc; + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); + + /* + * Disable pull-up on: + * RXDV (PA17) => PHY normal mode (not Test mode) + * ERX0 (PA14) => PHY ADDR0 + * ERX1 (PA15) => PHY ADDR1 + * ERX2 (PA25) => PHY ADDR2 + * ERX3 (PA26) => PHY ADDR3 + * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 + * + * PHY has internal pull-down + */ + writel(pin_to_mask(AT91_PIN_PA14) | + pin_to_mask(AT91_PIN_PA15) | + pin_to_mask(AT91_PIN_PA17) | + pin_to_mask(AT91_PIN_PA25) | + pin_to_mask(AT91_PIN_PA26) | + pin_to_mask(AT91_PIN_PA28), + pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); + + rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL; + + /* Need to reset PHY -> 500ms reset */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + (AT91_RSTC_ERSTL & (0x0D << 8)) | + AT91_RSTC_URSTEN); + + at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + + /* Wait for end hardware reset */ + while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); + + /* Restore NRST value */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + (rstc) | + AT91_RSTC_URSTEN); + + /* Re-enable pull-up */ + writel(pin_to_mask(AT91_PIN_PA14) | + pin_to_mask(AT91_PIN_PA15) | + pin_to_mask(AT91_PIN_PA17) | + pin_to_mask(AT91_PIN_PA25) | + pin_to_mask(AT91_PIN_PA26) | + pin_to_mask(AT91_PIN_PA28), + pin_to_controller(AT91_PIN_PA0) + PIO_PUER); + + at91_macb_hw_init(); +} +#endif + +int board_init(void) +{ + /* Enable Ctrlc */ + console_init_f(); + + gd->bd->bi_arch_number = MACH_TYPE_SBC35_A9G20; + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + at91_serial_hw_init(); + sbc35_a9g20_nand_hw_init(); +#ifdef CONFIG_ATMEL_SPI + at91_spi0_hw_init(1 << 4 | 1 << 5); +#endif +#ifdef CONFIG_MACB + sbc35_a9g20_macb_hw_init(); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + if(get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) != PHYS_SDRAM_SIZE) + return -1; + + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +#ifdef CONFIG_MACB + /* + * Initialize ethernet HW addr prior to starting Linux, + * needed for nfsroot + */ + eth_init(gd->bd); +#endif +} +#endif + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00); +#endif + return rc; +} diff --git a/board/calao/sbc35_a9g20/spi.c b/board/calao/sbc35_a9g20/spi.c new file mode 100644 index 0000000000..1057fa2e99 --- /dev/null +++ b/board/calao/sbc35_a9g20/spi.c @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2009 + * Albin Tonnerre, Free Electrons + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#define SBC_A9260_CS0_PIN AT91_PIN_PA3 +#define SBC_A9260_CS1_PIN AT91_PIN_PC11 + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && (cs == 1 || cs == 0); +} + +void spi_cs_activate(struct spi_slave *slave) +{ + if(slave->cs == 0) + at91_set_gpio_value(SBC_A9260_CS0_PIN, 0); + else if(slave->cs == 1) + at91_set_gpio_value(SBC_A9260_CS1_PIN, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + if(slave->cs == 0) + at91_set_gpio_value(SBC_A9260_CS0_PIN, 1); + else if(slave->cs == 1) + at91_set_gpio_value(SBC_A9260_CS1_PIN, 1); +} + +void spi_init_f(void) +{ + /* everything done in board_init */ +} -- cgit v1.2.1