From 952e7760bfc5b0e3b142b9ce34e7fbb7d008c900 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 24 Sep 2009 09:55:50 +0200 Subject: ppc4xx: Convert PPC4xx UIC defines from lower case to upper case The latest PPC4xx register cleanup patch missed the UIC defines. This patch now changes lower case UIC defines to upper case. Signed-off-by: Stefan Roese --- board/amcc/yucca/yucca.c | 64 ++++++++++++++++++++++++------------------------ 1 file changed, 32 insertions(+), 32 deletions(-) (limited to 'board/amcc/yucca') diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 245004cee8..033bdd20fa 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -485,50 +485,50 @@ int board_early_init_f (void) | interrupt trigger levels. Make bit 0 High priority. Clear all | interrupts again. +-------------------------------------------------------------------*/ - mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic3er, 0x00000000); /* disable all interrupts */ - mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical + mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */ + mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical * interrupts */ - mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */ - mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest + mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */ + mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest * priority */ - mtdcr (uic3sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic3sr, 0xffffffff); /* clear all interrupts */ + mtdcr (UIC3SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts */ - mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic2er, 0x00000000); /* disable all interrupts */ - mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical + mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */ + mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical * interrupts */ - mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities */ - mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */ - mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest + mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities */ + mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */ + mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest * priority */ - mtdcr (uic2sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */ + mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */ - mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic1er, 0x00000000); /* disable all interrupts */ - mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical + mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */ + mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical * interrupts */ - mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels */ - mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest + mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels */ + mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest * priority */ - mtdcr (uic1sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */ + mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */ - mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted + mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted * cascade to be checked */ - mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical + mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical * interrupts */ - mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */ - mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest + mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */ + mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest * priority */ - mtdcr (uic0sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */ + mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */ mfsdr(SDR0_MFR, mfr); mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ -- cgit v1.2.1