From 29155e735203b28951d0e836f13773defa6e6118 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 24 Oct 2015 17:24:07 -0400 Subject: ocotea: Drop This board has not compiled for me for quite some time due to size constraints, remove. Cc: Stefan Roese Signed-off-by: Tom Rini Reviewed-by: Bin Meng Signed-off-by: Stefan Roese --- board/amcc/ocotea/init.S | 42 ------------------------------------------ 1 file changed, 42 deletions(-) delete mode 100644 board/amcc/ocotea/init.S (limited to 'board/amcc/ocotea/init.S') diff --git a/board/amcc/ocotea/init.S b/board/amcc/ocotea/init.S deleted file mode 100644 index 35085f0a06..0000000000 --- a/board/amcc/ocotea/init.S +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2002 Scott McNutt - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX) - tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX) - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG) - tlbtab_end -- cgit v1.2.1