From 0c028a03284aabceb89a85736e23661d6fe7915e Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Fri, 20 Nov 2015 15:52:02 +0800 Subject: arm: ls102x: add get_svr and IS_SVR_REV helper Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- arch/arm/cpu/armv7/ls102xa/cpu.c | 8 ++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 5 +++++ 2 files changed, 13 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index 2215fe93cf..2f0df65582 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -218,6 +218,14 @@ void enable_caches(void) } #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ + +uint get_svr(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + return in_be32(&gur->svr); +} + #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 1bcdf04dd4..c12706d908 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -11,6 +11,8 @@ #define SVR_MIN(svr) (((svr) >> 0) & 0xf) #define SVR_SOC_VER(svr) (((svr) >> 8) & 0x7ff) #define IS_E_PROCESSOR(svr) (svr & 0x80000) +#define IS_SVR_REV(svr, maj, min) \ + ((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min)) #define SOC_VER_SLS1020 0x00 #define SOC_VER_LS1020 0x10 @@ -422,4 +424,7 @@ struct ccsr_ahci { u32 pberr; /* port 0/1 BIST error */ u32 cmds; /* port 0/1 CMD status error */ }; + +uint get_svr(void); + #endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */ -- cgit v1.2.1 From a07bdad749ea080e009a82ba40e791dc7361ab54 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Fri, 20 Nov 2015 15:52:03 +0800 Subject: fsl/errata: move fsl_errata.h to common directory move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h to make it public for both ARM and POWER SoCs. Signed-off-by: Shengzhou Liu [York Sun: fix soc.h path in fsl_errata.h] Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 2 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +- arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 2 +- arch/powerpc/include/asm/fsl_errata.h | 53 -------------------------- 4 files changed, 3 insertions(+), 56 deletions(-) delete mode 100644 arch/powerpc/include/asm/fsl_errata.h (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index b368562a24..a4935567f6 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -7,7 +7,7 @@ #include #include #include -#include +#include #include #include #include "fsl_corenet_serdes.h" diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 4cf8853b72..13a7d0f664 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index acb1353e5d..f89c94e7b3 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include "fsl_corenet2_serdes.h" #ifdef CONFIG_SYS_FSL_SRDS_1 diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h deleted file mode 100644 index 4861e3bf8d..0000000000 --- a/arch/powerpc/include/asm/fsl_errata.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_FSL_ERRATA_H -#define _ASM_FSL_ERRATA_H - -#include -#include - -#ifdef CONFIG_SYS_FSL_ERRATUM_A006379 -static inline bool has_erratum_a006379(void) -{ - u32 svr = get_svr(); - if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) || - ((SVR_SOC_VER(svr) == SVR_T4160) && SVR_MAJ(svr) <= 1) || - ((SVR_SOC_VER(svr) == SVR_T4080) && SVR_MAJ(svr) <= 1) || - ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2) || - ((SVR_SOC_VER(svr) == SVR_B4420) && SVR_MAJ(svr) <= 2) || - ((SVR_SOC_VER(svr) == SVR_T2080) && SVR_MAJ(svr) <= 1) || - ((SVR_SOC_VER(svr) == SVR_T2081) && SVR_MAJ(svr) <= 1)) - return true; - - return false; -} -#endif -#endif - -#ifdef CONFIG_SYS_FSL_ERRATUM_A007186 -static inline bool has_erratum_a007186(void) -{ - u32 svr = get_svr(); - u32 soc = SVR_SOC_VER(svr); - - switch (soc) { - case SVR_T4240: - return IS_SVR_REV(svr, 2, 0); - case SVR_T4160: - return IS_SVR_REV(svr, 2, 0); - case SVR_B4860: - return IS_SVR_REV(svr, 2, 0); - case SVR_B4420: - return IS_SVR_REV(svr, 2, 0); - case SVR_T2081: - case SVR_T2080: - return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1); - } - - return false; -} -#endif -- cgit v1.2.1 From a46b1852de967f8a7de26e0b46e864c794a18c16 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Fri, 20 Nov 2015 15:52:04 +0800 Subject: fsl/ddr: updated ddr errata-A008378 for arm and power SoCs DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0, T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on LS102x Rev2. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- arch/powerpc/include/asm/config_mpc85xx.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 7a5487be88..674fac8828 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -807,6 +807,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 #define CONFIG_SYS_FSL_SFP_VER_3_0 +#define CONFIG_SYS_FSL_ERRATUM_A008378 #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) @@ -854,6 +855,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 #define CONFIG_SYS_FSL_SFP_VER_3_0 +#define CONFIG_SYS_FSL_ERRATUM_A008378 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define CONFIG_E6500 -- cgit v1.2.1 From e994dddbbe031c818758b2ea91f59697b07d94b6 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Mon, 23 Nov 2015 15:23:48 +0800 Subject: armv8/ls1043ardb: Add support for >2GB memory This patch also expose the complete DDR region(s) to Linux. Signed-off-by: Shaohui Xie Signed-off-by: Mingkai Hu Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index b5a2d28c08..7217a87502 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -126,8 +126,8 @@ #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */ #define CONFIG_SYS_FSL_DDR_BE -#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE #define CONFIG_SYS_FSL_CCSR_GUR_BE #define CONFIG_SYS_FSL_CCSR_SCFG_BE -- cgit v1.2.1 From 1a338921642bf622230d91e5eb16b8b5250b44a5 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 28 Nov 2015 08:04:41 -0500 Subject: fsl_*_serdes.c: Modify memset call in serdes_init GCC 5.x does not like sizeof(array_variable) and errors out. Change these calls to be instead sizeof(u8) (as that's what serdes_prtcl_map is) * SERDES_PRCTL_COUNT (the number of array elements). Cc: York Sun Signed-off-by: Tom Rini Reviewed-by: Bin Meng Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 2 +- arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c index f7178d1470..fe3444a91e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c @@ -86,7 +86,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, u32 cfg; int lane; - memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map)); + memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT); cfg = gur_in32(&gur->rcwsr[4]) & sd_prctl_mask; cfg >>= sd_prctl_shift; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index 918e889052..be6acc63fe 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -79,7 +79,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, u32 cfg; int lane; - memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map)); + memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT); cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask; cfg >>= sd_prctl_shift; diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index f89c94e7b3..9920839d68 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -184,7 +184,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, u32 cfg; int lane; - memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map)); + memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT); #ifdef CONFIG_SYS_FSL_ERRATUM_A007186 struct ccsr_sfp_regs __iomem *sfp_regs = (struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR); -- cgit v1.2.1 From 7ba0261810dd8924f0aeeb4cf2f12253106170b3 Mon Sep 17 00:00:00 2001 From: Yao Yuan Date: Sat, 5 Dec 2015 14:59:10 +0800 Subject: arm: ls1021a: merge SoC specific code in a separate file Create a soc.c file to put the code for soc special settings. Signed-off-by: Yuan Yao Reviewed-by: York Sun --- arch/arm/cpu/armv7/ls102xa/Makefile | 1 + arch/arm/cpu/armv7/ls102xa/soc.c | 66 +++++++++++++++++++++++++ arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h | 12 +++++ 3 files changed, 79 insertions(+) create mode 100644 arch/arm/cpu/armv7/ls102xa/soc.c create mode 100644 arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h (limited to 'arch') diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile index 2311468ac9..02283009ab 100644 --- a/arch/arm/cpu/armv7/ls102xa/Makefile +++ b/arch/arm/cpu/armv7/ls102xa/Makefile @@ -8,6 +8,7 @@ obj-y += cpu.o obj-y += clock.o obj-y += timer.o obj-y += fsl_epu.o +obj-y += soc.o obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o obj-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c new file mode 100644 index 0000000000..0fdd6d4c86 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -0,0 +1,66 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +unsigned int get_soc_major_rev(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int svr, major; + + svr = in_be32(&gur->svr); + major = SVR_MAJ(svr); + + return major; +} + +int arch_soc_init(void) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + unsigned int major; + +#ifdef CONFIG_FSL_QSPI + out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); +#endif + +#ifdef CONFIG_FSL_DCU_FB + out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); +#endif + + /* Configure Little endian for SAI, ASRC and SPDIF */ + out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); + + /* + * Enable snoop requests and DVM message requests for + * Slave insterface S4 (A7 core cluster) + */ + out_le32(&cci->slave[4].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); + + major = get_soc_major_rev(); + if (major == SOC_MAJOR_VER_1_0) { + /* + * Set CCI-400 Slave interface S1, S2 Shareable Override + * Register All transactions are treated as non-shareable + */ + out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + + /* Workaround for the issue that DDR could not respond to + * barrier transaction which is generated by executing DSB/ISB + * instruction. Set CCI-400 control override register to + * terminate the barrier transaction. After DDR is initialized, + * allow barrier transaction to DDR again */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); + } + + return 0; +} diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h new file mode 100644 index 0000000000..f10cb91f4b --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h @@ -0,0 +1,12 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_LS102XA_SOC_H +#define __FSL_LS102XA_SOC_H + +unsigned int get_soc_major_rev(void); +int arch_soc_init(void); +#endif /* __FSL_LS102XA_SOC_H */ -- cgit v1.2.1 From 762b3535467202ee216dce81f13eec42cd2ac2e3 Mon Sep 17 00:00:00 2001 From: Yao Yuan Date: Sat, 5 Dec 2015 14:59:11 +0800 Subject: arm: ls102xa: enable all the snoop signal for masters. Enable the IP feature's snoop signal to support hardware snoop for cache coherence. SNPCNFGCR contains the bits to drive snoop signal for various masters. Signed-off-by: Yuan Yao Reviewed-by: York Sun --- arch/arm/cpu/armv7/ls102xa/soc.c | 8 ++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 6 ++++++ 2 files changed, 14 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 0fdd6d4c86..6036473a50 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -62,5 +62,13 @@ int arch_soc_init(void) out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); } + /* Enable all the snoop signal for various masters */ + out_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR | + SCFG_SNPCNFGCR_DCU_RD_WR | + SCFG_SNPCNFGCR_SATA_RD_WR | + SCFG_SNPCNFGCR_USB3_RD_WR | + SCFG_SNPCNFGCR_DBG_RD_WR | + SCFG_SNPCNFGCR_EDMA_SNP); + return 0; } diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index c12706d908..931727275c 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -152,6 +152,12 @@ struct ccsr_gur { #define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 #define SCFG_PIXCLKCR_PXCKEN 0x80000000 #define SCFG_QSPI_CLKSEL 0xc0100000 +#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 +#define SCFG_SNPCNFGCR_DCU_RD_WR 0x03000000 +#define SCFG_SNPCNFGCR_SATA_RD_WR 0x00c00000 +#define SCFG_SNPCNFGCR_USB3_RD_WR 0x00300000 +#define SCFG_SNPCNFGCR_DBG_RD_WR 0x000c0000 +#define SCFG_SNPCNFGCR_EDMA_SNP 0x00020000 #define SCFG_ENDIANCR_LE 0x80000000 /* Supplemental Configuration Unit */ -- cgit v1.2.1 From 0b8bc6314e1abc4379cc00f93f949257e0b1b196 Mon Sep 17 00:00:00 2001 From: Yao Yuan Date: Sat, 5 Dec 2015 14:59:12 +0800 Subject: armv7: ls102xa: cci-400: Enable snoop and DVM message requests. Enable snoop and DVM message on all CCI-400 slave ports. Setting on disabled feature (snoop or DVM) is ignored by CCI-400. Signed-off-by: Yuan Yao [York Sun: Add commit message] Reviewed-by: York Sun --- arch/arm/cpu/armv7/ls102xa/soc.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 6036473a50..97ba6d5179 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -40,8 +40,14 @@ int arch_soc_init(void) /* * Enable snoop requests and DVM message requests for - * Slave insterface S4 (A7 core cluster) + * All the slave insterfaces. */ + out_le32(&cci->slave[0].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); + out_le32(&cci->slave[1].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); + out_le32(&cci->slave[2].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); out_le32(&cci->slave[4].snoop_ctrl, CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); -- cgit v1.2.1 From 6c4a1eba3fcc013f7d21cdb88098bdd3e7afa75b Mon Sep 17 00:00:00 2001 From: Yao Yuan Date: Sat, 5 Dec 2015 14:59:13 +0800 Subject: armv7/fsl-ls102xa: Workaround for DDR erratum A008514 This is a workaround for hardware erratum. Write the value of 63b2_0042h to EDDRTQCFG will optimal the memory controller performance. The value: 63b2_0042h comes from the hardware team. Signed-off-by: Yuan Yao Reviewed-by: York Sun --- arch/arm/cpu/armv7/ls102xa/soc.c | 10 ++++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 97ba6d5179..79ae883b13 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -76,5 +76,15 @@ int arch_soc_init(void) SCFG_SNPCNFGCR_DBG_RD_WR | SCFG_SNPCNFGCR_EDMA_SNP); + /* + * Memory controller require a register write before being enabled. + * Affects: DDR + * Register: EDDRTQCFG + * Description: Memory controller performance is not optimal with + * default internal target queue register values. + * Workaround: Write a value of 63b2_0042h to address: 157_020Ch. + */ + out_be32(&scfg->eddrtqcfg, 0x63b20042); + return 0; } diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 931727275c..89339fe0ef 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -230,7 +230,7 @@ struct ccsr_scfg { u32 scfgrevcr; u32 coresrencr; u32 pex2pmrdsr; - u32 ddrc1cr; + u32 eddrtqcfg; u32 ddrc2cr; u32 ddrc3cr; u32 ddrc4cr; -- cgit v1.2.1 From 000f4e7686f4291fbd74d8920b586caf10f9241f Mon Sep 17 00:00:00 2001 From: Yao Yuan Date: Sat, 5 Dec 2015 14:59:14 +0800 Subject: move erratum a008336 and a008514 to soc specific file As the errata A008336 and A008514 do not apply to all LS series SoCs (such as LS1021A, LS1043A) we move them to an soc specific file Signed-off-by: Yuan Yao Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 37 +++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 8896b70e78..a0de4becd1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -14,6 +14,41 @@ DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +/* + * This erratum requires setting a value to eddrtqcr1 to + * optimal the DDR performance. + */ +static void erratum_a008336(void) +{ + u32 *eddrtqcr1; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008336 +#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR + eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; + out_le32(eddrtqcr1, 0x63b30002); +#endif +#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR + eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; + out_le32(eddrtqcr1, 0x63b30002); +#endif +#endif +} + +/* + * This erratum requires a register write before being Memory + * controller 3 being enabled. + */ +static void erratum_a008514(void) +{ + u32 *eddrtqcr1; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008514 +#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR + eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; + out_le32(eddrtqcr1, 0x63b20002); +#endif +#endif +} #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val" @@ -118,6 +153,8 @@ void fsl_lsch3_early_init_f(void) erratum_rcw_src(); init_early_memctl_regs(); /* tighten IFC timing */ erratum_a009203(); + erratum_a008514(); + erratum_a008336(); } #elif defined(CONFIG_LS1043A) -- cgit v1.2.1 From c107c0c05c988ac6cfba6de60c90f105bbea0e1e Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 4 Dec 2015 11:57:08 -0800 Subject: armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 121 +++++++++++++++++++--- arch/arm/include/asm/arch-fsl-layerscape/config.h | 6 ++ arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 14 ++- 3 files changed, 122 insertions(+), 19 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 8847fc0287..87ccaf166f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -206,11 +206,65 @@ static inline void early_mmu_setup(void) set_sctlr(get_sctlr() | CR_M); } +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +/* + * Called from final mmu setup. The phys_addr is new, non-existing + * address. A new sub table is created @level2_table_secure to cover + * size of CONFIG_SYS_MEM_RESERVE_SECURE memory. + */ +static inline int final_secure_ddr(u64 *level0_table, + u64 *level2_table_secure, + phys_addr_t phys_addr) +{ + int ret = -EINVAL; + struct table_info table = {}; + struct sys_mmu_table ddr_entry = { + 0, 0, BLOCK_SIZE_L1, MT_NORMAL, + PMD_SECT_OUTER_SHARE | PMD_SECT_NS + }; + u64 index; + + /* Need to create a new table */ + ddr_entry.virt_addr = phys_addr & ~(BLOCK_SIZE_L1 - 1); + ddr_entry.phys_addr = phys_addr & ~(BLOCK_SIZE_L1 - 1); + ret = find_table(&ddr_entry, &table, level0_table); + if (ret) + return ret; + index = (ddr_entry.virt_addr - table.table_base) >> SECTION_SHIFT_L1; + set_pgtable_table(table.ptr, index, level2_table_secure); + table.ptr = level2_table_secure; + table.table_base = ddr_entry.virt_addr; + table.entry_size = BLOCK_SIZE_L2; + ret = set_block_entry(&ddr_entry, &table); + if (ret) { + printf("MMU error: could not fill non-secure ddr block entries\n"); + return ret; + } + ddr_entry.virt_addr = phys_addr; + ddr_entry.phys_addr = phys_addr; + ddr_entry.size = CONFIG_SYS_MEM_RESERVE_SECURE; + ddr_entry.attribute = PMD_SECT_OUTER_SHARE; + ret = find_table(&ddr_entry, &table, level0_table); + if (ret) { + printf("MMU error: could not find secure ddr table\n"); + return ret; + } + ret = set_block_entry(&ddr_entry, &table); + if (ret) + printf("MMU error: could not set secure ddr block entry\n"); + + return ret; +} +#endif + /* * The final tables look similar to early tables, but different in detail. * These tables are in DRAM. Sub tables are added to enable cache for * QBMan and OCRAM. * + * Put the MMU table in secure memory if gd->secure_ram is valid. + * OCRAM will be not used for this purpose so gd->secure_ram can't be 0. + * * Level 1 table 0 contains 512 entries for each 1GB from 0 to 512GB. * Level 1 table 1 contains 512 entries for each 1GB from 512GB to 1TB. * Level 2 table 0 contains 512 entries for each 2MB from 0 to 1GB. @@ -223,18 +277,40 @@ static inline void early_mmu_setup(void) */ static inline void final_mmu_setup(void) { - unsigned int el, i; + unsigned int el = current_el(); + unsigned int i; u64 *level0_table = (u64 *)gd->arch.tlb_addr; - u64 *level1_table0 = (u64 *)(gd->arch.tlb_addr + 0x1000); - u64 *level1_table1 = (u64 *)(gd->arch.tlb_addr + 0x2000); - u64 *level2_table0 = (u64 *)(gd->arch.tlb_addr + 0x3000); -#ifdef CONFIG_FSL_LSCH3 - u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000); -#elif defined(CONFIG_FSL_LSCH2) - u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000); - u64 *level2_table2 = (u64 *)(gd->arch.tlb_addr + 0x5000); + u64 *level1_table0; + u64 *level1_table1; + u64 *level2_table0; + u64 *level2_table1; +#ifdef CONFIG_FSL_LSCH2 + u64 *level2_table2; #endif - struct table_info table = {level0_table, 0, BLOCK_SIZE_L0}; + struct table_info table = {NULL, 0, BLOCK_SIZE_L0}; + +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + u64 *level2_table_secure; + + if (el == 3) { + /* + * Only use gd->secure_ram if the address is recalculated + * Align to 4KB for MMU table + */ + if (gd->secure_ram & MEM_RESERVE_SECURE_MAINTAINED) + level0_table = (u64 *)(gd->secure_ram & ~0xfff); + else + printf("MMU warning: gd->secure_ram is not maintained, disabled.\n"); + } +#endif + level1_table0 = level0_table + 512; + level1_table1 = level1_table0 + 512; + level2_table0 = level1_table1 + 512; + level2_table1 = level2_table0 + 512; +#ifdef CONFIG_FSL_LSCH2 + level2_table2 = level2_table1 + 512; +#endif + table.ptr = level0_table; /* Invalidate all table entries */ memset(level0_table, 0, PGTABLE_SIZE); @@ -269,17 +345,34 @@ static inline void final_mmu_setup(void) &final_mmu_table[i]); } } + /* Set the secure memory to secure in MMU */ +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + if (el == 3 && gd->secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { +#ifdef CONFIG_FSL_LSCH3 + level2_table_secure = level2_table1 + 512; +#elif defined(CONFIG_FSL_LSCH2) + level2_table_secure = level2_table2 + 512; +#endif + if (!final_secure_ddr(level0_table, + level2_table_secure, + gd->secure_ram & ~0x3)) { + gd->secure_ram |= MEM_RESERVE_SECURE_SECURED; + debug("Now MMU table is in secured memory at 0x%llx\n", + gd->secure_ram & ~0x3); + } else { + printf("MMU warning: Failed to secure DDR\n"); + } + } +#endif /* flush new MMU table */ - flush_dcache_range(gd->arch.tlb_addr, - gd->arch.tlb_addr + gd->arch.tlb_size); + flush_dcache_range((ulong)level0_table, + (ulong)level0_table + gd->arch.tlb_size); #ifdef CONFIG_SYS_DPAA_FMAN flush_dcache_all(); #endif /* point TTBR to the new table */ - el = current_el(); - set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR_FINAL, MEMORY_ATTRIBUTES); /* diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 7217a87502..b39281260d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -17,6 +17,12 @@ #define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 +/* + * Reserve secure memory + * To be aligned with MMU block size + */ +#define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */ + #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) #define CONFIG_MAX_CPUS 16 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 454409488a..e030430786 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -129,7 +129,8 @@ static const struct sys_mmu_table early_mmu_table[] = { { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, + PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, @@ -138,7 +139,8 @@ static const struct sys_mmu_table early_mmu_table[] = { CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, + PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, #elif defined(CONFIG_FSL_LSCH2) { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, @@ -165,7 +167,8 @@ static const struct sys_mmu_table final_mmu_table[] = { { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, + PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, @@ -183,7 +186,7 @@ static const struct sys_mmu_table final_mmu_table[] = { /* For QBMAN portal, only the first 64MB is cache-enabled */ { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, - PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN | PMD_SECT_NS }, { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, @@ -212,7 +215,8 @@ static const struct sys_mmu_table final_mmu_table[] = { CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, + PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, #elif defined(CONFIG_FSL_LSCH2) { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE, -- cgit v1.2.1 From c04921414c087e15f8fa82d808a25e9338a7e8d5 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 7 Dec 2015 11:08:58 -0800 Subject: armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 87ccaf166f..6ea28ed5cb 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -636,3 +636,24 @@ void reset_cpu(ulong addr) val |= 0x02; scfg_out32(rstcr, val); } + +phys_size_t board_reserve_ram_top(phys_size_t ram_size) +{ + phys_size_t ram_top = ram_size; + +#ifdef CONFIG_SYS_MEM_TOP_HIDE +#error CONFIG_SYS_MEM_TOP_HIDE not to be used together with this function +#endif +/* Carve the Debug Server private DRAM block from the end of DRAM */ +#ifdef CONFIG_FSL_DEBUG_SERVER + ram_top -= debug_server_get_dram_block_size(); +#endif + +/* Carve the MC private DRAM block from the end of DRAM */ +#ifdef CONFIG_FSL_MC_ENET + ram_top -= mc_get_dram_block_size(); + ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1); +#endif + + return ram_top; +} -- cgit v1.2.1 From b644d3e932f133bbb8b577c1965eae399b7df99e Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Tue, 8 Dec 2015 13:54:26 +0530 Subject: armv8: define usec2ticks function usec2ticks() function has been defined for ARMv8 which will be used by SEC Driver. Signed-off-by: Aneesh Bansal Reviewed-by: York Sun --- arch/arm/cpu/armv8/generic_timer.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c index 8e60baebc5..8f47a82043 100644 --- a/arch/arm/cpu/armv8/generic_timer.c +++ b/arch/arm/cpu/armv8/generic_timer.c @@ -40,3 +40,14 @@ unsigned long timer_read_counter(void) #endif return cntpct; } + +unsigned long usec2ticks(unsigned long usec) +{ + ulong ticks; + if (usec < 1000) + ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000; + else + ticks = ((usec / 10) * (get_tbclk() / 100000)); + + return ticks; +} -- cgit v1.2.1 From 70f959c3c45bd408ba4f7b18a3a69afd9ccfe739 Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Tue, 8 Dec 2015 13:54:27 +0530 Subject: armv8: Make SEC read/write as snoopable for LS1043 For LS1043, SEC read/writes are made snoopable by setting the corresponding bits in SCFG to avoid coherency issues. Signed-off-by: Aneesh Bansal Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index a0de4becd1..8d40405923 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -161,11 +161,16 @@ void fsl_lsch3_early_init_f(void) void fsl_lsch2_early_init_f(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; #ifdef CONFIG_FSL_IFC init_early_memctl_regs(); /* tighten IFC timing */ #endif + /* Make SEC reads and writes snoopable */ + setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | + SCFG_SNPCNFGCR_SECWRSNP); + /* * Enable snoop requests and DVM message requests for * Slave insterface S4 (A53 core cluster) -- cgit v1.2.1 From 9711f52806655bcfa28fe5594b91fed430beb72e Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Tue, 8 Dec 2015 13:54:29 +0530 Subject: armv8/ls1043ardb: add SECURE BOOT target for NOR LS1043ARDB Secure Boot Target from NOR has been added. - Configs defined to enable esbc_validate. - ESBC Address in header is made 64 bit. - SMMU is re-configured in Bypass mode. Signed-off-by: Aneesh Bansal Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 ++-- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 +- arch/arm/include/asm/fsl_secure_boot.h | 6 +++++- 3 files changed, 8 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index b39281260d..6e5224ea1c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -153,8 +153,8 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_SFP_VER_3_2 -#define CONFIG_SYS_FSL_SNVS_LE -#define CONFIG_SYS_FSL_SEC_LE +#define CONFIG_SYS_FSL_SEC_MON_BE +#define CONFIG_SYS_FSL_SEC_BE #define CONFIG_SYS_FSL_SFP_BE #define CONFIG_SYS_FSL_SRK_LE #define CONFIG_KEY_REVOCATION diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 83caa918bd..e7def3ac4a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -38,7 +38,7 @@ #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) #define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) -#define CONFIG_SYS_SNVS_ADDR (CONFIG_SYS_IMMR + 0xe90000) +#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) #define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000 diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index f2d4c3c5f9..806302bc61 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -11,13 +11,17 @@ #define CONFIG_CMD_ESBC_VALIDATE #define CONFIG_FSL_SEC_MON #define CONFIG_SHA_PROG_HW_ACCEL -#define CONFIG_DM #define CONFIG_RSA #define CONFIG_RSA_FREESCALE_EXP + #ifndef CONFIG_FSL_CAAM #define CONFIG_FSL_CAAM #endif +#ifndef CONFIG_DM +#define CONFIG_DM +#endif + #define CONFIG_KEY_REVOCATION #ifndef CONFIG_SYS_RAMBOOT /* The key used for verification of next level images -- cgit v1.2.1 From 989c5f0a8f8694ac92eb0d6cff8745ae8659364f Mon Sep 17 00:00:00 2001 From: Tang Yuantian Date: Wed, 9 Dec 2015 15:32:18 +0800 Subject: armv8: Add sata support on Layerscape ARMv8 board Freescale ARM-based Layerscape contains a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls2080aqds, ls2080ardb and ls1043aqds boards. Signed-off-by: Tang Yuantian Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 43 ++++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 ++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 31 ++++++++++++++++ 3 files changed, 78 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 8d40405923..984eaf903e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -6,6 +6,8 @@ #include #include +#include +#include #include #include #include @@ -157,7 +159,44 @@ void fsl_lsch3_early_init_f(void) erratum_a008336(); } +#ifdef CONFIG_SCSI_AHCI_PLAT +int sata_init(void) +{ + struct ccsr_ahci __iomem *ccsr_ahci; + + ccsr_ahci = (void *)CONFIG_SYS_SATA2; + out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); + out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); + + ccsr_ahci = (void *)CONFIG_SYS_SATA1; + out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); + out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); + + ahci_init((void __iomem *)CONFIG_SYS_SATA1); + scsi_scan(0); + + return 0; +} +#endif + #elif defined(CONFIG_LS1043A) +#ifdef CONFIG_SCSI_AHCI_PLAT +int sata_init(void) +{ + struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA; + + out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); + out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); + out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG); + out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); + + ahci_init((void __iomem *)CONFIG_SYS_SATA); + scsi_scan(0); + + return 0; +} +#endif + void fsl_lsch2_early_init_f(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; @@ -183,6 +222,10 @@ void fsl_lsch2_early_init_f(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { +#ifdef CONFIG_SCSI_AHCI_PLAT + sata_init(); +#endif + return 0; } #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index cd96604171..91f3ce843a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -69,6 +69,10 @@ #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) +/* SATA */ +#define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000) +#define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000) + /* PCIe */ #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 504c1f9197..1565592996 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -51,6 +51,37 @@ struct cpu_type { #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) +/* ahci port register default value */ +#define AHCI_PORT_PHY_1_CFG 0xa003fffe +#define AHCI_PORT_PHY_2_CFG 0x28184d1f +#define AHCI_PORT_PHY_3_CFG 0x0e081509 +#define AHCI_PORT_TRANS_CFG 0x08000029 + +/* AHCI (sata) register map */ +struct ccsr_ahci { + u32 res1[0xa4/4]; /* 0x0 - 0xa4 */ + u32 pcfg; /* port config */ + u32 ppcfg; /* port phy1 config */ + u32 pp2c; /* port phy2 config */ + u32 pp3c; /* port phy3 config */ + u32 pp4c; /* port phy4 config */ + u32 pp5c; /* port phy5 config */ + u32 axicc; /* AXI cache control */ + u32 paxic; /* port AXI config */ + u32 axipc; /* AXI PROT control */ + u32 ptc; /* port Trans Config */ + u32 pts; /* port Trans Status */ + u32 plc; /* port link config */ + u32 plc1; /* port link config1 */ + u32 plc2; /* port link config2 */ + u32 pls; /* port link status */ + u32 pls1; /* port link status1 */ + u32 pcmdc; /* port CMD config */ + u32 ppcs; /* port phy control status */ + u32 pberr; /* port 0/1 BIST error */ + u32 cmds; /* port 0/1 CMD status error */ +}; + #ifdef CONFIG_FSL_LSCH3 void fsl_lsch3_early_init_f(void); #elif defined(CONFIG_FSL_LSCH2) -- cgit v1.2.1