From 48ef0d2a1002d3da0bf7ed13d0959bcbf782c792 Mon Sep 17 00:00:00 2001 From: Ruchika Gupta Date: Tue, 9 Sep 2014 11:50:30 +0530 Subject: fsl_sec : Move SEC CCSR definition to common include Freescale SEC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of SEC to common include Signed-off-by: Ruchika Gupta Reviewed-by: York Sun --- arch/powerpc/include/asm/immap_85xx.h | 67 +---------------------------------- 1 file changed, 1 insertion(+), 66 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index dfb370e051..e426314fdb 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -2675,72 +2676,6 @@ enum { FSL_SRDS_B3_LANE_D = 23, }; -/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */ -#if CONFIG_SYS_FSL_SEC_COMPAT >= 4 -typedef struct ccsr_sec { - u32 res0; - u32 mcfgr; /* Master CFG Register */ - u8 res1[0x8]; - struct { - u32 ms; /* Job Ring LIODN Register, MS */ - u32 ls; /* Job Ring LIODN Register, LS */ - } jrliodnr[4]; - u8 res2[0x30]; - struct { - u32 ms; /* RTIC LIODN Register, MS */ - u32 ls; /* RTIC LIODN Register, LS */ - } rticliodnr[4]; - u8 res3[0x1c]; - u32 decorr; /* DECO Request Register */ - struct { - u32 ms; /* DECO LIODN Register, MS */ - u32 ls; /* DECO LIODN Register, LS */ - } decoliodnr[8]; - u8 res4[0x40]; - u32 dar; /* DECO Avail Register */ - u32 drr; /* DECO Reset Register */ - u8 res5[0xe78]; - u32 crnr_ms; /* CHA Revision Number Register, MS */ - u32 crnr_ls; /* CHA Revision Number Register, LS */ - u32 ctpr_ms; /* Compile Time Parameters Register, MS */ - u32 ctpr_ls; /* Compile Time Parameters Register, LS */ - u8 res6[0x10]; - u32 far_ms; /* Fault Address Register, MS */ - u32 far_ls; /* Fault Address Register, LS */ - u32 falr; /* Fault Address LIODN Register */ - u32 fadr; /* Fault Address Detail Register */ - u8 res7[0x4]; - u32 csta; /* CAAM Status Register */ - u8 res8[0x8]; - u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/ - u32 ccbvid; /* CHA Cluster Block Version ID Register */ - u32 chavid_ms; /* CHA Version ID Register, MS */ - u32 chavid_ls; /* CHA Version ID Register, LS */ - u32 chanum_ms; /* CHA Number Register, MS */ - u32 chanum_ls; /* CHA Number Register, LS */ - u32 secvid_ms; /* SEC Version ID Register, MS */ - u32 secvid_ls; /* SEC Version ID Register, LS */ - u8 res9[0x6020]; - u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */ - u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */ - u8 res10[0x8fd8]; -} ccsr_sec_t; - -#define SEC_CTPR_MS_AXI_LIODN 0x08000000 -#define SEC_CTPR_MS_QI 0x02000000 -#define SEC_RVID_MA 0x0f000000 -#define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000 -#define SEC_CHANUM_MS_JRNUM_SHIFT 28 -#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000 -#define SEC_CHANUM_MS_DECONUM_SHIFT 24 -#define SEC_SECVID_MS_IPID_MASK 0xffff0000 -#define SEC_SECVID_MS_IPID_SHIFT 16 -#define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00 -#define SEC_SECVID_MS_MAJ_REV_SHIFT 8 -#define SEC_CCBVID_ERA_MASK 0xff000000 -#define SEC_CCBVID_ERA_SHIFT 24 -#endif - typedef struct ccsr_qman { #ifdef CONFIG_SYS_FSL_QMAN_V3 u8 res0[0x200]; -- cgit v1.2.1 From 028dbb8db1d18c5835ab34659f9ef7a516571524 Mon Sep 17 00:00:00 2001 From: Ruchika Gupta Date: Tue, 9 Sep 2014 11:50:31 +0530 Subject: fsl_sec : Change accessor function to take care of endianness SEC registers can be of type Little Endian or big Endian depending upon Freescale SoC. Here SoC defines the register type of SEC IP. So update acessor functions with common SEC acessor functions to take care both type of endianness. Signed-off-by: Ruchika Gupta Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +- arch/powerpc/cpu/mpc85xx/fdt.c | 2 +- arch/powerpc/cpu/mpc85xx/liodn.c | 4 ++-- arch/powerpc/cpu/mpc8xxx/fdt.c | 4 ++-- arch/powerpc/include/asm/config_mpc85xx.h | 1 + 5 files changed, 7 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 5bfab70b7e..bf9fbbf1da 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -803,7 +803,7 @@ int cpu_init_r(void) #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 #define MCFGR_AXIPIPE 0x000000f0 if (IS_SVR_REV(svr, 1, 0)) - clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE); + sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE); #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 3222e26a5a..d4c3d9df9b 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -714,7 +714,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) ccsr_sec_t __iomem *sec; sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; - fdt_fixup_crypto_node(blob, in_be32(&sec->secvid_ms)); + fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); } #endif diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index 19e130e87f..7a2d4be42c 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -66,12 +66,12 @@ static void setup_sec_liodn_base(void) return; /* QILCR[QSLOM] */ - out_be32(&sec->qilcr_ms, 0x3ff<<16); + sec_out32(&sec->qilcr_ms, 0x3ff<<16); base = (liodn_bases[FSL_HW_PORTAL_SEC].id[0] << 16) | liodn_bases[FSL_HW_PORTAL_SEC].id[1]; - out_be32(&sec->qilcr_ls, base); + sec_out32(&sec->qilcr_ls, base); } #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 4cec5e118f..c6b4d95549 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -287,8 +287,8 @@ static u8 caam_get_era(void) }; ccsr_sec_t __iomem *sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; - u32 secvid_ms = in_be32(&sec->secvid_ms); - u32 ccbvid = in_be32(&sec->ccbvid); + u32 secvid_ms = sec_in32(&sec->secvid_ms); + u32 ccbvid = sec_in32(&sec->ccbvid); u16 ip_id = (secvid_ms & SEC_SECVID_MS_IPID_MASK) >> SEC_SECVID_MS_IPID_SHIFT; u8 maj_rev = (secvid_ms & SEC_SECVID_MS_MAJ_REV_MASK) >> diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 712f2ef4b3..4c1774f503 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -24,6 +24,7 @@ /* IP endianness */ #define CONFIG_SYS_FSL_IFC_BE +#define CONFIG_SYS_FSL_SEC_BE /* Number of TLB CAM entries we have on FSL Book-E chips */ #if defined(CONFIG_E500MC) -- cgit v1.2.1 From b9eebfade974c86c8ddef64793649374c9876242 Mon Sep 17 00:00:00 2001 From: Ruchika Gupta Date: Wed, 15 Oct 2014 11:35:30 +0530 Subject: fsl_sec: Add hardware accelerated SHA256 and SHA1 SHA-256 and SHA-1 accelerated using SEC hardware in Freescale SoC's The driver for SEC (CAAM) IP is based on linux drivers/crypto/caam. The platforms needto add the MACRO CONFIG_FSL_CAAM inorder to enable initialization of this hardware IP. Signed-off-by: Ruchika Gupta Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 7 +++++++ arch/powerpc/include/asm/immap_85xx.h | 5 +++++ arch/powerpc/include/asm/types.h | 4 ++++ 3 files changed, 16 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index bf9fbbf1da..963e32676b 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -27,6 +27,9 @@ #include #include #include "mp.h" +#ifdef CONFIG_FSL_CAAM +#include +#endif #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND #include #include @@ -938,6 +941,10 @@ int cpu_init_r(void) fman_enet_init(); #endif +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) /* * For P1022/1013 Rev1.0 silicon, after power on SATA host diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index e426314fdb..88c1e08df5 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2875,6 +2875,7 @@ struct ccsr_sfp_regs { #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000 #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000 +#define CONFIG_SYS_FSL_JR0_OFFSET 0x301000 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000 @@ -2935,8 +2936,10 @@ struct ccsr_sfp_regs { #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 #if defined(CONFIG_PPC_C29X) #define CONFIG_SYS_FSL_SEC_OFFSET 0x80000 +#define CONFIG_SYS_FSL_JR0_OFFSET 0x81000 #else #define CONFIG_SYS_FSL_SEC_OFFSET 0x30000 +#define CONFIG_SYS_FSL_JR0_OFFSET 0x31000 #endif #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 @@ -3041,6 +3044,8 @@ struct ccsr_sfp_regs { (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET) #define CONFIG_SYS_FSL_SEC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) +#define CONFIG_SYS_FSL_JR0_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) #define CONFIG_SYS_FSL_FM1_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET) #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \ diff --git a/arch/powerpc/include/asm/types.h b/arch/powerpc/include/asm/types.h index b27a6b753a..b29ce792f7 100644 --- a/arch/powerpc/include/asm/types.h +++ b/arch/powerpc/include/asm/types.h @@ -41,8 +41,12 @@ typedef unsigned long long u64; #define BITS_PER_LONG 32 +#ifdef CONFIG_PHYS_64BIT +typedef unsigned long long dma_addr_t; +#else /* DMA addresses are 32-bits wide */ typedef u32 dma_addr_t; +#endif #ifdef CONFIG_PHYS_64BIT typedef unsigned long long phys_addr_t; -- cgit v1.2.1 From 4ba4a095da4f7d38270ee22cc1a1ce64fa47d009 Mon Sep 17 00:00:00 2001 From: Ruchika Gupta Date: Wed, 15 Oct 2014 11:39:06 +0530 Subject: ls102x: configs - Add hash command in freescale LS1 platforms Hardware accelerated support for SHA-1 and SHA-256 has been added. Hash command enabled along with hardware accelerated support for SHA-1 and SHA-256 for platforms which have CAAM block. Signed-off-by: Ruchika Gupta Reviewed-by: York Sun --- arch/arm/include/asm/arch-ls102xa/config.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index a500b5bc3b..f2c9687df4 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -19,6 +19,8 @@ #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) +#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) +#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) #define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) @@ -66,6 +68,7 @@ #define CONFIG_SYS_FSL_DSPI_BE #define CONFIG_SYS_FSL_QSPI_BE #define CONFIG_SYS_FSL_DCU_BE +#define CONFIG_SYS_FSL_SEC_LE #define DCU_LAYER_MAX_NUM 16 @@ -76,6 +79,7 @@ #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 +#define CONFIG_SYS_FSL_SEC_COMPAT 5 #else #error SoC not defined #endif -- cgit v1.2.1 From 7cad2e38d61e27ea59fb7944f7e647e97ef292d3 Mon Sep 17 00:00:00 2001 From: Ruchika Gupta Date: Mon, 29 Sep 2014 11:35:33 +0530 Subject: powerpc/mpc85xx: SECURE BOOT - Bypass PAMU in case of secure boot By default, PAMU's (IOMMU) are enabled in case of secure boot. Disable/bypass them once the control reaches the bootloader. For non-secure boot, PAMU's are already bypassed in the default SoC configuration. Signed-off-by: Ruchika Gupta Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 9 ++++++++- arch/powerpc/include/asm/immap_85xx.h | 1 + 2 files changed, 9 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 963e32676b..85d32fc612 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -426,7 +426,8 @@ ulong cpu_init_f(void) { ulong flag = 0; extern void m8560_cpm_reset (void); -#ifdef CONFIG_SYS_DCSRBAR_PHYS +#if defined(CONFIG_SYS_DCSRBAR_PHYS) || \ + (defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif #if defined(CONFIG_SECURE_BOOT) @@ -458,6 +459,12 @@ ulong cpu_init_f(void) #if defined(CONFIG_SYS_CPC_REINIT_F) disable_cpc_sram(); #endif + +#if defined(CONFIG_FSL_CORENET) + /* Put PAMU in bypass mode */ + out_be32(&gur->pamubypenr, FSL_CORENET_PAMU_BYPASS); +#endif + #endif #ifdef CONFIG_CPM2 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 88c1e08df5..0264523d64 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1912,6 +1912,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) u8 res24[64]; u32 pblsr; /* Preboot loader status */ u32 pamubypenr; /* PAMU bypass enable */ +#define FSL_CORENET_PAMU_BYPASS 0xffff0000 u32 dmacr1; /* DMA control */ u8 res25[4]; u32 gensr1; /* General status */ -- cgit v1.2.1