From 06f60ae3e454e15a410a0d4e96769bf938af8fcb Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Thu, 6 Dec 2012 13:33:17 +0000 Subject: powerpc/mpc83xx: add support for new SPL This adds arch support for PPC mpc83xx to boot "minimal" (4K) SPLs using the new infrastructure. Existing nand_spl targets are updated to deal with the name change from nand_init.c to spl_minimal.c (as in theory this isn't limited to NAND anymore). Signed-off-by: Scott Wood Signed-off-by: Kim Phillips --- arch/powerpc/cpu/mpc83xx/Makefile | 16 +++++ arch/powerpc/cpu/mpc83xx/nand_init.c | 112 -------------------------------- arch/powerpc/cpu/mpc83xx/spl_minimal.c | 112 ++++++++++++++++++++++++++++++++ arch/powerpc/cpu/mpc83xx/start.S | 31 +++++---- arch/powerpc/cpu/mpc83xx/u-boot-spl.lds | 55 ++++++++++++++++ arch/powerpc/lib/Makefile | 3 +- 6 files changed, 204 insertions(+), 125 deletions(-) delete mode 100644 arch/powerpc/cpu/mpc83xx/nand_init.c create mode 100644 arch/powerpc/cpu/mpc83xx/spl_minimal.c create mode 100644 arch/powerpc/cpu/mpc83xx/u-boot-spl.lds (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile index 687f5e90a4..8a470b84b8 100644 --- a/arch/powerpc/cpu/mpc83xx/Makefile +++ b/arch/powerpc/cpu/mpc83xx/Makefile @@ -27,8 +27,22 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).o +MINIMAL= + +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_INIT_MINIMAL +MINIMAL=y +endif +endif + START = start.o +ifdef MINIMAL + +COBJS-y += spl_minimal.o + +else + COBJS-y += traps.o COBJS-y += cpu.o COBJS-y += cpu_init.o @@ -51,6 +65,8 @@ COBJS-y += spd_sdram.o endif COBJS-$(CONFIG_FSL_DDR2) += law.o +endif # not minimal + COBJS := $(COBJS-y) SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix $(obj),$(COBJS_LN-y:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS_LN-y)) diff --git a/arch/powerpc/cpu/mpc83xx/nand_init.c b/arch/powerpc/cpu/mpc83xx/nand_init.c deleted file mode 100644 index d1648b7810..0000000000 --- a/arch/powerpc/cpu/mpc83xx/nand_init.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Breathe some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - * initialize the UPM's - */ -void cpu_init_f (volatile immap_t * im) -{ - int i; - - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - - /* Clear initial global data */ - for (i = 0; i < sizeof(gd_t); i++) - ((char *)gd)[i] = 0; - - /* system performance tweaking */ - -#ifdef CONFIG_SYS_ACR_PIPE_DEP - /* Arbiter pipeline depth */ - im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | - (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT); -#endif - -#ifdef CONFIG_SYS_ACR_RPTCNT - /* Arbiter repeat count */ - im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) | - (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT); -#endif - -#ifdef CONFIG_SYS_SPCR_OPT - /* Optimize transactions between CSB and other devices */ - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) | - (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT); -#endif - - /* Enable Time Base & Decrimenter (so we will have udelay()) */ - im->sysconf.spcr |= SPCR_TBEN; - - /* DDR control driver register */ -#ifdef CONFIG_SYS_DDRCDR - im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR; -#endif - /* Output buffer impedance register */ -#ifdef CONFIG_SYS_OBIR - im->sysconf.obir = CONFIG_SYS_OBIR; -#endif - - /* - * Memory Controller: - */ - - /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary - * addresses - these have to be modified later when FLASH size - * has been determined - */ - -#if defined(CONFIG_SYS_NAND_BR_PRELIM) \ - && defined(CONFIG_SYS_NAND_OR_PRELIM) \ - && defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \ - && defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM) - set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); - set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); - im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM; - im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM; -#else -#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined -#endif -} - -/* - * Get timebase clock frequency (like cpu_clk in Hz) - */ -unsigned long get_tbclk(void) -{ - return (gd->bus_clk + 3L) / 4L; -} - -void puts(const char *str) -{ - while (*str) - putc(*str++); -} diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c new file mode 100644 index 0000000000..d1648b7810 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c @@ -0,0 +1,112 @@ +/* + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Breathe some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f (volatile immap_t * im) +{ + int i; + + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); + + /* Clear initial global data */ + for (i = 0; i < sizeof(gd_t); i++) + ((char *)gd)[i] = 0; + + /* system performance tweaking */ + +#ifdef CONFIG_SYS_ACR_PIPE_DEP + /* Arbiter pipeline depth */ + im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | + (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT); +#endif + +#ifdef CONFIG_SYS_ACR_RPTCNT + /* Arbiter repeat count */ + im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) | + (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT); +#endif + +#ifdef CONFIG_SYS_SPCR_OPT + /* Optimize transactions between CSB and other devices */ + im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) | + (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT); +#endif + + /* Enable Time Base & Decrimenter (so we will have udelay()) */ + im->sysconf.spcr |= SPCR_TBEN; + + /* DDR control driver register */ +#ifdef CONFIG_SYS_DDRCDR + im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR; +#endif + /* Output buffer impedance register */ +#ifdef CONFIG_SYS_OBIR + im->sysconf.obir = CONFIG_SYS_OBIR; +#endif + + /* + * Memory Controller: + */ + + /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary + * addresses - these have to be modified later when FLASH size + * has been determined + */ + +#if defined(CONFIG_SYS_NAND_BR_PRELIM) \ + && defined(CONFIG_SYS_NAND_OR_PRELIM) \ + && defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \ + && defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM) + set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); + set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); + im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM; + im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM; +#else +#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined +#endif +} + +/* + * Get timebase clock frequency (like cpu_clk in Hz) + */ +unsigned long get_tbclk(void) +{ + return (gd->bus_clk + 3L) / 4L; +} + +void puts(const char *str) +{ + while (*str) + putc(*str++); +} diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index b70b4ca12c..44a64b7acd 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -58,7 +58,13 @@ #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) #endif -#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_NAND_SPL) || \ + (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)) +#define MINIMAL_SPL +#endif + +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \ + !defined(CONFIG_SYS_RAMBOOT) #define CONFIG_SYS_FLASHBOOT #endif @@ -72,7 +78,7 @@ GOT_ENTRY(__bss_start) GOT_ENTRY(__bss_end__) -#ifndef CONFIG_NAND_SPL +#ifndef MINIMAL_SPL GOT_ENTRY(_FIXUP_TABLE_) GOT_ENTRY(_start) GOT_ENTRY(_start_of_vectors) @@ -206,7 +212,8 @@ _start: /* time t 0 */ /* Initialise the E300 processor core */ /*------------------------------------------*/ -#ifdef CONFIG_NAND_SPL +#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \ + defined(CONFIG_NAND_SPL) /* The FCM begins execution after only the first page * is loaded. Wait for the rest before branching * to another flash page. @@ -292,7 +299,7 @@ in_flash: /* NOTREACHED - board_init_f() does not return */ -#ifndef CONFIG_NAND_SPL +#ifndef MINIMAL_SPL /* * Vector Table */ @@ -467,7 +474,7 @@ int_return: lwz r1,GPR1(r1) SYNC rfi -#endif /* !CONFIG_NAND_SPL */ +#endif /* !MINIMAL_SPL */ /* * This code initialises the E300 processor core @@ -724,7 +731,7 @@ setup_bats: * Note: requires that all cache bits in * HID0 are in the low half word. */ -#ifndef CONFIG_NAND_SPL +#ifndef MINIMAL_SPL .globl icache_enable icache_enable: mfspr r3, HID0 @@ -753,7 +760,7 @@ icache_status: mfspr r3, HID0 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 blr -#endif /* !CONFIG_NAND_SPL */ +#endif /* !MINIMAL_SPL */ .globl dcache_enable dcache_enable: @@ -936,7 +943,7 @@ in_ram: stw r0,0(r3) 2: bdnz 1b -#ifndef CONFIG_NAND_SPL +#ifndef MINIMAL_SPL /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. @@ -991,7 +998,7 @@ clear_bss: mr r4, r10 /* Destination Address */ bl board_init_r -#ifndef CONFIG_NAND_SPL +#ifndef MINIMAL_SPL /* * Copy exception vector code to low memory * @@ -1061,7 +1068,7 @@ trap_init: mtlr r4 /* restore link register */ blr -#endif /* !CONFIG_NAND_SPL */ +#endif /* !MINIMAL_SPL */ #ifdef CONFIG_SYS_INIT_RAM_LOCK lock_ram_in_cache: @@ -1085,7 +1092,7 @@ lock_ram_in_cache: sync blr -#ifndef CONFIG_NAND_SPL +#ifndef MINIMAL_SPL .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ @@ -1111,7 +1118,7 @@ unlock_ram_in_cache: sync mtspr HID0, r3 /* no invalidate, unlock */ blr -#endif /* !CONFIG_NAND_SPL */ +#endif /* !MINIMAL_SPL */ #endif /* CONFIG_SYS_INIT_RAM_LOCK */ #ifdef CONFIG_SYS_FLASHBOOT diff --git a/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds new file mode 100644 index 0000000000..d140453d49 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright 2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + . = 0xfff00000; + .text : { + *(.text*) + . = ALIGN(16); + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + + . = ALIGN(8); + .data : { + *(.data*) + *(.sdata*) + _GOT2_TABLE_ = .; + KEEP(*(.got2)) + KEEP(*(.got)) + PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); + } + __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; + + . = ALIGN(8); + __bss_start = .; + .bss (NOLOAD) : { + *(.*bss) + } + __bss_end__ = .; +} +ENTRY(_start) +ASSERT(__bss_end__ <= 0xfff01000, "NAND bootstrap too big"); diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index 844fe8636d..86cf02ace4 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -47,7 +47,8 @@ endif endif ifdef MINIMAL -COBJS-y += cache.o +COBJS-y += cache.o time.o +SOBJS-y += ticks.o else SOBJS-y += ppcstring.o -- cgit v1.2.1