From 6b8ac524e7bcfd4853bb4f494e539a63d894a46f Mon Sep 17 00:00:00 2001 From: Ashok Date: Fri, 15 Jun 2012 03:48:57 +0000 Subject: mx6: Make pad name macro consistent with the datasheet Use the same name as defined in the datasheet. DSP_CLK -> DISP_CLK Signed-off-by: Ashok Kumar Reddy Kourla Acked-by: Marek Vasut --- arch/arm/include/asm/arch-mx6/mx6x_pins.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-mx6/mx6x_pins.h b/arch/arm/include/asm/arch-mx6/mx6x_pins.h index 9979651b0f..cf9103c3d2 100644 --- a/arch/arm/include/asm/arch-mx6/mx6x_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6x_pins.h @@ -530,8 +530,8 @@ enum { MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 = IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0), MX6Q_PAD_EIM_BCLK__GPIO_6_31 = IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0), MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 = IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0), - MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, 0), - MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0), + MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, 0), + MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0), MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 = IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0), MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 = IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0), MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 = IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0), -- cgit v1.2.1 From f8f09dd40423b7f9ea0f0b810a8f5da9cd580a17 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Thu, 19 Jul 2012 01:35:32 +0000 Subject: ARM1136: Fix cache range checks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit bad_cache_range actually returned true if the range was OK, but it was used according to its name, which resulted in all valid dcache range invalidate/flush operations being dropped. Hence, most DMA transfers resulted in garbage data. This patch renames this function according to what it does, and it fixes the interpretation of its return value by other functions. The chosen naming is the same as for ARM926EJ-S in order to be consistent. Signed-off-by: Benoît Thébaudeau Cc: Albert Aribaud Acked-by: Stefano Babic --- arch/arm/cpu/arm1136/cpu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/arm1136/cpu.c b/arch/arm/cpu/arm1136/cpu.c index f72bab6693..b98e3d9fac 100644 --- a/arch/arm/cpu/arm1136/cpu.c +++ b/arch/arm/cpu/arm1136/cpu.c @@ -95,7 +95,7 @@ void flush_dcache_all(void) asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); } -static inline int bad_cache_range(unsigned long start, unsigned long stop) +static int check_cache_range(unsigned long start, unsigned long stop) { int ok = 1; @@ -114,7 +114,7 @@ static inline int bad_cache_range(unsigned long start, unsigned long stop) void invalidate_dcache_range(unsigned long start, unsigned long stop) { - if (bad_cache_range(start, stop)) + if (!check_cache_range(start, stop)) return; while (start < stop) { @@ -125,7 +125,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop) void flush_dcache_range(unsigned long start, unsigned long stop) { - if (bad_cache_range(start, stop)) + if (!check_cache_range(start, stop)) return; while (start < stop) { -- cgit v1.2.1