From da30b9fd97f031a6b6863359f3d4c6633e5c7035 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Fri, 1 Apr 2011 13:19:36 -0500 Subject: powerpc/85xx: Implement work-around for P4080 erratum SERDES-A005 SerDes PLL bandwidth default setting is incorrect when no lanes are configured as PCI Express. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala --- arch/powerpc/include/asm/config_mpc85xx.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/powerpc/include/asm') diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index da2e99804d..b8b8914c44 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -311,6 +311,7 @@ #define CONFIG_SYS_P4080_ERRATUM_CPU22 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 +#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 /* P5010 is single core version of P5020 */ #elif defined(CONFIG_PPC_P5010) -- cgit v1.2.1