From 7fd101c97b58dab7b0bd87f30c3dedb0db21d15f Mon Sep 17 00:00:00 2001 From: york Date: Fri, 2 Jul 2010 22:25:54 +0000 Subject: powerpc/8xxx: Enabled address hashing for 85xx For 85xx silicon which supports address hashing, it can be activated by hwconfig. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 10 ++++++++++ arch/powerpc/cpu/mpc8xxx/ddr/options.c | 7 +++++++ 2 files changed, 17 insertions(+) (limited to 'arch/powerpc/cpu/mpc8xxx/ddr') diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index 6e73b1d314..ff0ddd1894 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1161,6 +1161,14 @@ static void set_ddr_sdram_rcw_2(fsl_ddr_cfg_regs_t *ddr) ); } +static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) +{ + if (popts->addr_hash) { + ddr->ddr_eor = 0x40000000; /* address hash enable */ + puts("Addess hashing enabled.\n"); + } +} + unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) { @@ -1392,6 +1400,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_csn_config_2(i, ddr); } + set_ddr_eor(ddr, popts); + #if !defined(CONFIG_FSL_DDR1) set_timing_cfg_0(ddr); #endif diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index 1d5f3e2cdd..e4805d36b0 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -341,6 +341,13 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, } } + if (hwconfig_sub("fsl_ddr", "addr_hash")) { + if (hwconfig_subarg_cmp("fsl_ddr", "addr_hash", "null")) + popts->addr_hash = 0; + else if (hwconfig_subarg_cmp("fsl_ddr", "addr_hash", "true")) + popts->addr_hash = 1; + } + if (pdimm[0].n_ranks == 4) popts->quad_rank_present = 1; -- cgit v1.2.1