From 24995d829aecc6abca0f1b41443ae0cd9b4fde5a Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Thu, 20 Jan 2011 22:26:31 +0000 Subject: powerpc/85xx: Refactor Qman/Portal support to be shared between SoCs There are some differences between CoreNet (P2040, P3041, P5020, P4080) and and non-CoreNet (P1017, P1023) based SoCs in what features exist and the memory maps. * Rename various immap defines to remove _CORENET_ if they are shared * Added P1023/P1017 specific memory offsets * Only setup LIODNs or LIODN related code on CORENET based SoCs (features doesn't exist on P1023/P1017) Signed-off-by: Haiying Wang Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/speed.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'arch/powerpc/cpu/mpc85xx/speed.c') diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index f2aa8d039d..9d749c3330 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -162,7 +162,6 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ; } #endif -#endif #ifdef CONFIG_QE qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) @@ -170,6 +169,15 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ; #endif +#ifdef CONFIG_SYS_DPAA_FMAN + sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; +#if (CONFIG_SYS_NUM_FMAN) == 2 + sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; +#endif +#endif + +#endif /* CONFIG_FSL_CORENET */ + #if defined(CONFIG_FSL_LBC) #if defined(CONFIG_SYS_LBC_LCRR) /* We will program LCRR to this value later */ -- cgit v1.2.1 From 7d640e9bdf5e38f7f40f8becc47dc4036943f01a Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Tue, 8 Feb 2011 15:45:25 +0530 Subject: powerpc/85xx: Corrected sdhc clock value for P1010 SDHC clock is equal to CCB on P1010 and P1014 not CCB/2. Signed-off-by: Priyanka Jain Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/speed.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/powerpc/cpu/mpc85xx/speed.c') diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 9d749c3330..faca451cc1 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -262,7 +262,8 @@ int get_clocks (void) gd->i2c2_clk = gd->i2c1_clk; #if defined(CONFIG_FSL_ESDHC) -#ifdef CONFIG_MPC8569 +#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\ + defined(CONFIG_P1014) gd->sdhc_clk = gd->bus_clk; #else gd->sdhc_clk = gd->bus_clk / 2; -- cgit v1.2.1 From b5c8753fa173d6372d86dcd11f83ef23c911b0de Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 16 Feb 2011 02:03:29 -0600 Subject: powerpc/85xx: Fixup determining PME, FMan freq On CoreNet based SoCs (P2040, P3041, P4080, P5020) we have some additional rules to determining the various frequencies that PME & FMan IP blocks run at. We need to take into account: * Reduced number of Core Complex PLL clusters * HWA_ASYNC_DIV (allows for /2 or /4 options) On P2040/P3041/P5020 we only have 2 Core Complex PLLs and in such SoCs the PME & FMan blocks utilize the second Core Complex PLL. On SoCs like p4080 with 4 Core Complex PLLs we utilize the third Core Complex PLL for PME & FMan blocks. On P2040/P3041/P5020 we have the added feature that we can divide the PLL down further by either /2 or /4 based on HWA_ASYNC_DIV. On P4080 this options doesn't exist, however HWA_ASYNC_DIV field in RCW should be set to 0 and this gets a backward compatiable /2 behavior. Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/speed.c | 38 +++++++++++++++++++++++++++++--------- 1 file changed, 29 insertions(+), 9 deletions(-) (limited to 'arch/powerpc/cpu/mpc85xx/speed.c') diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index faca451cc1..f26de6cd3e 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -107,25 +107,45 @@ void get_sys_info (sys_info_t * sysInfo) #define PME_CLK_SEL 0x80000000 #define FM1_CLK_SEL 0x40000000 #define FM2_CLK_SEL 0x20000000 +#define HWA_ASYNC_DIV 0x04000000 +#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2) +#define HWA_CC_PLL 1 +#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4) +#define HWA_CC_PLL 2 +#else +#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case +#endif rcw_tmp = in_be32(&gur->rcwsr[7]); #ifdef CONFIG_SYS_DPAA_PME - if (rcw_tmp & PME_CLK_SEL) - sysInfo->freqPME = freqCC_PLL[2] / 2; - else + if (rcw_tmp & PME_CLK_SEL) { + if (rcw_tmp & HWA_ASYNC_DIV) + sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 4; + else + sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 2; + } else { sysInfo->freqPME = sysInfo->freqSystemBus / 2; + } #endif #ifdef CONFIG_SYS_DPAA_FMAN - if (rcw_tmp & FM1_CLK_SEL) - sysInfo->freqFMan[0] = freqCC_PLL[2] / 2; - else + if (rcw_tmp & FM1_CLK_SEL) { + if (rcw_tmp & HWA_ASYNC_DIV) + sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 4; + else + sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 2; + } else { sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; + } #if (CONFIG_SYS_NUM_FMAN) == 2 - if (rcw_tmp & FM2_CLK_SEL) - sysInfo->freqFMan[1] = freqCC_PLL[2] / 2; - else + if (rcw_tmp & FM2_CLK_SEL) { + if (rcw_tmp & HWA_ASYNC_DIV) + sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 4; + else + sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 2; + } else { sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; + } #endif #endif -- cgit v1.2.1 From 939cdcdc622840d43dd01b6a9509abcb6f4c24f6 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 10 Mar 2011 06:09:20 -0600 Subject: powerpc/85xx: Fix determining Fman freq on P1023 On the P1023 the Fman freq is equivalent to the system bus freq, not 1/2 of it. Also we only have one Fman so no need for the code to deal with a second. Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/speed.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'arch/powerpc/cpu/mpc85xx/speed.c') diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index f26de6cd3e..e530494102 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -190,10 +190,7 @@ void get_sys_info (sys_info_t * sysInfo) #endif #ifdef CONFIG_SYS_DPAA_FMAN - sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; -#if (CONFIG_SYS_NUM_FMAN) == 2 - sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; -#endif + sysInfo->freqFMan[0] = sysInfo->freqSystemBus; #endif #endif /* CONFIG_FSL_CORENET */ -- cgit v1.2.1