From 24995d829aecc6abca0f1b41443ae0cd9b4fde5a Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Thu, 20 Jan 2011 22:26:31 +0000 Subject: powerpc/85xx: Refactor Qman/Portal support to be shared between SoCs There are some differences between CoreNet (P2040, P3041, P5020, P4080) and and non-CoreNet (P1017, P1023) based SoCs in what features exist and the memory maps. * Rename various immap defines to remove _CORENET_ if they are shared * Added P1023/P1017 specific memory offsets * Only setup LIODNs or LIODN related code on CORENET based SoCs (features doesn't exist on P1023/P1017) Signed-off-by: Haiying Wang Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/portals.c | 32 +++++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) (limited to 'arch/powerpc/cpu/mpc85xx/portals.c') diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c index 01aec6e794..e8d53bb2fd 100644 --- a/arch/powerpc/cpu/mpc85xx/portals.c +++ b/arch/powerpc/cpu/mpc85xx/portals.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -30,18 +30,13 @@ #include #include -static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_CORENET_QMAN_ADDR; +static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR; void setup_portals(void) { +#ifdef CONFIG_FSL_CORENET int i; - /* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */ -#ifdef CONFIG_PHYS_64BIT - out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32)); -#endif - out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS); - for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) { u8 sdest = qp_info[i].sdest; u16 fliodn = qp_info[i].fliodn; @@ -53,6 +48,13 @@ void setup_portals(void) /* set frame liodn */ out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn); } +#endif + + /* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */ +#ifdef CONFIG_PHYS_64BIT + out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32)); +#endif + out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS); } /* Update portal containter to match LAW setup of portal in phy map */ @@ -118,9 +120,12 @@ void fdt_portal(void *blob, const char *compat, const char *container, static int fdt_qportal(void *blob, int off, int id, char *name, enum fsl_dpaa_dev dev, int create) { - int childoff, dev_off, num, ret = 0; + int childoff, dev_off, ret = 0; uint32_t dev_handle; +#ifdef CONFIG_FSL_CORENET + int num; u32 liodns[2]; +#endif childoff = fdt_subnode_offset(blob, off, name); if (create) { @@ -154,9 +159,11 @@ static int fdt_qportal(void *blob, int off, int id, char *name, if (ret < 0) return ret; +#ifdef CONFIG_FSL_CORENET num = get_dpaa_liodn(dev, &liodns[0], id); ret = fdt_setprop(blob, childoff, "fsl,liodn", &liodns[0], sizeof(u32) * num); +#endif } else { return childoff; } @@ -184,7 +191,9 @@ void fdt_fixup_qportals(void *blob) off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal"); while (off != -FDT_ERR_NOTFOUND) { +#ifdef CONFIG_FSL_CORENET u32 liodns[2]; +#endif const int *ci = fdt_getprop(blob, off, "cell-index", NULL); int j, i = *ci; @@ -192,6 +201,7 @@ void fdt_fixup_qportals(void *blob) if (err < 0) goto err; +#ifdef CONFIG_FSL_CORENET liodns[0] = qp_info[i].dliodn; liodns[1] = qp_info[i].fliodn; @@ -199,6 +209,7 @@ void fdt_fixup_qportals(void *blob) &liodns, sizeof(u32) * 2); if (err < 0) goto err; +#endif i++; @@ -207,6 +218,7 @@ void fdt_fixup_qportals(void *blob) if (err < 0) goto err; +#ifdef CONFIG_FSL_CORENET #ifdef CONFIG_SYS_DPAA_PME err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 1); if (err < 0) @@ -214,6 +226,8 @@ void fdt_fixup_qportals(void *blob) #else fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 0); #endif +#endif + #ifdef CONFIG_SYS_DPAA_FMAN for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) { char name[] = "fman@0"; -- cgit v1.2.1