From 00f892fcc9726b8b299c1da2383fc9bf4a3618c5 Mon Sep 17 00:00:00 2001
From: Macpaul Lin <macpaul@andestech.com>
Date: Tue, 11 Oct 2011 22:33:15 +0000
Subject: nds32: add header files support for nds32

Add generic header files support for nds32 architecture.
Cache, ptregs, data type and other definitions are included.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
 arch/nds32/include/asm/byteorder.h | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 arch/nds32/include/asm/byteorder.h

(limited to 'arch/nds32/include/asm/byteorder.h')

diff --git a/arch/nds32/include/asm/byteorder.h b/arch/nds32/include/asm/byteorder.h
new file mode 100644
index 0000000000..39fd9eddf0
--- /dev/null
+++ b/arch/nds32/include/asm/byteorder.h
@@ -0,0 +1,36 @@
+/*
+ *  linux/include/asm-arm/byteorder.h
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * ARM Endian-ness.  In little endian mode, the data bus is connected such
+ * that byte accesses appear as:
+ *  0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ *
+ * When in big endian mode, byte accesses appear as:
+ *  0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ */
+
+#ifndef __ASM_NDS_BYTEORDER_H
+#define __ASM_NDS_BYTEORDER_H
+
+#include <asm/types.h>
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __NDSEB__
+#include <linux/byteorder/big_endian.h>
+#else
+#include <linux/byteorder/little_endian.h>
+#endif
+
+#endif
-- 
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