From aa0ecfeb9d60d82e095daa0d6271f77b2c25d3fb Mon Sep 17 00:00:00 2001
From: Ajay Bhargav <[ajay.bhargav@einfochips.com]>
Date: Tue, 13 Sep 2011 22:22:04 +0530
Subject: Armada100: Enable Ethernet support for GplugD

This patch enables ethernet support for Marvell GplugD board. Network
related commands works.

Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
---
 arch/arm/include/asm/arch-armada100/armada100.h | 57 +++++++++++++++++++++++++
 arch/arm/include/asm/arch-armada100/mfp.h       | 19 +++++++++
 2 files changed, 76 insertions(+)

(limited to 'arch/arm')

diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h
index 9b9ed165e0..c449d4e639 100644
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -41,6 +41,10 @@
 /* Functional Clock Selection Mask */
 #define APBC_FNCLKSEL(x)        (((x) & 0xf) << 4)
 
+/* Fast Ethernet Controller Clock register definition */
+#define FE_CLK_RST		0x1
+#define FE_CLK_ENA		0x8
+
 /* Register Base Addresses */
 #define ARMD1_DRAM_BASE		0xB0000000
 #define ARMD1_FEC_BASE		0xC0800000
@@ -84,6 +88,59 @@ struct armd1mpmu_registers {
 	u32 arsr;	/*0x1028*/
 };
 
+/*
+ * Application Subsystem Power Management
+ * Refer Datasheet Appendix A.9
+ */
+struct armd1apmu_registers {
+	u32 pcr;		/* 0x000 */
+	u32 ccr;		/* 0x004 */
+	u32 pad1;
+	u32 ccsr;		/* 0x00C */
+	u32 fc_timer;		/* 0x010 */
+	u32 pad2;
+	u32 ideal_cfg;		/* 0x018 */
+	u8 pad3[0x04C - 0x018 - 4];
+	u32 lcdcrc;		/* 0x04C */
+	u32 cciccrc;		/* 0x050 */
+	u32 sd1crc;		/* 0x054 */
+	u32 sd2crc;		/* 0x058 */
+	u32 usbcrc;		/* 0x05C */
+	u32 nfccrc;		/* 0x060 */
+	u32 dmacrc;		/* 0x064 */
+	u32 pad4;
+	u32 buscrc;		/* 0x06C */
+	u8 pad5[0x07C - 0x06C - 4];
+	u32 wake_clr;		/* 0x07C */
+	u8 pad6[0x090 - 0x07C - 4];
+	u32 core_status;	/* 0x090 */
+	u32 rfsc;		/* 0x094 */
+	u32 imr;		/* 0x098 */
+	u32 irwc;		/* 0x09C */
+	u32 isr;		/* 0x0A0 */
+	u8 pad7[0x0B0 - 0x0A0 - 4];
+	u32 mhst;		/* 0x0B0 */
+	u32 msr;		/* 0x0B4 */
+	u8 pad8[0x0C0 - 0x0B4 - 4];
+	u32 msst;		/* 0x0C0 */
+	u32 pllss;		/* 0x0C4 */
+	u32 smb;		/* 0x0C8 */
+	u32 gccrc;		/* 0x0CC */
+	u8 pad9[0x0D4 - 0x0CC - 4];
+	u32 smccrc;		/* 0x0D4 */
+	u32 pad10;
+	u32 xdcrc;		/* 0x0DC */
+	u32 sd3crc;		/* 0x0E0 */
+	u32 sd4crc;		/* 0x0E4 */
+	u8 pad11[0x0F0 - 0x0E4 - 4];
+	u32 cfcrc;		/* 0x0F0 */
+	u32 mspcrc;		/* 0x0F4 */
+	u32 cmucrc;		/* 0x0F8 */
+	u32 fecrc;		/* 0x0FC */
+	u32 pciecrc;		/* 0x100 */
+	u32 epdcrc;		/* 0x104 */
+};
+
 /*
  * APB1 Clock Reset/Control Registers
  * Refer Datasheet Appendix A.10
diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h
index d6e0494b7e..da76b58405 100644
--- a/arch/arm/include/asm/arch-armada100/mfp.h
+++ b/arch/arm/include/asm/arch-armada100/mfp.h
@@ -64,6 +64,25 @@
 #define MFP105_CI2C_SDA		(MFP_REG(0x1a4) | MFP_AF1 | MFP_DRIVE_MEDIUM)
 #define MFP106_CI2C_SCL		(MFP_REG(0x1a8) | MFP_AF1 | MFP_DRIVE_MEDIUM)
 
+/* Fast Ethernet */
+#define MFP086_ETH_TXCLK	(MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP087_ETH_TXEN		(MFP_REG(0x15C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP088_ETH_TXDQ3	(MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP089_ETH_TXDQ2	(MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP090_ETH_TXDQ1	(MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP091_ETH_TXDQ0	(MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP092_ETH_CRS		(MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP093_ETH_COL		(MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP094_ETH_RXCLK	(MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP095_ETH_RXER		(MFP_REG(0x17C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP096_ETH_RXDQ3	(MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP097_ETH_RXDQ2	(MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP098_ETH_RXDQ1	(MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP099_ETH_RXDQ0	(MFP_REG(0x18C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP100_ETH_MDC		(MFP_REG(0x190) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP101_ETH_MDIO		(MFP_REG(0x194) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP103_ETH_RXDV		(MFP_REG(0x19C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+
 /* More macros can be defined here... */
 
 #define MFP_PIN_MAX	117
-- 
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