From a83e1bc06bef1dc155b7f4d9f96f2bfc315d4dd7 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 13 Jul 2016 16:36:57 +0930 Subject: ARM: AST2500: add support Extracted from ast_sdk.v00.03.21 which is based on u-boot v2013. Signed-off-by: Joel Stanley --- arch/arm/Kconfig | 8 + arch/arm/Makefile | 1 + arch/arm/cpu/arm926ejs/aspeed/Makefile | 1 + arch/arm/cpu/arm926ejs/aspeed/cpu.c | 23 + arch/arm/include/asm/arch-aspeed/aspeed.h | 29 + arch/arm/include/asm/arch-aspeed/ast-ahbc.h | 38 + arch/arm/include/asm/arch-aspeed/ast-sdmc.h | 34 + .../arm/include/asm/arch-aspeed/ast2400_platform.h | 82 + arch/arm/include/asm/arch-aspeed/ast_g5_platform.h | 190 ++ arch/arm/include/asm/arch-aspeed/ast_scu.h | 48 + arch/arm/include/asm/arch-aspeed/platform.h | 34 + arch/arm/include/asm/arch-aspeed/regs-ahbc.h | 38 + arch/arm/include/asm/arch-aspeed/regs-scu.h | 952 ++++++ arch/arm/include/asm/arch-aspeed/regs-sdmc.h | 32 + arch/arm/include/asm/mach-types.h | 13 + arch/arm/mach-aspeed/Makefile | 17 + arch/arm/mach-aspeed/ast-ahbc.c | 87 + arch/arm/mach-aspeed/ast-scu.c | 498 ++++ arch/arm/mach-aspeed/ast-sdmc.c | 99 + arch/arm/mach-aspeed/cpuinfo.c | 46 + arch/arm/mach-aspeed/flash.c | 1403 +++++++++ arch/arm/mach-aspeed/platform_g4.S | 3092 ++++++++++++++++++++ arch/arm/mach-aspeed/platform_g5.S | 1999 +++++++++++++ arch/arm/mach-aspeed/reset.c | 18 + arch/arm/mach-aspeed/timer.c | 140 + 25 files changed, 8922 insertions(+) create mode 100644 arch/arm/cpu/arm926ejs/aspeed/Makefile create mode 100644 arch/arm/cpu/arm926ejs/aspeed/cpu.c create mode 100644 arch/arm/include/asm/arch-aspeed/aspeed.h create mode 100644 arch/arm/include/asm/arch-aspeed/ast-ahbc.h create mode 100644 arch/arm/include/asm/arch-aspeed/ast-sdmc.h create mode 100644 arch/arm/include/asm/arch-aspeed/ast2400_platform.h create mode 100644 arch/arm/include/asm/arch-aspeed/ast_g5_platform.h create mode 100644 arch/arm/include/asm/arch-aspeed/ast_scu.h create mode 100644 arch/arm/include/asm/arch-aspeed/platform.h create mode 100644 arch/arm/include/asm/arch-aspeed/regs-ahbc.h create mode 100644 arch/arm/include/asm/arch-aspeed/regs-scu.h create mode 100644 arch/arm/include/asm/arch-aspeed/regs-sdmc.h create mode 100644 arch/arm/mach-aspeed/Makefile create mode 100644 arch/arm/mach-aspeed/ast-ahbc.c create mode 100644 arch/arm/mach-aspeed/ast-scu.c create mode 100644 arch/arm/mach-aspeed/ast-sdmc.c create mode 100644 arch/arm/mach-aspeed/cpuinfo.c create mode 100644 arch/arm/mach-aspeed/flash.c create mode 100644 arch/arm/mach-aspeed/platform_g4.S create mode 100644 arch/arm/mach-aspeed/platform_g5.S create mode 100644 arch/arm/mach-aspeed/reset.c create mode 100644 arch/arm/mach-aspeed/timer.c (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3237a74f72..801152ae29 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -849,6 +849,14 @@ config TARGET_THUNDERX_88XX select ARM64 select OF_CONTROL +config TARGET_AST_G5 + bool "Support Apseed fifth generation SoCs" + select CPU_ARM1176 + +config TARGET_AST_G4 + bool "Support Aspeed fourth generation SoCs" + select CPU_ARM926EJS + endchoice source "arch/arm/mach-at91/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 6a07cd178e..839775d008 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -42,6 +42,7 @@ PLATFORM_CPPFLAGS += $(arch-y) $(tune-y) # Machine directory name. This list is sorted alphanumerically # by CONFIG_* macro name. +machine-$(CONFIG_ARCH_ASPEED) += aspeed machine-$(CONFIG_ARCH_AT91) += at91 machine-$(CONFIG_ARCH_BCM283X) += bcm283x machine-$(CONFIG_ARCH_DAVINCI) += davinci diff --git a/arch/arm/cpu/arm926ejs/aspeed/Makefile b/arch/arm/cpu/arm926ejs/aspeed/Makefile new file mode 100644 index 0000000000..e085b7b442 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/Makefile @@ -0,0 +1 @@ +obj-y += cpu.o diff --git a/arch/arm/cpu/arm926ejs/aspeed/cpu.c b/arch/arm/cpu/arm926ejs/aspeed/cpu.c new file mode 100644 index 0000000000..488d540ba9 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/cpu.c @@ -0,0 +1,23 @@ +/* + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +void enable_caches(void) +{ + icache_enable(); + //TODO ..... + dcache_enable(); + +} + diff --git a/arch/arm/include/asm/arch-aspeed/aspeed.h b/arch/arm/include/asm/arch-aspeed/aspeed.h new file mode 100644 index 0000000000..7d2de1cbd4 --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/aspeed.h @@ -0,0 +1,29 @@ +/* + * arch/arm/plat-aspeed/include/plat/aspeed.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#if defined(CONFIG_ARCH_AST3200) || defined(CONFIG_ARCH_AST2500) || defined(CONFIG_ARCH_AST1520) +#define AST_SOC_G5 +#define SRAM_SIZE SZ_32K +#elif defined(CONFIG_ARCH_AST1400) || defined(CONFIG_ARCH_AST2400) || defined(CONFIG_ARCH_AST3100) +#define AST_SOC_G4 +#define SRAM_SIZE SZ_32K +#else +#error "Not define SoC generation" +#endif diff --git a/arch/arm/include/asm/arch-aspeed/ast-ahbc.h b/arch/arm/include/asm/arch-aspeed/ast-ahbc.h new file mode 100644 index 0000000000..c870d11127 --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/ast-ahbc.h @@ -0,0 +1,38 @@ +/******************************************************************************* +* File Name : arch/arm/mach-aspeed/include/plat/ast-ahbc.h +* Author : Ryan Chen +* Description : AST SCU Service Header +* +* Copyright (C) 2012-2020 ASPEED Technology Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but +* WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +* USA +* +* History : +* 1. 2014/08/03 Ryan Chen create this file +* +*******************************************************************************/ + +#ifndef __AST_AHBC_H +#define __AST_AHBC_H + +extern void ast_ahbc_boot_remap(void); + +#ifdef AST_SOC_G5 +extern void ast_ahbc_lpc_plus_mapping(u8 enable); +extern void ast_ahbc_peie_mapping(u8 enable); +#endif + +#endif diff --git a/arch/arm/include/asm/arch-aspeed/ast-sdmc.h b/arch/arm/include/asm/arch-aspeed/ast-sdmc.h new file mode 100644 index 0000000000..4590d307c2 --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/ast-sdmc.h @@ -0,0 +1,34 @@ +/******************************************************************************* + * File Name : arch/arm/mach-aspeed/include/plat/ast-sdmc.h + * Author : Ryan Chen + * Description : AST SDMC Header + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * History : + * 1. 2012/08/03 Ryan Chen create this file + * + ******************************************************************************/ + +#ifndef __AST_SDMC_H +#define __AST_SDMC_H + +extern u32 ast_sdmc_get_mem_size(void); +extern u8 ast_sdmc_get_eec(void); +extern u8 ast_sdmc_get_cache(void); + +#endif diff --git a/arch/arm/include/asm/arch-aspeed/ast2400_platform.h b/arch/arm/include/asm/arch-aspeed/ast2400_platform.h new file mode 100644 index 0000000000..5c00bb60ea --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/ast2400_platform.h @@ -0,0 +1,82 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST2400_PLATFORM_H +#define _AST2400_PLATFORM_H + +#define AST_DRAM_BASE 0x40000000 + +#define AST_SRAM_SIZE (SZ_16K * 2) + +#define AST_OLD_SMC_BASE 0x10000000 /* Legacy BMC Static Memory */ +#define AST_OLD_SMC_CTRL_BASE 0x16000000 /* Legacy BMC Static Memory Ctrl*/ + +#define AST_AHBC_BASE 0x1E600000 /* AHB CONTROLLER */ + +#define AST_FMC_BASE 0x1E620000 /* NEW SMC CONTROLLER */ +#define AST_SPI_BASE 0x1E630000 /* SPI CONTROLLER */ +#define AST_MIC_BASE 0x1E640000 /* MIC CONTROLLER */ +#define AST_MAC0_BASE 0x1E660000 /* MAC1 */ +#define AST_MAC1_BASE 0x1E680000 /* MAC2 */ + +#define AST_USB20_BASE 0x1E6A0000 /* USB 2.0 VIRTUAL HUB CONTROLLER */ +#define AST_EHCI_BASE 0x1E6A1000 /* USB 2.0 HOST CONTROLLER */ +#define AST_UHCI_BASE 0x1E6B0000 /* USB 1.1 HOST CONTROLLER */ +#define AST_VIC_BASE 0x1E6C0000 /* VIC */ +#define AST_SDMC_BASE 0x1E6E0000 /* MMC */ +#define AST_USB11_BASE 0x1E6E1000 /* USB11 */ +#define AST_SCU_BASE 0x1E6E2000 /* SCU */ +#define AST_CRYPTO_BASE 0x1E6E3000 /* Crypto */ +#define AST_JTAG_BASE 0x1E6E4000 /* JTAG */ +#define AST_GRAPHIC_BASE 0x1E6E6000 /* Graphics */ +#define AST_XDMA_BASE 0x1E6E7000 /* XDMA */ +#define AST_MCTP_BASE 0x1E6E8000 /* MCTP */ +#define AST_ADC_BASE 0x1E6E9000 /* ADC */ + +#define AST_LPC_PLUS_BASE 0x1E6EC000 /* LPC+ Controller */ + +#define AST_VIDEO_BASE 0x1E700000 /* VIDEO ENGINE */ +#define AST_SRAM_BASE 0x1E720000 /* SRAM */ +#define AST_SDHC_BASE 0x1E740000 /* SDHC */ +#define AST_2D_BASE 0x1E760000 /* 2D */ +#define AST_GPIO_BASE 0x1E780000 /* GPIO */ +#define AST_RTC_BASE 0x1E781000 /* RTC */ +#define AST_TIMER_BASE 0x1E782000 /* TIMER #0~7*/ +#define AST_UART1_BASE 0x1E783000 /* UART1 */ +#define AST_UART0_BASE 0x1E784000 /* UART5 */ +#define AST_WDT_BASE 0x1E785000 /* WDT */ +#define AST_PWM_BASE 0x1E786000 /* PWM */ +#define AST_VUART0_BASE 0x1E787000 /* VUART1 */ +#define AST_PUART_BASE 0x1E788000 /* PUART */ +#define AST_LPC_BASE 0x1E789000 /* LPC */ +#define AST_I2C_BASE 0x1E78A000 /* I2C */ +#define AST_PECI_BASE 0x1E78B000 /* PECI */ +#define AST_PCIARBITER_BASE 0x1E78C000 /* PCI ARBITER */ +#define AST_UART2_BASE 0x1E78D000 /* UART2 */ +#define AST_UART3_BASE 0x1E78E000 /* UART3 */ +#define AST_UART4_BASE 0x1E78F000 /* UART4 */ +#define AST_SPI_MEM 0x30000000 + +#define AST_LPC_PLUS_BRIDGE 0x70000000 +#define AST_LPC_BRIDGE 0x60000000 + +#define AST_FMC_CS0_BASE 0x20000000 /* CS0 */ +#define AST_FMC_CS1_BASE 0x24000000 /* CS1 */ +#define AST_FMC_CS2_BASE 0x26000000 /* CS2 */ +#define AST_FMC_CS3_BASE 0x28000000 /* CS3 */ +#define AST_FMC_CS4_BASE 0x2a000000 /* CS4 */ + +#endif diff --git a/arch/arm/include/asm/arch-aspeed/ast_g5_platform.h b/arch/arm/include/asm/arch-aspeed/ast_g5_platform.h new file mode 100644 index 0000000000..3b178cdbe2 --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/ast_g5_platform.h @@ -0,0 +1,190 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST_G5_PLATFORM_H +#define _AST_G5_PLATFORM_H + +#ifdef CONFIG_AST_PCIE_EXT +/* +#define AST_PCI_EXT_ADC (AST_PCIE_WIN_BASE + 0x2000) +#define AST_PCI_EXT_PWM (AST_PCIE_WIN_BASE + 0x3000) +#define AST_PCI_EXT_GPIO (AST_PCIE_WIN_BASE + 0x4000) +*/ +#define AST_PCI_EXT_I2C (AST_PCIE_WIN_BASE + 0x5000) +#define AST_PCI_EXT_SCU (AST_PCIE_WIN_BASE + 0x6000) +#define AST_PCI_EXT_VIC (AST_PCIE_WIN_BASE + 0x7000) + +#define AST_PCI_EXT_GPIO (AST_PCIE_WIN_BASE + 0x10000) +#define AST_PCI_EXT_UART1 (AST_PCIE_WIN_BASE + 0x13000) +#define AST_PCI_EXT_UART0 (AST_PCIE_WIN_BASE + 0x14000) +#define AST_PCI_EXT_UART2 (AST_PCIE_WIN_BASE + 0x1D000) +#define AST_PCI_EXT_UART3 (AST_PCIE_WIN_BASE + 0x1E000) +#define AST_PCI_EXT_UART4 (AST_PCIE_WIN_BASE + 0x1F000) + +#endif + +#define AST_DRAM_BASE 0x80000000 + +#define AST_SRAM_SIZE (SZ_32K) + +#define AST_AHBC_BASE 0x1E600000 /* AHB CONTROLLER */ + +#define AST_FMC_BASE 0x1E620000 /* NEW SMC CONTROLLER */ +#define AST_FMC_SPI0_BASE 0x1E630000 /* NEW SMC CONTROLLER */ +#define AST_FMC_SPI1_BASE 0x1E631000 /* NEW SMC CONTROLLER */ + +#define AST_MIC_BASE 0x1E650000 /* Memory Integrity Check Controller */ +#define AST_MAC0_BASE 0x1E660000 /* MAC1 */ +#define AST_MAC1_BASE 0x1E680000 /* MAC2 */ +#define AST_VHUB_BASE 0x1E6A0000 /* USB 2.0 VIRTUAL HUB CONTROLLER */ +#define AST_EHCI0_BASE 0x1E6A1000 /* USB 2.0 HOST CONTROLLER */ +#define AST_UDC1_BASE 0x1E6A2000 /* USB 2.0 Device CONTROLLER */ +#define AST_EHCI1_BASE 0x1E6A3000 /* USB 2.0 HOST CONTROLLER */ +#define AST_UHCI_BASE 0x1E6B0000 /* USB 1.1 HOST CONTROLLER */ +#define AST_VIC_BASE 0x1E6C0000 /* VIC */ +#define AST_SDMC_BASE 0x1E6E0000 /* MMC SDRAM*/ +#define AST_HID_BASE 0x1E6E1000 /* USB 1.1 Controller */ +#define AST_SCU_BASE 0x1E6E2000 /* SCU */ +#define AST_CRYPTO_BASE 0x1E6E3000 /* Crypto */ +#define AST_JTAG_BASE 0x1E6E4000 /* JTAG */ +#define AST_I2S_BASE 0x1E6E5000 /* I2S */ +#define AST_CRT0_BASE 0x1E6E6000 /* CRT0 */ +#define AST_CRT1_BASE 0x1E6E6100 /* CRT1 */ +#define AST_CRT2_BASE 0x1E6E6200 /* CRT2 */ +#define AST_CRT3_BASE 0x1E6E6300 /* CRT3 */ +#define AST_XDMA_BASE 0x1E6E7000 /* XDMA */ +#define AST_MCTP_BASE 0x1E6E8000 /* MCTP */ +#define AST_ADC_BASE 0x1E6E9000 /* ADC */ +#define AST_ENTROPY_BASE 0x1E6EB000 /* Entropy */ +#define AST_BULK_BASE 0x1E6EB100 /* Bulk Decoder */ +#define AST_CMDQ_BASE 0x1E6EB180 /* CMDQ */ +#define AST_BITBLT_BASE 0x1E6EB200 /* Bitblt */ +#define AST_RLE_BASE 0x1E6EB300 /* RLE */ +#define AST_EGFX_BASE 0x1E6EB400 /* EGFX */ +#define AST_VMASK_BASE 0x1E6EB600 /* VMASK */ +#define AST_GMASK_BASE 0x1E6EB680 /* GMASK */ + +#define AST_EGFX_SYS_BASE 0x1E6EB700 /* EGFXSYS*/ + +#define AST_LPC_PLUS_BASE 0x1E6EC000 /* LPC+ */ +#define AST_PCIE_PLDA_BASE 0x1E6ED000 /* PCIE PLDA Bridge */ +#define AST_ESPI_BASE 0x1E6EE000 /* e-SPI */ +#define AST_BSRAM_BASE 0x1E6EF000 /* Battery Backup SRAM */ +#define AST_P2X_BASE 0x1E6F0000 /* P2X */ + +#define AST_VIDEO_BASE 0x1E700000 /* VIDEO ENGINE */ +#define AST_SRAM_BASE 0x1E720000 /* SRAM */ +#define AST_SDHC_BASE 0x1E740000 /* SD */ +#define AST_2D_BASE 0x1E760000 /* 2D */ +#define AST_GPIO_BASE 0x1E780000 /* GPIO */ +#define AST_SGPIO_BASE 0x1E780200 /* SGPIO */ +#define AST_SGPIO_S_BASE 0x1E780300 /* SGPIO Slave*/ +#define AST_RTC_BASE 0x1E781000 /* RTC */ +#define AST_TIMER_BASE 0x1E782000 /* TIMER #0~2*/ +#define AST_UART1_BASE 0x1E783000 /* UART1 */ +#define AST_UART0_BASE 0x1E784000 /* UART5 */ +#define AST_WDT_BASE 0x1E785000 /* WDT */ +#define AST_PWM_BASE 0x1E786000 /* PWM */ +#define AST_VUART0_BASE 0x1E787000 /* VUART1 */ +#define AST_PUART_BASE 0x1E788000 /* PUART */ +#define AST_LPC_BASE 0x1E789000 /* LPC */ +#define AST_MBX_BASE 0x1E789200 /* Mailbox */ +#define AST_I2C_BASE 0x1E78A000 /* I2C */ +#define AST_PECI_BASE 0x1E78B000 /* PECI */ +#define AST_PCIARBITER_BASE 0x1E78C000 /* PCI ARBITER */ +#define AST_UART2_BASE 0x1E78D000 /* UART2 */ +#define AST_UART3_BASE 0x1E78E000 /* UART3 */ +#define AST_UART4_BASE 0x1E78F000 /* UART4 */ +#define AST_UART5_BASE 0x1E790000 /* UART6 */ +#define AST_UART6_BASE 0x1E791000 /* UART7 */ +#define AST_UART7_BASE 0x1E792000 /* UART8 */ +#define AST_UART8_BASE 0x1E793000 /* UART9 */ +#define AST_UART9_BASE 0x1E794000 /* UART10 */ +#define AST_UART10_BASE 0x1E795000 /* UART11 */ +#define AST_UART11_BASE 0x1E796000 /* UART12 */ +#define AST_UART12_BASE 0x1E797000 /* UART13 */ +#define AST_UART_SDMA_BASE 0x1E79E000 /* UART SDMA */ + +#define AST_H264_BASE 0x1E7C0000 /* H.264 */ +#define AST_FORMATTER_BASE 0x1E7C2100 /* Formatter */ + + +#define AST_FMC_CS0_BASE 0x20000000 /* CS0 */ +#define AST_FMC_CS1_BASE 0x28000000 /* CS1 */ +#define AST_FMC_CS2_BASE 0x2a000000 /* CS2 */ + +#define AST_SPI0_CS0_BASE 0x30000000 /* SPI 2 Flash CS 0 Memory */ +#define AST_SPI0_CS1_BASE 0x32000000 /* SPI 2 Flash CS 1 Memory */ + +#define AST_SPI1_CS0_BASE 0x38000000 /* SPI 3 Flash CS 0 Memory */ +#define AST_SPI1_CS1_BASE 0x3a000000 /* SPI 3 Flash CS 1 Memory */ + +#define AST_LPC_BRIDGE 0x60000000 +#define AST_LPC_PLUS_BRIDGE 0x70000000 + +#define AST_PCIE_WIN_BASE 0x70000000 +#define AST_PCIE_WIN_SIZE 0x10000000 + +#ifdef CONFIG_AST_VIDEO +#define ASR_VIDEO_MEM_SIZE 0x2800000 /* 40MB */ +#define ASR_VIDEO_MEM (AST_DRAM_BASE + (SZ_8M*10)) /* (AST_DRAM_BASE + SZ_256M) */ + +#define AST_CRT0_MEM_SIZE SZ_8M +#define AST_CRT0_MEM_BASE (ASR_VIDEO_MEM + ASR_VIDEO_MEM_SIZE) +#else + +#define AST_CRT0_MEM_SIZE SZ_8M +#define AST_CRT0_MEM_BASE (AST_DRAM_BASE + 0x8000000) //from 128M +#endif + +#define AST_CURSOR0_MEM_SIZE SZ_1M +#define AST_CURSOR0_MEM_BASE (AST_CRT0_MEM_BASE + AST_CRT0_MEM_SIZE) + +#define AST_CRT1_MEM_SIZE SZ_8M +#define AST_CRT1_MEM_BASE (AST_CURSOR0_MEM_BASE + AST_CURSOR0_MEM_SIZE) + +#define AST_CRT2_MEM_SIZE SZ_8M +#define AST_CRT2_MEM_BASE (AST_CRT1_MEM_BASE + AST_CRT1_MEM_SIZE) + +#define AST_CRT3_MEM_SIZE SZ_8M +#define AST_CRT3_MEM_BASE (AST_CRT2_MEM_BASE + AST_CRT2_MEM_SIZE) + +#define AST_BULK_STREAM_MEM_SIZE SZ_8M /* 4Mb for bulk , 4Mb for history */ +#define AST_BULK_STREAM_MEM_BASE (AST_CRT3_MEM_BASE + AST_CRT3_MEM_SIZE) + +#define AST_GRAPHIC_STREAM_MEM_SIZE SZ_8M /* 4Mb for bulk , 4Mb for history */ +#define AST_GRAPHIC_STREAM_MEM_BASE (AST_BULK_STREAM_MEM_BASE + AST_BULK_STREAM_MEM_SIZE) + +#define AST_ENTROPY_MEM_SIZE SZ_4M +#define AST_ENTROPY_MEM_BASE (AST_GRAPHIC_STREAM_MEM_BASE + AST_GRAPHIC_STREAM_MEM_SIZE) + +#define AST_CMDQ_MEM_SIZE SZ_2M +#define AST_CMDQ_MEM_BASE (AST_ENTROPY_MEM_BASE + AST_ENTROPY_MEM_SIZE) + +#define AST_VMASK_MEM_SIZE SZ_1M +#define AST_VMASK_MEM_BASE (AST_CMDQ_MEM_BASE + AST_CMDQ_MEM_SIZE) + +#define AST_GMASK_MEM_SIZE SZ_1M +#define AST_GMASK_MEM_BASE (AST_VMASK_MEM_BASE + AST_VMASK_MEM_SIZE) + +#define AST_H264_MEM_SIZE 0x1100000 /* 11MB : BS 8MB + fifo 3 * 3MB */ +#define AST_H264_MEM_BASE (AST_GMASK_MEM_BASE + AST_GMASK_MEM_SIZE) + +#define AST_FORMATTER_MEM_SIZE 0xC00000 /* 12MB */ +#define AST_FORMATTER_MEM_BASE (AST_H264_MEM_BASE + AST_H264_MEM_SIZE) + + +#endif diff --git a/arch/arm/include/asm/arch-aspeed/ast_scu.h b/arch/arm/include/asm/arch-aspeed/ast_scu.h new file mode 100644 index 0000000000..d248416432 --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/ast_scu.h @@ -0,0 +1,48 @@ +/******************************************************************************* + * File Name : arch/arm/mach-aspeed/include/plat/ast-scu.h + * Author : Ryan Chen + * Description : AST SCU Service Header + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 + * USA + * + * History : + * 1. 2012/08/03 Ryan Chen create this file + * + ******************************************************************************/ + +#ifndef __AST_SCU_H +#define __AST_SCU_H + +extern void ast_scu_show_system_info (void); +extern void ast_scu_sys_rest_info(void); +extern void ast_scu_security_info(void); +extern u32 ast_scu_revision_id(void); +extern u32 ast_scu_get_vga_memsize(void); +extern void ast_scu_get_who_init_dram(void); + +extern u32 ast_get_clk_source(void); +extern u32 ast_get_h_pll_clk(void); +extern u32 ast_get_ahbclk(void); + +extern u32 ast_scu_get_vga_memsize(void); + +extern void ast_scu_init_eth(u8 num); +extern void ast_scu_multi_func_eth(u8 num); +extern void ast_scu_multi_func_romcs(u8 num); + +#endif diff --git a/arch/arm/include/asm/arch-aspeed/platform.h b/arch/arm/include/asm/arch-aspeed/platform.h new file mode 100644 index 0000000000..1c02914fcb --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/platform.h @@ -0,0 +1,34 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST_PLATFORM_H +#define _AST_PLATFORM_H + +#include + +#define AST_PLL_25MHZ 25000000 +#define AST_PLL_24MHZ 24000000 +#define AST_PLL_12MHZ 12000000 + +#if defined(CONFIG_ARCH_AST2400) +#include +#elif defined(AST_SOC_G5) +#include +#else +#err "No define for platform.h" +#endif + +#endif diff --git a/arch/arm/include/asm/arch-aspeed/regs-ahbc.h b/arch/arm/include/asm/arch-aspeed/regs-ahbc.h new file mode 100644 index 0000000000..66e29839e8 --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/regs-ahbc.h @@ -0,0 +1,38 @@ +/* arch/arm/mach-aspeed/include/mach/regs-ahbc.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * History : + * 1. 2012/12/29 Ryan Chen Create + * + ******************************************************************************/ +#ifndef __AST_AHBC_H +#define __AST_AHBC_H + +#include + +/* Registers for AHBC */ +#define AST_AHBC_PROTECT 0x00 /* Protection Key Register */ +#define AST_AHBC_PRIORITY_CTRL 0x80 /* Priority Cortrol Register */ +#define AST_AHBC_ADDR_REMAP 0x8C /* Address Remapping Register */ + +/* AST_AHBC_PROTECT 0x00 Protection Key Register */ +#define AHBC_PROTECT_UNLOCK 0xAEED1A03 + +/* AST_AHBC_ADDR_REMAP 0x8C Address Remapping Register */ +#define AHBC_PCI_REMAP1 (1 << 5) +#define AHBC_PCI_REMAP0 (1 << 4) + +#if defined(AST_SOC_G5) +#define AHBC_PCIE_MAP (1 << 5) +#define AHBC_LPC_PLUS_MAP (1 << 4) +#else +#define AHBC_BOOT_REMAP 1 +#endif + + +#endif diff --git a/arch/arm/include/asm/arch-aspeed/regs-scu.h b/arch/arm/include/asm/arch-aspeed/regs-scu.h new file mode 100644 index 0000000000..b714fa9234 --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/regs-scu.h @@ -0,0 +1,952 @@ +/* arch/arm/mach-aspeed/include/mach/regs-scu.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * History : + * 1. 2012/12/29 Ryan Chen Create + * +********************************************************************************/ +#ifndef __AST_REGS_SCU_H +#define __AST_REGS_SCU_H 1 + +#include + +/* + * Register for SCU + */ +#define AST_SCU_PROTECT 0x00 /* protection key register */ +#define AST_SCU_RESET 0x04 /* system reset control register */ +#define AST_SCU_RESET2 0xD4 /* Reset Control register set 2*/ +#define AST_SCU_CLK_SEL 0x08 /* clock selection register */ +#define AST_SCU_CLK_SEL2 0xD8 /* clock selection register Set 2*/ +#define AST_SCU_CLK_STOP 0x0C /* clock stop control register */ +#define AST_SCU_CLK_STOP2 0xDC /* clock stop control register set 2*/ +#define AST_SCU_COUNT_CTRL 0x10 /* frequency counter control register */ +#define AST_SCU_COUNT_VAL 0x14 /* frequency counter measure register */ +#define AST_SCU_INTR_CTRL 0x18 /* Interrupt control and status register */ +#define AST_SCU_D2_PLL 0x1C /* D2-PLL Parameter register */ +#define AST_SCU_D2_PLL_EXTEND 0x13C /* D2-PLL Extender Parameter register */ +#define AST_SCU_M_PLL 0x20 /* M-PLL Parameter register */ +#define AST_SCU_H_PLL 0x24 /* H-PLL Parameter register */ +#define AST_SCU_MH_PLL_EXTEND 0x148 /* Extended Parameter of M/H-PLL register */ +#ifdef AST_SOC_G5 +#define AST_SCU_D_PLL 0x28 /* D-PLL Parameter register */ +#define AST_SCU_D_PLL_EXTEND0 0x130 /* D-PLL Extended Parameter register */ +#define AST_SCU_D_PLL_EXTEND1 0x134 /* D-PLL Extended Parameter register */ +#define AST_SCU_D_PLL_EXTEND2 0x138 /* D-PLL Extended Parameter register */ +#else +#define AST_SCU_FREQ_LIMIT 0x28 /* frequency counter comparsion register */ +#endif +#define AST_SCU_MISC1_CTRL 0x2C /* Misc. Control register */ +#define AST_SCU_PCI_CONF1 0x30 /* PCI configuration setting register#1 */ +#define AST_SCU_PCI_CONF2 0x34 /* PCI configuration setting register#2 */ +#define AST_SCU_PCI_CONF3 0x38 /* PCI configuration setting register#3 */ +#define AST_SCU_SYS_CTRL 0x3C /* System reset contrl/status register*/ +#define AST_SCU_SOC_SCRATCH0 0x40 /* SOC scratch 0~31 register */ +#define AST_SCU_SOC_SCRATCH1 0x44 /* SOC scratch 32~63 register */ +#define AST_SCU_VGA0 0x40 /* VGA fuction handshake register */ +#define AST_SCU_VGA1 0x44 /* VGA fuction handshake register */ +#define AST_SCU_MAC_CLK 0x48 /* MAC interface clock delay setting register */ +#define AST_SCU_MISC2_CTRL 0x4C /* Misc. 2 Control register */ +#define AST_SCU_VGA_SCRATCH0 0x50 /* VGA Scratch register */ +#define AST_SCU_VGA_SCRATCH1 0x54 /* VGA Scratch register */ +#define AST_SCU_VGA_SCRATCH2 0x58 /* VGA Scratch register */ +#define AST_SCU_VGA_SCRATCH3 0x5c /* VGA Scratch register */ +#define AST_SCU_VGA_SCRATCH4 0x60 /* VGA Scratch register */ +#define AST_SCU_VGA_SCRATCH5 0x64 /* VGA Scratch register */ +#define AST_SCU_VGA_SCRATCH6 0x68 /* VGA Scratch register */ +#define AST_SCU_VGA_SCRATCH7 0x6c /* VGA Scratch register */ +#define AST_SCU_HW_STRAP1 0x70 /* hardware strapping register */ +#define AST_SCU_RAMDOM_GEN 0x74 /* random number generator register */ + + +#define AST_SCU_RAMDOM_DATA 0x78 /* random number generator data output*/ +#define AST_SCU_REVISION_ID 0x7C /* Silicon revision ID register */ +#define AST_SCU_FUN_PIN_CTRL1 0x80 /* Multi-function Pin Control#1*/ +#define AST_SCU_FUN_PIN_CTRL2 0x84 /* Multi-function Pin Control#2*/ +#define AST_SCU_FUN_PIN_CTRL3 0x88 /* Multi-function Pin Control#3*/ +#define AST_SCU_FUN_PIN_CTRL4 0x8C /* Multi-function Pin Control#4*/ +#define AST_SCU_FUN_PIN_CTRL5 0x90 /* Multi-function Pin Control#5*/ +#define AST_SCU_FUN_PIN_CTRL6 0x94 /* Multi-function Pin Control#6*/ +#define AST_SCU_WDT_RESET 0x9C /* Watchdog Reset Selection */ +#define AST_SCU_FUN_PIN_CTRL7 0xA0 /* Multi-function Pin Control#7*/ +#define AST_SCU_FUN_PIN_CTRL8 0xA4 /* Multi-function Pin Control#8*/ +#define AST_SCU_FUN_PIN_CTRL9 0xA8 /* Multi-function Pin Control#9*/ +#define AST_SCU_MAC_CLK_DELAY_100M 0xB8 /* MAC interface clock delay 100M setting*/ +#define AST_SCU_MAC_CLK_DELAY_10M 0xBC /* MAC interface clock delay 10M setting*/ +#define AST_SCU_PWR_SAVING_EN 0xC0 /* Power Saving Wakeup Enable*/ +#define AST_SCU_PWR_SAVING_CTRL 0xC4 /* Power Saving Wakeup Control*/ +#define AST_SCU_HW_STRAP2 0xD0 /* Haardware strapping register set 2*/ +#define AST_SCU_COUNTER4 0xE0 /* SCU Free Run Counter Read Back #4*/ +#define AST_SCU_COUNTER4_EXT 0xE4 /* SCU Free Run Counter Extended Read Back #4*/ + +#define AST_SCU_DPLL_PAR0 0x130 +#define AST_SCU_DPLL_PAR1 0x134 +#define AST_SCU_DPLL_PAR2 0x138 + +#define AST_SCU_OTP0 0x150 +#define AST_SCU_OTP1 0x154 +#define AST_SCU_OTP2 0x158 +#define AST_SCU_OTP3 0x15C + +#define AST_SCU_UART24_REF 0x160 /* Generate UART 24Mhz Ref from H-PLL when CLKIN is 25Mhz */ +#define AST_SCU_PCIE_CONFIG_SET 0x180 /* PCI-E Configuration Setting Control Register */ +#define AST_SCU_BMC_MMIO_DEC 0x184 /* BMC MMIO Decode Setting Register */ +#define AST_SCU_DEC_AREA1 0x188 /* 1st relocated controller decode area location */ +#define AST_SCU_DEC_AREA2 0x18C /* 2nd relocated controller decode area location */ +#define AST_SCU_MBOX_DEC_AREA 0x190 /* Mailbox decode area location*/ +#define AST_SCU_SRAM_DEC_AREA0 0x194 /* Shared SRAM area decode location*/ +#define AST_SCU_SRAM_DEC_AREA1 0x198 /* Shared SRAM area decode location*/ +#define AST_SCU_BMC_CLASS 0x19C /* BMC device class code and revision ID */ +#define AST_SCU_BMC_DEV_ID 0x1A4 /* BMC device ID */ + +#define AST_SCU_MAC_CLK_DUTY 0x1DC /* Clock Duty Selection */ + + +/* AST_SCU_PROTECT 0x00 - protection key register */ +#define SCU_PROTECT_UNLOCK 0x1688A8A8 + +/* AST_SCU_RESET 0x04 - system reset control register */ +#define SCU_RESET_H264 (0x1 << 26) +#define SCU_RESET_XDMA (0x1 << 25) +#define SCU_RESET_MCTP (0x1 << 24) +#define SCU_RESET_P2X (0x1 << 24) +#define SCU_RESET_ADC (0x1 << 23) +#define SCU_RESET_JTAG (0x1 << 22) +#ifdef AST_SOC_G5 +#define SCU_RESET_PCIE_DIR (0x1 << 21) +#define SCU_RESET_PCIE (0x1 << 19) +#else +#define SCU_PWAKE_PIN_EN (0x1 << 20) +#define SCU_PWAKE_PIN_OUT (0x1 << 19) +#endif +#define SCU_RESET_MIC (0x1 << 18) +#define SCU_RESET_RFX (0x1 << 17) +#define SCU_RESET_SD (0x1 << 16) +#define SCU_RESET_USB11 (0x1 << 15) +#define SCU_RESET_USB20 (0x1 << 14) +#define SCU_RESET_CRT (0x1 << 13) +#define SCU_RESET_MAC1 (0x1 << 12) +#define SCU_RESET_MAC0 (0x1 << 11) +#define SCU_RESET_PECI (0x1 << 10) +#define SCU_RESET_PWM (0x1 << 9) +#define SCU_PCI_VGA_DIS (0x1 << 8) +#define SCU_RESET_2D (0x1 << 7) +#define SCU_RESET_VIDEO (0x1 << 6) +#define SCU_RESET_LPC (0x1 << 5) +#define SCU_RESET_HACE (0x1 << 4) +#define SCU_RESET_USB_P1 (0x1 << 3) +#define SCU_RESET_I2C (0x1 << 2) +#define SCU_RESET_AHB (0x1 << 1) +#define SCU_RESET_SRAM_CTRL (0x1 << 0) + +/* AST_SCU_RESET2 0xD4 - Reset Control register set 2 */ +#define SCU_RESET_CRT3 (0x1 << 8) +#define SCU_RESET_CRT2 (0x1 << 7) +#define SCU_RESET_CRT1 (0x1 << 6) +#define SCU_RESET_CRT0 (0x1 << 5) +#define SCU_RESET_NIC1 (0x1 << 4) +#define SCU_RESET_NIC0 (0x1 << 3) +#define SCU_RESET_RFXDEC (0x1 << 2) +#define SCU_RESET_BITBLT (0x1 << 1) +#define SCU_RESET_RFXCMQ (0x1) + +/* AST_SCU_CLK_SEL 0x08 - clock selection register */ +#define SCU_CLK_VIDEO_SLOW_EN (0x1 << 31) +//G5 the same with RemoteFX EPDEC +#define SCU_CLK_VIDEO_SLOW_SET(x) (x << 28) +#define SCU_CLK_VIDEO_SLOW_MASK (0x7 << 28) +#define SCU_CLK_2D_ENG_GCLK_INVERT (0x1 << 27) // valid only at CRT mode SCU2C[7] +#define SCU_CLK_2D_ENG_THROT_EN (0x1 << 26) //valid only at CRT mode SCU2C[7] +#define SCU_PCLK_APB_DIV(x) (x << 23) +#define SCU_GET_PCLK_DIV(x) ((x >> 23) & 0x7) +#define SCU_PCLK_APB_DIV_MASK (0x7 << 23) //limitation on PCLK .. PCLK > 0.5*LCLK (33Mhz) +#define SCU_GET_LHCLK_DIV(x) ((x >> 20) & 0x7) +#define SCU_SET_LHCLK_DIV(x) (x << 20) +#define SCU_LHCLK_DIV_MASK (0x7 << 20) +#define SCU_LHCLK_SOURCE_EN (0x1 << 19) //0: ext , 1:internel +#define SCU_CLK_MAC_DIV(x) (x << 16) +#define SCU_CLK_MAC_MASK (0x7 << 16) +#define SCU_CLK_SD_EN (0x1 << 15) +#define SCU_CLK_VIDE0_SO_D2 (0x1 << 8) +#define SCU_CLK_SD_DIV(x) (x << 12) +#define SCU_CLK_SD_GET_DIV(x) ((x >> 12) & 0x7) +#define SCU_CLK_SD_MASK (0x7 << 12) +#if defined(AST_SOC_G5) +#define SCU_CRT_CLK_L_SOURCE (0x1 << 8) +#else +#define SCU_CLK_VIDEO_DELAY(x) (x << 8) +#define SCU_CLK_VIDEO_DELAY_MASK (0xf << 8) +#endif +#define SCU_CLK_CPU_AHB_SLOW_EN (0x1 << 7) +#define SCU_CLK_CPU_AHB_SLOW(x) (x << 4) +#define SCU_CLK_CPU_AHB_SLOW_MASK (0x7 << 4) +#define SCU_GET_AHB_SLOW_DIV(x) ((x >> 4) & 0x7) +#define SCU_ECLK_SOURCE(x) (x << 2) +#define SCU_ECLK_SOURCE_MASK (0x3 << 2) +#define SCU_CLK_CPU_AHB_SLOW_IDLE (0x1 << 1) +#define SCU_CLK_CPU_AHB_DYN_SLOW_EN (0x1 << 0) + +/* AST_SCU_CLK_SEL2 0xD8 - clock selection register Set 2 */ +#define SCU_VIDEO4_OUTPUT_CLK_INVERT (1 << 29) +#define SCU_VIDEO4_OUTPUT_CLK_DELAY(x) (x << 24) +#define SCU_VIDEO4_OUTPUT_CLK_DELAY_MASK (0x1f << 24) +#define SCU_VIDEO3_OUTPUT_CLK_INVERT (1 << 23) +#define SCU_VIDEO3_OUTPUT_CLK_DELAY(x) (x << 18) +#define SCU_VIDEO3_OUTPUT_CLK_DELAY_MASK (0x1f << 18) +#define SCU_VIDEO2_OUTPUT_CLK_INVERT (1 << 17) +#define SCU_VIDEO2_OUTPUT_CLK_DELAY(x) (x << 12) +#define SCU_VIDEO2_OUTPUT_CLK_DELAY_MASK (0x1f << 12) +#define SCU_VIDEO1_OUTPUT_CLK_INVERT (1 << 11) +#define SCU_VIDEO1_OUTPUT_CLK_DELAY(x) (x << 6) +#define SCU_VIDEO1_OUTPUT_CLK_DELAY_MASK (0x1f << 6) +#define SCU_GET_H264CLK_DIV(x) ((x & 0x7) >> 3) +#define SCU_SET_H264CLK_DIV(x) (x << 3) +#define SCU_H264CLK_MASK (7 << 3) +#define SCU_GET_BCLK_DIV(x) (x & 0x7) +#define SCU_SET_BCLK_DIV(x) (x) + + +/* AST_SCU_CLK_STOP 0x0C - clock stop control register */ +#define SCU_LHCLK_STOP_EN (0x1 << 28) +#define SCU_SDCLK_STOP_EN (0x1 << 27) +#define SCU_UART4CLK_STOP_EN (0x1 << 26) +#define SCU_UART3CLK_STOP_EN (0x1 << 25) +#define SCU_RSACLK_STOP_EN (0x1 << 24) +//bit 23 must keep 1 +#define SCU_H264_STOP_EN (0x1 << 22) +#define SCU_MAC1CLK_STOP_EN (0x1 << 21) +#define SCU_MAC0CLK_STOP_EN (0x1 << 20) +//bit 19 must keep 1 +#if defined(AST_SOC_G5) +#define SCU_ESPI_CLK_STOP_EN (0x1 << 19) +#endif + +#define SCU_RFX_CLK_STOP_EN (0x1 << 18) +#define SCU_UART5CLK_STOP_EN (0x1 << 17) +#define SCU_UART2CLK_STOP_EN (0x1 << 16) +#define SCU_UART1CLK_STOP_EN (0x1 << 15) +#define SCU_USB20_PHY_CLK_EN (0x1 << 14) +#define SCU_YCLK_STOP_EN (0x1 << 13) +#define SCU_D2CLK_STOP_EN (0x1 << 10) +#define SCU_USB11CLK_STOP_EN (0x1 << 9) +#define SCU_LCLK_STOP_EN (0x1 << 8) +#define SCU_USB_P1_STOP_EN (0x1 << 7) +#define SCU_REFCLK_STOP_EN (0x1 << 6) +#define SCU_DCLK_STOP_EN (0x1 << 5) +#define SCU_SACLK_STOP_EN (0x1 << 4) +#define SCU_VCLK_STOP_EN (0x1 << 3) +#define SCU_VCLK_STOP_EN (0x1 << 3) +#define SCU_MCLK_STOP_EN (0x1 << 2) +#define SCU_GCLK_STOP_EN (0x1 << 1) +#define SCU_ECLK_STOP_EN (0x1 << 0) + +/* AST_SCU_CLK_STOP2 0xDC - clock stop control register set 2*/ +#define SCU_NIC2_STOP_EN (0x1 << 10) +#define SCU_NIC1_STOP_EN (0x1 << 9) +#define SCU_CMQCLK_STOP (0x1 << 8) +#define SCU_RFXCLK_STOP (0x1 << 7) +#define SCU_BITBLTCLK_STOP (0x1 << 6) +/* bit 6*/ +#define SCU_UART_DIV13 (0x1 << 4) +#define SCU_UARTXCLK_STOP (0x1 << 3) +#define SCU_D4CLK_STOP (0x1 << 2) +#define SCU_D3CLK_STOP (0x1 << 1) +#define SCU_D2CLK_STOP (0x1) + +/* AST_SCU_COUNT_CTRL 0x10 - frequency counter control register */ +#if defined(AST_SOC_G5) +#define SCU_OSC_OUT_EN (0x1 << 8) +#endif +#define SCU_FREQ_COMP_RESULT (0x1 << 7) +#define SCU_FREQ_MEASU_FINISH (0x1 << 6) +#define SCU_FREQ_SOURCE_FOR_MEASU(x) (x << 2) +#define SCU_FREQ_SOURCE_FOR_MEASU_MASK (0xf << 2) + +#if defined(AST_SOC_G5) +#define SCU_SOURCE_PCLK 0xf +#define SCU_SOURCE_VPACLK 0xe +#define SCU_SOURCE_VPBCLK 0xd +#define SCU_SOURCE_12M 0xc +#define SCU_SOURCE_LCLK 0xb +#define SCU_SOURCE_GRCLK 0xa +#define SCU_SOURCE_HCLK 0x9 +#define SCU_SOURCE_MCLK 0x8 +#define SCU_SOURCE_BCLK 0x7 +#define SCU_SOURCE_XPCLK 0x6 +#define SCU_SOURCE_D2_CLK 0x5 +#define SCU_SOURCE_D_CLK 0x4 +#define SCU_SOURCE_DLY32 0x3 +#define SCU_SOURCE_DLY16 0x2 +#define SCU_SOURCE_NAND 0x1 +#define SCU_SOURCE_DEL_CELL 0x0 +#else /* ! AST_SOC_G5 */ +#define SCU_SOURCE_6M 0xf +#define SCU_SOURCE_12M 0xe +#define SCU_SOURCE_I2SM_CLK 0xd +#define SCU_SOURCE_H_CLK 0xc +#define SCU_SOURCE_B_CLK 0xb +#define SCU_SOURCE_D2_PLL 0xa + +#define SCU_SOURCE_VIDEO_CLK 0x7 +#define SCU_SOURCE_LPC_CLK 0x6 +#define SCU_SOURCE_I2S_CLK 0x5 +#define SCU_SOURCE_M_CLK 0x4 +#define SCU_SOURCE_SALI_CLK 0x3 +#define SCU_SOURCE_D_PLL 0x2 +#define SCU_SOURCE_NAND 0x1 +#define SCU_SOURCE_DEL_CELL 0x0 +#endif /* AST_SOC_G5 */ +#define SCU_OSC_COUNT_EN (0x1 << 1) +#define SCU_RING_OSC_EN (0x1 << 0) + + +/* AST_SCU_INTR_CTRL 0x18 - Interrupt register */ +#define INTR_LPC_H_L_RESET (0x1 << 21) +#define INTR_LPC_L_H_RESET (0x1 << 20) +#define INTR_PCIE_H_L_RESET (0x1 << 19) +#define INTR_PCIE_L_H_RESET (0x1 << 18) +#define INTR_VGA_SCRATCH_CHANGE (0x1 << 17) +#define INTR_VGA_CURSOR_CHANGE (0x1 << 16) +#define INTR_ISSUE_MSI (0x1 << 6) +#define INTR_LPC_H_L_RESET_EN (0x1 << 5) +#define INTR_LPC_L_H_RESET_EN (0x1 << 4) +#define INTR_PCIE_H_L_RESET_EN (0x1 << 3) +#define INTR_PCIE_L_H_RESET_EN (0x1 << 2) +#define INTR_VGA_SCRATCH_CHANGE_EN (0x1 << 1) +#define INTR_VGA_CURSOR_CHANGE_EN (0x1 << 0) + +/* AST_SCU_D2_PLL 0x1C - D2-PLL Parameter register */ +#ifdef AST_SOC_G5 +#define SCU_D2_PLL_SET_ODNUM(x) (x << 19) +#define SCU_D2_PLL_GET_ODNUM(x) ((x >> 19) & 0x3) +#define SCU_D2_PLL_OD_MASK (0x3 << 19) +#define SCU_D2_PLL_SET_PNUM(x) (x << 13) +#define SCU_D2_PLL_GET_PNUM(x) ((x >>13)&0x3f) +#define SCU_D2_PLL_PNUM_MASK (0x3f << 13) +#define SCU_D2_PLL_SET_NNUM(x) (x << 8) +#define SCU_D2_PLL_GET_NNUM(x) ((x >>8)&0x1f) +#define SCU_D2_PLL_NNUM_MASK (0x1f << 8) +#define SCU_D2_PLL_SET_MNUM(x) (x) +#define SCU_D2_PLL_GET_MNUM(x) (x & 0xff) +#define SCU_D2_PLL_MNUM_MASK (0xff) + +/* AST_SCU_D2_PLL_EXTEND 0x13C - D2-PLL Extender Parameter register */ +#define SCU_D2_PLL_PARAMETER0(x) ((x) << 5) +#define SCU_D2_PLL_SET_MODE(x) ((x) << 3) +#define SCU_D2_PLL_GET_MODE(x) (((x) >> 3) & 0x3) +#define SCU_D2_PLL_RESET (0x1 << 2) +#define SCU_D2_PLL_BYPASS (0x1 << 1) +#define SCU_D2_PLL_OFF (0x1) +#else /* ! AST_SOC_G5 */ +#define SCU_D2_PLL_SET_PD2(x) (x << 19) +#define SCU_D2_PLL_GET_PD2(x) ((x >> 19)&0x7) +#define SCU_D2_PLL_PD2_MASK (0x7 << 19) +#define SCU_D2_PLL_BYPASS (0x1 << 18) +#define SCU_D2_PLL_OFF (0x1 << 17) +#define SCU_D2_PLL_SET_PD(x) (x << 15) +#define SCU_D2_PLL_GET_PD(x) ((x >> 15) &0x3) +#define SCU_D2_PLL_PD_MASK (0x3 << 15) +#define SCU_D2_PLL_SET_OD(x) (x << 13) +#define SCU_D2_PLL_GET_OD(x) ((x >> 13) & 0x3) +#define SCU_D2_PLL_OD_MASK (0x3 << 13) +#define SCU_D2_PLL_SET_DENUM(x) (x << 8) +#define SCU_D2_PLL_GET_DENUM(x) ((x >>8)&0x1f) +#define SCU_D2_PLL_DENUM_MASK (0x1f << 8) +#define SCU_D2_PLL_SET_NUM(x) (x) +#define SCU_D2_PLL_GET_NUM(x) (x & 0xff) +#define SCU_D2_PLL_NUM_MASK (0xff) +#endif /* AST_SOC_G5 */ + +/* AST_SCU_M_PLL 0x20 - M-PLL Parameter register */ +#ifdef AST_SOC_G5 +#define SCU_M_PLL_RESET (0x1 << 21) +#define SCU_M_PLL_BYPASS (0x1 << 20) +#define SCU_M_PLL_OFF (0x1 << 19) +#define SCU_M_PLL_GET_PDNUM(x) ((x >> 13) & 0x3f) +#define SCU_M_PLL_GET_MNUM(x) ((x >> 5) & 0xff) +#define SCU_M_PLL_GET_NNUM(x) (x & 0x1f) +#else /* ! AST_SOC_G5 */ +#define SCU_M_PLL_BYPASS (0x1 << 17) +#define SCU_M_PLL_OFF (0x1 << 16) +#define SCU_M_PLL_NUM(x) (x << 5) +#define SCU_M_PLL_GET_NUM(x) ((x >> 5) & 0x3f) +#define SCU_M_PLL_NUM_MASK (0x3f << 5) +#define SCU_M_PLL_OUT_DIV (0x1 << 4) +#define SCU_M_PLL_GET_DIV(x) ((x >> 4) & 0x1) +#define SCU_M_PLL_DENUM(x) (x) +#define SCU_M_PLL_GET_DENUM(x) (x & 0xf) +#endif /* AST_SOC_G5 */ + +/* AST_SCU_H_PLL 0x24 - H-PLL Parameter register */ +#ifdef AST_SOC_G5 +#define SCU_H_PLL_PARAMETER0(x) ((x) << 22) +#define SCU_H_PLL_GET_PARAMETER0(x) ((x >> 22) & 0x3ff) +#define SCU_H_PLL_PARAMETER0_MASK(x) (0x3ff << 22) +#define SCU_H_PLL_GET_PARAMETER0(x) ((x >> 22) & 0x3ff) +#define SCU_H_PLL_RESET (0x1 << 21) +#define SCU_H_PLL_BYPASS_EN (0x1 << 20) +#define SCU_H_PLL_OFF (0x1 << 19) +#define SCU_H_PLL_PNUM(x) (x << 13) +#define SCU_H_PLL_GET_PNUM(x) ((x >> 13) & 0x3f) +#define SCU_H_PLL_PNUM_MASK (0x3f << 13) +#define SCU_H_PLL_MNUM(x) (x << 5) +#define SCU_H_PLL_GET_MNUM(x) ((x >> 5) & 0xff) +#define SCU_H_PLL_MNUM_MASK (0xff << 5) +#define SCU_H_PLL_NNUM(x) (x) +#define SCU_H_PLL_GET_NNUM(x) (x & 0xf) +#define SCU_H_PLL_NNUM_MASK (0xf) +#else /* ! AST_SOC_G5 */ +#define SCU_H_PLL_PARAMETER (0x1 << 18) +#define SCU_H_PLL_BYPASS_EN (0x1 << 17) +#define SCU_H_PLL_OFF (0x1 << 16) +#define SCU_H_PLL_NUM(x) (x << 5) +#define SCU_H_PLL_GET_NUM(x) ((x >> 5) & 0x3f) +#define SCU_H_PLL_NUM_MASK (0x3f << 5) +#define SCU_H_PLL_OUT_DIV (0x1 << 4) +#define SCU_H_PLL_GET_DIV(x) ((x >> 4) & 0x1) +#define SCU_H_PLL_DENUM(x) (x) +#define SCU_H_PLL_GET_DENUM(x) (x & 0xf) +#define SCU_H_PLL_DENUM_MASK (0xf) +#endif /* AST_SOC_G5 */ + +/* AST_SCU_MH_PLL_EXTEND 0x148 - Extended Parameter of M/H-PLL register */ +#define SCU_H_PLL_GET_PARAMETER1(x) ((x >> 16) & 0x3f) +#define SCU_H_PLL_PARAMETER1_MASK(x) (0x3f << 16) +#define SCU_M_PLL_GET_PARAMETER1(x) (x & 0x3f) +#define SCU_M_PLL_PARAMETER1_MASK(x) (0x3f) + +#ifdef AST_SOC_G5 +/* AST_SCU_D_PLL 0x28 - D-PLL Parameter register */ +#define SCU_D_PLL_GET_SIP(x) ((x >>27) & 0x1f) +#define SCU_D_PLL_GET_SIC(x) ((x >>22) & 0x1f) +#define SCU_D_PLL_GET_ODNUM(x) ((x >>19) & 0x7) +#define SCU_D_PLL_GET_PNUM(x) ((x >>13) & 0x3f) +#define SCU_D_PLL_GET_NNUM(x) ((x >>8) & 0x1f) +#define SCU_D_PLL_GET_MNUM(x) (x & 0xff) + +/* AST_SCU_D_PLL_EXTEND 0x130 - D-PLL Extended Parameter register */ +#define SCU_D_PLL_SET_MODE(x) ((x & 0x3) << 3) +#define SCU_D_PLL_RESET (0x1 << 2) +#define SCU_D_PLL_BYPASS (0x1 << 1) +#define SCU_D_PLL_OFF (0x1) + +#else /* ! AST_SOC_G5 */ +/* AST_SCU_FREQ_LIMIT 0x28 - frequency counter comparsion register */ +#define SCU_FREQ_U_LIMIT(x) (x << 16) +#define SCU_FREQ_U_LIMIT_MASK (0x3fff << 16) +#define SCU_FREQ_L_LIMIT(x) (x) +#define SCU_FREQ_L_LIMIT_MASK (0x3fff) +#endif /* AST_SOC_G5 */ + +/* AST_SCU_MISC1_CTRL 0x2C - Misc. Control register */ +#define SCU_MISC_JTAG_MASTER_DIS (0x1 << 26) +#define SCU_MISC_DRAM_W_P2A_DIS (0x1 << 25) +#define SCU_MISC_SPI_W_P2A_DIS (0x1 << 24) +#define SCU_MISC_SOC_W_P2A_DIS (0x1 << 23) +#define SCU_MISC_FLASH_W_P2A_DIS (0x1 << 22) +#ifdef AST_SOC_G5 +#define SCU_MISC_CRT_CLK_H_SOURCE (0x1 << 21) +#define SCU_MISC_D_PLL_SOURCE (0x1 << 20) +#else +#define SCU_MISC_D_PLL_ASSIGN(x) (x << 20) +#define SCU_MISC_D_PLL_ASSIGN_MASK (0x3 << 20) +#endif +#define SCU_MISC_VGA_CONFIG_PREFETCH (0x1 << 19) +#define SCU_MISC_DVO_SOURCE_CRT (0x1 << 18) //0:VGA , 1:CRT +#define SCU_MISC_DAC_MASK (0x3 << 16) +#define SCU_MISC_SET_DAC_SOURCE(x) (x << 16) +#define SCU_MISC_DAC_SOURCE_CRT (0x1 << 16) //00 VGA, 01: CRT, 1x: PASS-Through DVO +#define SCU_MISC_DAC_SOURCE_MASK (0x3 << 16) +#define SCU_MISC_JTAG_TO_PCIE_EN (0x1 << 15) +#define SCU_MISC_JTAG__M_TO_PCIE_EN (0x1 << 14) +#define SCU_MISC_VUART_TO_CTRL (0x1 << 13) +#define SCU_MISC_DIV13_EN (0x1 << 12) +#define SCU_MISC_Y_CLK_INVERT (0x1 << 11) +#define SCU_MISC_OUT_DELAY (0x1 << 9) +#define SCU_MISC_PCI_TO_AHB_DIS (0x1 << 8) +#define SCU_MISC_2D_CRT_EN (0x1 << 7) +#define SCU_MISC_VGA_CRT_DIS (0x1 << 6) +#define SCU_MISC_VGA_REG_ACCESS_EN (0x1 << 5) +#define SCU_MISC_D2_PLL_DIS (0x1 << 4) +#define SCU_MISC_DAC_DIS (0x1 << 3) +#define SCU_MISC_D_PLL_DIS (0x1 << 2) +#define SCU_MISC_OSC_CLK_OUT_PIN (0x1 << 1) +#define SCU_MISC_LPC_TO_SPI_DIS (0x1 << 0) + +/* AST_SCU_PCI_CONF1 0x30 - PCI configuration setting register#1 */ +#define SCU_PCI_DEVICE_ID(x) (x << 16) +#define SCU_PCI_VENDOR_ID(x) (x) + +/* AST_SCU_PCI_CONF2 0x34 - PCI configuration setting register#2 */ +#define SCU_PCI_SUB_SYS_ID(x) (x << 16) +#define SCU_PCI_SUB_VENDOR_ID(x) (x) + +/* AST_SCU_PCI_CONF3 0x38 - PCI configuration setting register#3 */ +#define SCU_PCI_CLASS_CODE(x) (x << 8) +#define SCU_PCI_REVISION_ID(x) (x) + +/* AST_SCU_SYS_CTRL 0x3C - System reset contrl/status register*/ +#ifdef AST_SOC_G5 +#define SCU_SYS_WDT3_RESET_FLAG (0x1 << 4) +#define SCU_SYS_WDT2_RESET_FLAG (0x1 << 3) +#define SCU_SYS_WDT_RESET_FLAG (0x1 << 2) +#define SCU_SYS_EXT_RESET_FLAG (0x1 << 1) +#else +#define SCU_SYS_EXT_SOC_RESET_EN (0x1 << 3) +#define SCU_SYS_EXT_RESET_FLAG (0x1 << 2) +#define SCU_SYS_WDT_RESET_FLAG (0x1 << 1) +#endif +#define SCU_SYS_PWR_RESET_FLAG (0x1 << 0) + +/* AST_SCU_SOC_SCRATCH0 0x40 - SOC scratch 0~31 register */ + +/* AST_SCU_SOC_SCRATCH1 0x44 - SOC scratch 32~63 register */ + +/* AST_SCU_VGA0 0x40 - VGA fuction handshake register */ +#define SCU_VGA_SLT_HANDSHAKE(x) (x << 24) +#define SCU_VGA_SLT_HANDSHAKE_MASK (0xff << 24) +#define SCU_VGA_CTM_DEF(x) (x << 16) +#define SCU_VGA_CTM_DEF_MASK (0xff << 16) +#define SCU_MAC0_PHY_MODE(x) (x << 14) +#define SCU_MAC0_GET_PHY_MODE(x) ((x >> 14) & 0x3) +#define SCU_MAC0_PHY_MODE_MASK(x) (0x3 << 14) +#define SCU_MAC1_PHY_MODE(x) (x << 12) +#define SCU_MAC1_PHY_MODE_MASK (0x3 << 12) +#define SCU_MAC1_GET_PHY_MODE(x) ((x >> 12) & 0x3) + +#define SCU_VGA_ASPEED_DEF(x) (x << 8) +#define SCU_VGA_ASPEED_DEF_MASK (0xf << 8) + +#define SCU_VGA_DRAM_INIT_MASK(x) ((x >> 7) & 0x1) + +/* AST_SCU_VGA1 0x44 - VGA fuction handshake register */ + +/* AST_SCU_MAC_CLK 0x48 - MAC interface clock delay setting register */ + +/* AST_SCU_MISC2_CTRL 0x4C - Misc. 2 Control register */ +#ifdef AST_SOC_G5 +#define SCU_PCIE_MAPPING_HIGH (1 << 15) +#define SCU_MALI_DTY_MODE (1 << 8) +#define SCU_MALI_RC_MODE (1 << 7) +#endif +#define SCU_PCI_BM_ENABLE (1 << 6) +#define SCU_DAC_GC_SET(x) ((x & 0x7) << 3) +#define SCU_DAC_FS_SET(x) (x & 0x7) + +/* AST_SCU_VGA_SCRATCH0 0x50 - VGA Scratch register */ +/* AST_SCU_VGA_SCRATCH1 0x54 - VGA Scratch register */ +/* AST_SCU_VGA_SCRATCH2 0x58 - VGA Scratch register */ +/* AST_SCU_VGA_SCRATCH3 0x5c - VGA Scratch register */ +/* AST_SCU_VGA_SCRATCH4 0x60 - VGA Scratch register */ +/* AST_SCU_VGA_SCRATCH5 0x64 - VGA Scratch register */ +/* AST_SCU_VGA_SCRATCH6 0x68 - VGA Scratch register */ +/* AST_SCU_VGA_SCRATCH7 0x6c - VGA Scratch register */ + +/* AST_SCU_HW_STRAP1 0x70 - hardware strapping register */ +#ifdef AST_SOC_G5 + +#define CLK_25M_IN (0x1 << 23) + +#define SCU_HW_STRAP_2ND_BOOT_WDT (0x1 << 17) +#define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16) +#define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15) +#define SCU_HW_STRAP_LPC_RESET_PIN (0x1 << 14) +#define SCU_HW_STRAP_SPI_MODE(x) (x << 12) +#define SCU_HW_STRAP_SPI_MODE_MASK (0x3 << 12) +#define SCU_HW_STRAP_SPI_MASTER (0x1 << 12) +#define SCU_HW_STRAP_SPI_M_S_EN (0x2 << 12) +#define SCU_HW_STRAP_SPI_PASS_THROUGH (0x3 << 12) +#define SCU_HW_STRAP_GET_AXI_AHB_RATIO(x) ((x >> 9) & 0x7) +#define SCU_HW_STRAP_GET_CPU_AXI_RATIO(x) ((x >> 8) & 0x1) +#define SCU_HW_STRAP_MAC1_RGMII (0x1 << 7) +#define SCU_HW_STRAP_MAC0_RGMII (0x1 << 6) +#define SCU_HW_STRAP_VGA_BIOS_ROM (0x1 << 5) +#define SCU_HW_STRAP_SPI_WIDTH (0x1 << 4) + +#define SCU_HW_STRAP_VGA_SIZE_GET(x) ((x >> 2)& 0x3) +#define SCU_HW_STRAP_VGA_MASK (0x3 << 3) +#define SCU_HW_STRAP_VGA_SIZE_SET(x) (x << 2) +#define VGA_8M_DRAM 0 +#define VGA_16M_DRAM 1 +#define VGA_32M_DRAM 2 +#define VGA_64M_DRAM 3 + +#define SCU_HW_STRAP_DIS_BOOT (1) +#else /* !AST_SOC_G5 */ +#define SCU_HW_STRAP_SW_DEFINE(x) (x << 29) +#define SCU_HW_STRAP_SW_DEFINE_MASK (0x7 << 29) + +#define SCU_HW_STRAP_DRAM_SIZE(x) (x << 27) +#define SCU_HW_STRAP_DRAM_SIZE_MASK (0x3 << 27) +#define DRAM_SIZE_64MB 0 +#define DRAM_SIZE_128MB 1 +#define DRAM_SIZE_256MB 2 +#define DRAM_SIZE_512MB 3 + +#define SCU_HW_STRAP_DRAM_CONFIG(x) (x << 24) +#define SCU_HW_STRAP_DRAM_CONFIG_MASK (0x7 << 24) + +#define SCU_HW_STRAP_GPIOE_PT_EN (0x1 << 22) +#define SCU_HW_STRAP_GPIOD_PT_EN (0x1 << 21) +#define SCU_HW_STRAP_LPC_DEC_SUPER_IO (0x1 << 20) +#define SCU_HW_STRAP_ACPI_DIS (0x1 << 19) + +/* bit 23, 18 [1,0] */ +#define SCU_HW_STRAP_SET_CLK_SOURCE(x) ((((x & 0x3) >> 1) << 23) | \ + ((x & 0x1) << 18)) +#define SCU_HW_STRAP_GET_CLK_SOURCE(x) ((((x >> 23) & 0x1) << 1) | \ + ((x >> 18) & 0x1)) +#define SCU_HW_STRAP_CLK_SOURCE_MASK ((0x1 << 23) | (0x1 << 18)) +#define CLK_25M_IN (0x1 << 23) +#define CLK_24M_IN 0 +#define CLK_48M_IN 1 +#define CLK_25M_IN_24M_USB_CKI 2 +#define CLK_25M_IN_48M_USB_CKI 3 + +#define SCU_HW_STRAP_2ND_BOOT_WDT (0x1 << 17) +#define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16) +#define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15) +#define SCU_HW_STRAP_LPC_RESET_PIN (0x1 << 14) + +#define SCU_HW_STRAP_SPI_MODE(x) (x << 12) +#define SCU_HW_STRAP_SPI_MODE_MASK (0x3 << 12) +#define SCU_HW_STRAP_SPI_DIS 0 +#define SCU_HW_STRAP_SPI_MASTER 1 +#define SCU_HW_STRAP_SPI_M_S_EN 2 +#define SCU_HW_STRAP_SPI_PASS_THROUGH 3 + +#define SCU_HW_STRAP_SET_CPU_AHB_RATIO(x) (x << 10) +#define SCU_HW_STRAP_GET_CPU_AHB_RATIO(x) ((x >> 10) & 3) +#define SCU_HW_STRAP_CPU_AHB_RATIO_MASK (0x3 << 10) +#define CPU_AHB_RATIO_1_1 0 +#define CPU_AHB_RATIO_2_1 1 +#define CPU_AHB_RATIO_4_1 2 +#define CPU_AHB_RATIO_3_1 3 + +#define SCU_HW_STRAP_GET_H_PLL_CLK(x) ((x >> 8) & 0x3) +#define SCU_HW_STRAP_H_PLL_CLK_MASK (0x3 << 8) +#define CPU_384MHZ 0 +#define CPU_360MHZ 1 +#define CPU_336MHZ 2 +#define CPU_408MHZ 3 + +#define SCU_HW_STRAP_MAC1_RGMII (0x1 << 7) +#define SCU_HW_STRAP_MAC0_RGMII (0x1 << 6) +#define SCU_HW_STRAP_VGA_BIOS_ROM (0x1 << 5) +#define SCU_HW_STRAP_SPI_WIDTH (0x1 << 4) + +#define SCU_HW_STRAP_VGA_SIZE_GET(x) ((x >> 2) & 0x3) +#define SCU_HW_STRAP_VGA_MASK (0x3 << 2) +#define SCU_HW_STRAP_VGA_SIZE_SET(x) (x << 2) +#define VGA_8M_DRAM 0 +#define VGA_16M_DRAM 1 +#define VGA_32M_DRAM 2 +#define VGA_64M_DRAM 3 + +#define SCU_HW_STRAP_BOOT_MODE(x) (x) +#define NOR_BOOT 0 +#define NAND_BOOT 1 +#define SPI_BOOT 2 +#define DIS_BOOT 3 + +#endif /* AST_SOC_G5 */ + +/* AST_SCU_RAMDOM_GEN 0x74 - random number generator register */ +#define RNG_TYPE_MASK (0x7 << 1) +#define RNG_SET_TYPE(x) ((x) << 1) +#define RNG_GET_TYPE(x) (((x) >> 1) & 0x7) +#define RNG_ENABLE 0x1 +/* AST_SCU_RAMDOM_DATA 0x78 - random number generator data output */ + +/* AST_SCU_MULTI_FUNC_2 0x78 */ + +#define MULTI_FUNC_VIDEO_RGB18 (0x1 << 2) +#define MULTI_FUNC_VIDEO_SINGLE_EDGE (0x1 << 0) + + +/* AST_SCU_REVISION_ID 0x7C - Silicon revision ID register */ +#define AST_SOC_GEN 24 +#define AST1100_A0 0x00000200 +#define AST1100_A1 0x00000201 +#define AST1100_A2 0x00000202 +#define AST1100_A3 0x00000202 + +#define AST2050_A0 0x00000200 +#define AST2050_A1 0x00000201 +#define AST2050_A2 0x00000202 +#define AST2050_A3 0x00000202 + +#define AST2100_A0 0x00000300 +#define AST2100_A1 0x00000301 +#define AST2100_A2 0x00000302 +#define AST2100_A3 0x00000302 + +#define AST2200_A0 0x00000102 +#define AST2200_A1 0x00000102 + +#define AST2300_A0 0x01000003 +#define AST2300_A1 0x01010303 +#define AST1300_A1 0x01010003 +#define AST1050_A1 0x01010203 + +#define AST2400_A0 0x02000303 + +#define GET_CHIP_REVISION(x) ((x & 0xff000000) >> 24) +#define GET_HW_REVISION_ID(x) ((x & 0xff0000) >> 16) + +#define AST_DRAM_BASE_4 0x40000000 +#define AST_DRAM_BASE_8 0x80000000 + +/* AST_SCU_FUN_PIN_CTRL1 0x80 - Multi-function Pin Control#1 */ +#define SCU_FUN_PIN_UART4_RXD (0x1 << 31) +#define SCU_FUN_PIN_UART4_TXD (0x1 << 30) +#define SCU_FUN_PIN_UART4_NRTS (0x1 << 29) +#define SCU_FUN_PIN_UART4_NDTR (0x1 << 28) +#define SCU_FUN_PIN_UART4_NRI (0x1 << 27) +#define SCU_FUN_PIN_UART4_NDSR (0x1 << 26) +#define SCU_FUN_PIN_UART4_NDCD (0x1 << 25) +#define SCU_FUN_PIN_UART4_NCTS (0x1 << 24) +#define SCU_FUN_PIN_UART3_RXD (0x1 << 23) +#define SCU_FUN_PIN_UART3_TXD (0x1 << 22) +#define SCU_FUN_PIN_UART3_NRTS (0x1 << 21) +#define SCU_FUN_PIN_UART3_NDTR (0x1 << 20) +#define SCU_FUN_PIN_UART3_NRI (0x1 << 19) +#define SCU_FUN_PIN_UART3_NDSR (0x1 << 18) +#define SCU_FUN_PIN_UART3_NDCD (0x1 << 17) +#define SCU_FUN_PIN_UART3_NCTS (0x1 << 16) + +#define SCU_FUN_PIN_MAC1_PHY_LINK (0x1 << 1) +#define SCU_FUN_PIN_MAC0_PHY_LINK (0x1) + +/* AST_SCU_FUN_PIN_CTRL2 0x84 - Multi-function Pin Control#2 */ +#define SCU_FUN_PIN_VPIB9 (0x1 << 31) +#define SCU_FUN_PIN_VPIB8 (0x1 << 30) +#define SCU_FUN_PIN_VPIB7 (0x1 << 29) +#define SCU_FUN_PIN_VPIB6 (0x1 << 28) +#define SCU_FUN_PIN_VPIB5 (0x1 << 27) +#define SCU_FUN_PIN_VPIB4 (0x1 << 26) +#define SCU_FUN_PIN_VPIB3 (0x1 << 25) +#define SCU_FUN_PIN_VPIB2 (0x1 << 24) +#define SCU_FUN_PIN_VPIB1 (0x1 << 23) +#define SCU_FUN_PIN_VPIB0 (0x1 << 22) +#define SCU_FUN_PIN_VPICLK (0x1 << 21) +#define SCU_FUN_PIN_VPIVS (0x1 << 20) +#define SCU_FUN_PIN_VPIHS (0x1 << 19) +#define SCU_FUN_PIN_VPIODD (0x1 << 18) +#define SCU_FUN_PIN_VPIDE (0x1 << 17) + +#define SCU_FUN_PIN_DDCDAT (0x1 << 15) +#define SCU_FUN_PIN_DDCCLK (0x1 << 14) +#define SCU_FUN_PIN_VGAVS (0x1 << 13) +#define SCU_FUN_PIN_VGAHS (0x1 << 12) + +#define SCU_FUN_PIN_UART2_RXD (0x1 << 31) +#define SCU_FUN_PIN_UART2_TXD (0x1 << 30) +#define SCU_FUN_PIN_UART2_NRTS (0x1 << 29) +#define SCU_FUN_PIN_UART2_NDTR (0x1 << 28) +#define SCU_FUN_PIN_UART2_NRI (0x1 << 27) +#define SCU_FUN_PIN_UART2_NDSR (0x1 << 26) +#define SCU_FUN_PIN_UART2_NDCD (0x1 << 25) +#define SCU_FUN_PIN_UART2_NCTS (0x1 << 24) +#define SCU_FUN_PIN_UART1_RXD (0x1 << 23) +#define SCU_FUN_PIN_UART1_TXD (0x1 << 22) +#define SCU_FUN_PIN_UART1_NRTS (0x1 << 21) +#define SCU_FUN_PIN_UART1_NDTR (0x1 << 20) +#define SCU_FUN_PIN_UART1_NRI (0x1 << 19) +#define SCU_FUN_PIN_UART1_NDSR (0x1 << 18) +#define SCU_FUN_PIN_UART1_NDCD (0x1 << 17) +#define SCU_FUN_PIN_UART1_NCTS (0x1 << 16) + +#define SCU_FUN_PIN_SGPMI (0x1 << 11) +#define SCU_FUN_PIN_SGPMO (0x1 << 10) +#define SCU_FUN_PIN_SGPMLD (0x1 << 9) +#define SCU_FUN_PIN_SGPMCK (0x1 << 8) + +#if defined(AST_SOC_G5) +#define SCU_FUN_PIN_I2C4_SALT4 (0x1 << 7) +#define SCU_FUN_PIN_I2C3_SALT3 (0x1 << 6) +#define SCU_FUN_PIN_I2C2_SALT2 (0x1 << 5) +#define SCU_FUN_PIN_I2C1_SALT1 (0x1 << 4) +#else +#define SCU_FUN_PIN_NAND_FLWP (0x1 << 7) +#define SCU_FUN_PIN_NAND_FLBUSY (0x1 << 6) +#endif + +/* AST_SCU_FUN_PIN_CTRL3 0x88 - Multi-function Pin Control#3 */ +#define SCU_FUN_PIN_MAC0_MDIO (0x1 << 31) +#define SCU_FUN_PIN_MAC0_MDC (0x1 << 30) +#define SCU_FUN_PIN_ROMA25 (0x1 << 29) +#define SCU_FUN_PIN_ROMA24 (0x1 << 28) +#define SCU_FUN_PIN_ROMCS4 (0x1 << 27) +#define SCU_FUN_PIN_ROMCS3 (0x1 << 26) +#define SCU_FUN_PIN_ROMCS2 (0x1 << 25) +#define SCU_FUN_PIN_ROMCS1 (0x1 << 24) +#define SCU_FUN_PIN_ROMCS(x) (0x1 << (23+x)) + +#define SCU_FUN_PIN_USBP4_DN (0x1 << 23) +#define SCU_FUN_PIN_USBP4_DP (0x1 << 22) +#define SCU_FUN_PIN_USBP3_DN (0x1 << 21) +#define SCU_FUN_PIN_USBP3_DP (0x1 << 20) +/* Video pin */ +#define SCU_FUN_PIN_VPIR9 (0x1 << 19) +#define SCU_FUN_PIN_VPIR8 (0x1 << 18) +#define SCU_FUN_PIN_VPIR7 (0x1 << 17) +#define SCU_FUN_PIN_VPIR6 (0x1 << 16) +#define SCU_FUN_PIN_VPIR5 (0x1 << 15) +#define SCU_FUN_PIN_VPIR4 (0x1 << 14) +#define SCU_FUN_PIN_VPIR3 (0x1 << 13) +#define SCU_FUN_PIN_VPIR2 (0x1 << 12) +#define SCU_FUN_PIN_VPIR1 (0x1 << 11) +#define SCU_FUN_PIN_VPIR0 (0x1 << 10) +#define SCU_FUN_PIN_VPIG9 (0x1 << 9) +#define SCU_FUN_PIN_VPIG8 (0x1 << 8) +#define SCU_FUN_PIN_VPIG7 (0x1 << 7) +#define SCU_FUN_PIN_VPIG6 (0x1 << 6) +#define SCU_FUN_PIN_VPIG5 (0x1 << 5) +#define SCU_FUN_PIN_VPIG4 (0x1 << 4) +#define SCU_FUN_PIN_VPIG3 (0x1 << 3) +#define SCU_FUN_PIN_VPIG2 (0x1 << 2) +#define SCU_FUN_PIN_VPIG1 (0x1 << 1) +#define SCU_FUN_PIN_VPIG0 (0x1 << 0) + +/* pwm pin */ +#define SCU_FUN_PIN_PWM_TACHO (0) +/* AST_SCU_FUN_PIN_CTRL4 0x8C - Multi-function Pin Control#4 */ +#define SCU_FUN_PIN_ROMA23 (0x1 << 7) +#define SCU_FUN_PIN_ROMA22 (0x1 << 6) + +#define SCU_FUN_PIN_ROMWE (0x1 << 5) +#define SCU_FUN_PIN_ROMOE (0x1 << 4) +#define SCU_FUN_PIN_ROMD7 (0x1 << 3) +#define SCU_FUN_PIN_ROMD6 (0x1 << 2) +#define SCU_FUN_PIN_ROMD5 (0x1 << 1) +#define SCU_FUN_PIN_ROMD4 (0x1) + +/* AST_SCU_FUN_PIN_CTRL5 0x90 - Multi-function Pin Control#5 */ +#define SCU_FUN_PIN_SPICS1 (0x1 << 31) +#define SCU_FUN_PIN_LPC_PLUS (0x1 << 30) +#define SCU_FUC_PIN_USB20_HOST (0x1 << 29) +#define SCU_FUC_PIN_USB11_PORT4 (0x1 << 28) +#define SCU_FUC_PIN_I2C14 (0x1 << 27) +#define SCU_FUC_PIN_I2C13 (0x1 << 26) +#define SCU_FUC_PIN_I2C12 (0x1 << 25) +#define SCU_FUC_PIN_I2C11 (0x1 << 24) +#define SCU_FUC_PIN_I2C10 (0x1 << 23) +#define SCU_FUC_PIN_I2C9 (0x1 << 22) +#define SCU_FUC_PIN_I2C8 (0x1 << 21) +#define SCU_FUC_PIN_I2C7 (0x1 << 20) +#define SCU_FUC_PIN_I2C6 (0x1 << 19) +#define SCU_FUC_PIN_I2C5 (0x1 << 18) +#define SCU_FUC_PIN_I2C4 (0x1 << 17) +#define SCU_FUC_PIN_I2C3 (0x1 << 16) +#define SCU_FUC_PIN_MII2_RX_DWN_DIS (0x1 << 15) +#define SCU_FUC_PIN_MII2_TX_DWN_DIS (0x1 << 14) +#define SCU_FUC_PIN_MII1_RX_DWN_DIS (0x1 << 13) +#define SCU_FUC_PIN_MII1_TX_DWN_DIS (0x1 << 12) + +#define SCU_FUC_PIN_MII2_TX_DRIV(x) (x << 10) +#define SCU_FUC_PIN_MII2_TX_DRIV_MASK (0x3 << 10) +#define SCU_FUC_PIN_MII1_TX_DRIV(x) (x << 8) +#define SCU_FUC_PIN_MII1_TX_DRIV_MASK (0x3 << 8) + +#define MII_NORMAL_DRIV 0x0 +#define MII_HIGH_DRIV 0x2 + +#define SCU_FUC_PIN_UART6 (0x1 << 7) +#define SCU_FUC_PIN_ROM_16BIT (0x1 << 6) +#define SCU_FUC_PIN_DIGI_V_OUT(x) (x) +#define SCU_FUC_PIN_DIGI_V_OUT_MASK (0x3) + +#define VIDEO_DISABLE 0x0 +#define VIDEO_12BITS 0x1 +#define VIDEO_24BITS 0x2 +//#define VIDEO_DISABLE 0x3 + +#define SCU_FUC_PIN_USB11_PORT2 (0x1 << 3) +#define SCU_FUC_PIN_SD1_8BIT (0x1 << 3) + +#define SCU_FUC_PIN_MAC1_MDIO (0x1 << 2) +#define SCU_FUC_PIN_SD2 (0x1 << 1) +#define SCU_FUC_PIN_SD1 (0x1 << 0) + + +/* AST_SCU_FUN_PIN_CTRL6 0x94 - Multi-function Pin Control#6*/ +#define SCU_FUN_PIN_USBP1_MODE(x) (x << 13) /* Select USB2.0 Port\#2 function mode */ +#define SCU_FUN_PIN_USBP1_MASK (0x3 << 13) /* Select USB2.0 Port\#2 function mode */ +#define USB_HID_MODE 0 +#define USB_DEV_MODE 1 +#define USB_HOST_MODE 2 +#define SCU_FUN_PIN_SGPIOP2 (0x1 << 12) /* Enable Slave SGPIO port 2 function pins */ +#define SCU_FUN_PIN_UART13 (0x1 << 11) /* Enable UART13 function pins */ +#define SCU_FUN_PIN_UART12 (0x1 << 10) /* Enable UART12 function pins */ +#define SCU_FUN_PIN_UART11 (0x1 << 9) /* Enable UART11 function pins */ +#define SCU_FUN_PIN_UART10 (0x1 << 8) /* Enable UART10 function pins */ +#define SCU_FUN_PIN_UART9 (0x1 << 7) /* Enable UART9 function pins */ +#define SCU_FUN_PIN_UART8 (0x1 << 6) /* Enable UART8 function pins */ +#define SCU_FUN_PIN_UART7 (0x1 << 5) /* Enable UART7 function pins */ +#define SCU_FUN_PIN_I2S2 (0x1 << 4) +#define SCU_FUN_PIN_I2S1 (0x1 << 3) +#define SCU_FUN_PIN_VIDEO_SO (0x1 << 2) +#define SCU_FUN_PIN_DVO_24BIT (0x1) +#define SCU_VIDEO_OUT_MASK (~0x3) + +/* AST_SCU_WDT_RESET 0x9C - Watchdog Reset Selection */ +/* AST_SCU_FUN_PIN_CTRL7 0xA0 - Multi-function Pin Control#7*/ +/* AST_SCU_FUN_PIN_CTRL8 0xA4 - Multi-function Pin Control#8*/ +#define SCU_FUN_PIN_ROMA17 (0x1 << 31) +#define SCU_FUN_PIN_ROMA16 (0x1 << 30) +#define SCU_FUN_PIN_ROMA15 (0x1 << 29) +#define SCU_FUN_PIN_ROMA14 (0x1 << 28) +#define SCU_FUN_PIN_ROMA13 (0x1 << 27) +#define SCU_FUN_PIN_ROMA12 (0x1 << 26) +#define SCU_FUN_PIN_ROMA11 (0x1 << 25) +#define SCU_FUN_PIN_ROMA10 (0x1 << 24) +#define SCU_FUN_PIN_ROMA9 (0x1 << 23) +#define SCU_FUN_PIN_ROMA8 (0x1 << 22) +#define SCU_FUN_PIN_ROMA7 (0x1 << 21) +#define SCU_FUN_PIN_ROMA6 (0x1 << 20) +#define SCU_FUN_PIN_ROMA5 (0x1 << 19) +#define SCU_FUN_PIN_ROMA4 (0x1 << 18) +#define SCU_FUN_PIN_ROMA3 (0x1 << 17) +#define SCU_FUN_PIN_ROMA2 (0x1 << 16) + +/* AST_SCU_FUN_PIN_CTRL9 0xA8 - Multi-function Pin Control#9 */ +#define SCU_FUN_PIN_ROMA21 (0x1 << 3) +#define SCU_FUN_PIN_ROMA20 (0x1 << 2) +#define SCU_FUN_PIN_ROMA19 (0x1 << 1) +#define SCU_FUN_PIN_ROMA18 (0x1) + +/* AST_SCU_PWR_SAVING_EN 0xC0 - Power Saving Wakeup Enable */ +/* AST_SCU_PWR_SAVING_CTRL 0xC4 - Power Saving Wakeup Control */ +/* AST_SCU_HW_STRAP2 0xD0 - Haardware strapping register set 2 */ + + +/* AST_SCU_COUNTER4 0xE0 - SCU Free Run Counter Read Back #4 */ +/* AST_SCU_COUNTER4_EXT 0xE4 - SCU Free Run Counter Extended Read Back #4 */ + +//CPU 2 +/* AST_SCU_CPU2_CTRL 0x100 - CPU2 Control Register*/ +/* AST_SCU_CPU2_BASE0_ADDR 0x104 - CPU2 Base Address for Segment 0x00:0000~0x1F:FFFF */ +/* AST_SCU_CPU2_BASE1_ADDR 0x108 - CPU2 Base Address for Segment 0x20:0000~0x3F:FFFF */ +/* AST_SCU_CPU2_BASE2_ADDR 0x10C - CPU2 Base Address for Segment 0x40:0000~0x5F:FFFF */ +/* AST_SCU_CPU2_BASE3_ADDR 0x110 - CPU2 Base Address for Segment 0x60:0000~0x7F:FFFF */ +/* AST_SCU_CPU2_BASE4_ADDR 0x114 - CPU2 Base Address for Segment 0x80:0000~0xFF:FFFF */ +/* AST_SCU_CPU2_CACHE_CTRL 0x118 - CPU2 Cache Function Control */ + +/* AST_SCU_UART24_REF 0x160 - Generate UART 24Mhz Ref from H-PLL when CLKIN is 25Mhz */ +/* AST_SCU_PCIE_CONFIG_SET 0x180 - PCI-E Configuration Setting Control Register */ +/* AST_SCU_BMC_MMIO_DEC 0x184 - BMC MMIO Decode Setting Register */ +/* AST_SCU_DEC_AREA1 0x188 - 1st relocated controller decode area location */ +/* AST_SCU_DEC_AREA2 0x18C - 2nd relocated controller decode area location */ +/* AST_SCU_MBOX_DEC_AREA 0x190 - Mailbox decode area location*/ +/* AST_SCU_SRAM_DEC_AREA0 0x194 - Shared SRAM area decode location*/ +/* AST_SCU_SRAM_DEC_AREA1 0x198 - Shared SRAM area decode location*/ +/* AST_SCU_BMC_CLASS 0x19C - BMC device class code and revision ID */ +/* AST_SCU_BMC_DEV_ID 0x1A4 - BMC device ID */ + +#endif diff --git a/arch/arm/include/asm/arch-aspeed/regs-sdmc.h b/arch/arm/include/asm/arch-aspeed/regs-sdmc.h new file mode 100644 index 0000000000..2861f3b2c9 --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/regs-sdmc.h @@ -0,0 +1,32 @@ +/* arch/arm/mach-aspeed/include/mach/regs-sdmc.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * History : + * 1. 2012/12/29 Ryan Chen Create + * + ******************************************************************************/ +#ifndef __AST_SDMC_H +#define __AST_SDMC_H + +/* + * Register for SDMC + */ +#define AST_SDMC_PROTECT 0x00 /* protection key register */ +#define AST_SDMC_CONFIG 0x04 /* Configuration register */ + +/* AST_SDMC_PROTECT: 0x00 - protection key register */ +#define SDMC_PROTECT_UNLOCK 0xFC600309 + +/* AST_SDMC_CONFIG : 0x04 - Configuration register */ +#define SDMC_CONFIG_VER_NEW (0x1 << 28) +#define SDMC_CONFIG_MEM_GET(x) (x & 0x3) + +#define SDMC_CONFIG_CACHE_EN (0x1 << 10) +#define SDMC_CONFIG_EEC_EN (0x1 << 7) + +#endif diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index d51be0b1d2..8b0c2438fe 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -1107,6 +1107,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_COLIBRI_T30 4493 #define MACH_TYPE_APALIS_T30 4513 #define MACH_TYPE_OMAPL138_LCDK 2495 +#define MACH_TYPE_ASPEED 8888 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -14188,6 +14189,18 @@ extern unsigned int __machine_arch_type; # define machine_is_apalis_t30() (0) #endif +#ifdef CONFIG_MACH_ASPEED +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASPEED +# endif +# define machine_is_aspeed() (machine_arch_type == MACH_TYPE_ASPEED) +#else +# define machine_is_aspeed() (0) +#endif + /* * These have not yet been registered */ diff --git a/arch/arm/mach-aspeed/Makefile b/arch/arm/mach-aspeed/Makefile new file mode 100644 index 0000000000..7d8930beb9 --- /dev/null +++ b/arch/arm/mach-aspeed/Makefile @@ -0,0 +1,17 @@ +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + + +obj-y += timer.o reset.o cpuinfo.o ast-scu.o ast-ahbc.o ast-sdmc.o +obj-$(CONFIG_AST_SPI_NOR) += flash.o +obj-$(CONFIG_ARCH_AST2500) += platform_g5.o +obj-$(CONFIG_ARCH_AST2400) += platform_g4.o diff --git a/arch/arm/mach-aspeed/ast-ahbc.c b/arch/arm/mach-aspeed/ast-ahbc.c new file mode 100644 index 0000000000..9a41482c0f --- /dev/null +++ b/arch/arm/mach-aspeed/ast-ahbc.c @@ -0,0 +1,87 @@ +/******************************************************************************* + * File Name : arch/arm/mach-aspeed/ast-ahbc.c + * Author : Ryan Chen + * Description : AST AHB Ctrl + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 + * USA + * + * History : + * 1. 2014/03/15 Ryan Chen Create + * + ******************************************************************************/ +#include +#include +#include +#include +#include +#include + +static inline u32 ast_ahbc_read(u32 reg) +{ + u32 val = readl(AST_AHBC_BASE + reg); + + debug("reg = 0x%08x, val = 0x%08x\n", reg, val); + return val; +} + +static inline void ast_ahbc_write(u32 val, u32 reg) +{ + debug("reg = 0x%08x, val = 0x%08x\n", reg, val); + +#ifdef CONFIG_AST_AHBC_LOCK + //unlock + writel(AHBC_PROTECT_UNLOCK, AST_AHBC_BASE); + writel(val, AST_AHBC_BASE + reg); + //lock + writel(0xaa,AST_AHBC_BASE); +#else + writel(AHBC_PROTECT_UNLOCK, AST_AHBC_BASE); + writel(val, AST_AHBC_BASE + reg); +#endif + +} + +void ast_ahbc_boot_remap(void) +{ +#if ! defined(AST_SOC_G5) + ast_ahbc_write(ast_ahbc_read(AST_AHBC_ADDR_REMAP) | + AHBC_BOOT_REMAP, AST_AHBC_ADDR_REMAP); +#endif +} + +#ifdef AST_SOC_G5 +void ast_ahbc_peie_mapping(u8 enable) +{ + if (enable) + ast_ahbc_write(ast_ahbc_read(AST_AHBC_ADDR_REMAP) | + AHBC_PCIE_MAP, AST_AHBC_ADDR_REMAP); + else + ast_ahbc_write(ast_ahbc_read(AST_AHBC_ADDR_REMAP) & + ~AHBC_PCIE_MAP, AST_AHBC_ADDR_REMAP); +} + +void ast_ahbc_lpc_plus_mapping(u8 enable) +{ + if(enable) + ast_ahbc_write(ast_ahbc_read(AST_AHBC_ADDR_REMAP) | + AHBC_LPC_PLUS_MAP, AST_AHBC_ADDR_REMAP); + else + ast_ahbc_write(ast_ahbc_read(AST_AHBC_ADDR_REMAP) & + ~AHBC_LPC_PLUS_MAP, AST_AHBC_ADDR_REMAP); +} +#endif diff --git a/arch/arm/mach-aspeed/ast-scu.c b/arch/arm/mach-aspeed/ast-scu.c new file mode 100644 index 0000000000..0cc0d67b5d --- /dev/null +++ b/arch/arm/mach-aspeed/ast-scu.c @@ -0,0 +1,498 @@ +/******************************************************************************* + * File Name : arch/arm/cpu/ast-common/ast-scu.c + * Author : Ryan Chen + * Description : AST SCU + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. This program is free + * software; you can redistribute it and/or modify it under the terms + * of the GNU General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) any + * later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 + * USA + * + * CLK24M + * | + * |--> H-PLL -->HCLK + * | + * |--> M-PLL -xx->MCLK + * | + * |--> V-PLL1 -xx->DCLK + * | + * |--> V-PLL2 -xx->D2CLK + * | + * |--> USB2PHY -->UTMICLK + * + * History : + * 1. 2012/08/15 Ryan Chen Create + * + ******************************************************************************/ +#include +#include +#include +#include +#include +#include +#include + +/* #define ASPEED_SCU_LOCK */ + +static inline u32 ast_scu_read(u32 reg) +{ + u32 val = readl(AST_SCU_BASE + reg); + + debug("ast_scu_read : reg = 0x%08x, val = 0x%08x\n", reg, val); + return val; +} + +static inline void ast_scu_write(u32 val, u32 reg) +{ + debug("ast_scu_write : reg = 0x%08x, val = 0x%08x\n", reg, val); + + writel(SCU_PROTECT_UNLOCK, AST_SCU_BASE); + writel(val, AST_SCU_BASE + reg); +#ifdef CONFIG_AST_SCU_LOCK + writel(0xaa, AST_SCU_BASE); +#endif +} + +/* SoC mapping Table */ +struct soc_id { + const char *name; + u32 rev_id; +}; + +#define SOC_ID(str, rev) { .name = str, .rev_id = rev, } + +static struct soc_id soc_map_table[] = { + SOC_ID("AST1100/AST2050-A0", 0x00000200), + SOC_ID("AST1100/AST2050-A1", 0x00000201), + SOC_ID("AST1100/AST2050-A2,3/AST2150-A0,1", 0x00000202), + SOC_ID("AST1510/AST2100-A0", 0x00000300), + SOC_ID("AST1510/AST2100-A1", 0x00000301), + SOC_ID("AST1510/AST2100-A2,3", 0x00000302), + SOC_ID("AST2200-A0,1", 0x00000102), + SOC_ID("AST2300-A0", 0x01000003), + SOC_ID("AST2300-A1", 0x01010303), + SOC_ID("AST1300-A1", 0x01010003), + SOC_ID("AST1050-A1", 0x01010203), + SOC_ID("AST2400-A0", 0x02000303), + SOC_ID("AST2400-A1", 0x02010303), + SOC_ID("AST1010-A0", 0x03000003), + SOC_ID("AST1010-A1", 0x03010003), + SOC_ID("AST1520-A0", 0x03000203), + SOC_ID("AST3200-A0", 0x03000303), + SOC_ID("AST2500-A0", 0x04000303), + SOC_ID("AST2510-A0", 0x04000103), + SOC_ID("AST2520-A0", 0x04000203), + SOC_ID("AST2530-A0", 0x04000403), + SOC_ID("AST1520-A1", 0x03010203), + SOC_ID("AST3200-A1", 0x03010303), + SOC_ID("AST2500-A1", 0x04010303), + SOC_ID("AST2510-A1", 0x04010103), + SOC_ID("AST2520-A1", 0x04010203), + SOC_ID("AST2530-A1", 0x04010403), +}; + +void ast_scu_init_eth(u8 num) +{ +/* Set MAC delay Timing */ +#ifndef AST_SOC_G5 + /* AST2300 max clk to 125Mhz, AST2400 max clk to 198Mhz */ + + /* RGMII --> H-PLL/6 */ + if (ast_scu_read(AST_SCU_HW_STRAP1) & + (SCU_HW_STRAP_MAC1_RGMII | SCU_HW_STRAP_MAC0_RGMII)) + ast_scu_write((ast_scu_read(AST_SCU_CLK_SEL) & + ~SCU_CLK_MAC_MASK) | SCU_CLK_MAC_DIV(2), + AST_SCU_CLK_SEL); + else /* RMII --> H-PLL/10 */ + ast_scu_write((ast_scu_read(AST_SCU_CLK_SEL) & + ~SCU_CLK_MAC_MASK) | SCU_CLK_MAC_DIV(4), + AST_SCU_CLK_SEL); + + ast_scu_write(0x2255, AST_SCU_MAC_CLK); +#endif + + switch (num) { + case 0: + ast_scu_write(ast_scu_read(AST_SCU_RESET) | SCU_RESET_MAC0, + AST_SCU_RESET); + udelay(100); + ast_scu_write(ast_scu_read(AST_SCU_CLK_STOP) & + ~SCU_MAC0CLK_STOP_EN, AST_SCU_CLK_STOP); + udelay(1000); + ast_scu_write(ast_scu_read(AST_SCU_RESET) & ~SCU_RESET_MAC0, + AST_SCU_RESET); + + break; +#if defined(AST_MAC1_BASE) + case 1: + ast_scu_write(ast_scu_read(AST_SCU_RESET) | SCU_RESET_MAC1, + AST_SCU_RESET); + udelay(100); + ast_scu_write(ast_scu_read(AST_SCU_CLK_STOP) & + ~SCU_MAC1CLK_STOP_EN, AST_SCU_CLK_STOP); + udelay(1000); + ast_scu_write(ast_scu_read(AST_SCU_RESET) & ~SCU_RESET_MAC1, + AST_SCU_RESET); + break; +#endif + } +} + +/* 0: disable spi + * 1: enable spi master + * 2: enable spi master and spi slave to ahb + * 3: enable spi pass-through + */ +void ast_scu_spi_master(u8 mode) +{ +#ifdef AST_SOC_G5 + switch (mode) { + case 0: + ast_scu_write(SCU_HW_STRAP_SPI_MODE_MASK, AST_SCU_REVISION_ID); + break; + case 1: + ast_scu_write(SCU_HW_STRAP_SPI_MODE_MASK, AST_SCU_REVISION_ID); + ast_scu_write(SCU_HW_STRAP_SPI_MASTER, AST_SCU_HW_STRAP1); + break; + case 2: + ast_scu_write(SCU_HW_STRAP_SPI_MODE_MASK, AST_SCU_REVISION_ID); + ast_scu_write(SCU_HW_STRAP_SPI_M_S_EN, AST_SCU_HW_STRAP1); + break; + case 3: + ast_scu_write(SCU_HW_STRAP_SPI_MODE_MASK, AST_SCU_REVISION_ID); + ast_scu_write(SCU_HW_STRAP_SPI_PASS_THROUGH, AST_SCU_HW_STRAP1); + break; + } +#else + switch (mode) { + case 0: + ast_scu_write(ast_scu_read(AST_SCU_HW_STRAP1) & + ~SCU_HW_STRAP_SPI_MODE_MASK, AST_SCU_HW_STRAP1); + break; + case 1: + ast_scu_write((ast_scu_read(AST_SCU_HW_STRAP1) & + ~SCU_HW_STRAP_SPI_MODE_MASK) | + SCU_HW_STRAP_SPI_MASTER, AST_SCU_HW_STRAP1); + break; + case 2: + ast_scu_write((ast_scu_read(AST_SCU_HW_STRAP1) & + ~SCU_HW_STRAP_SPI_MODE_MASK) | + SCU_HW_STRAP_SPI_MASTER, AST_SCU_HW_STRAP1); + break; + case 3: + ast_scu_write((ast_scu_read(AST_SCU_HW_STRAP1) & + ~SCU_HW_STRAP_SPI_MODE_MASK) | + SCU_HW_STRAP_SPI_PASS_THROUGH, AST_SCU_HW_STRAP1); + break; + } +#endif +} + +u32 ast_get_clk_source(void) +{ + if (ast_scu_read(AST_SCU_HW_STRAP1) & CLK_25M_IN) + return AST_PLL_25MHZ; + else + return AST_PLL_24MHZ; +} + +#if defined(AST_SOC_G5) + +u32 ast_get_h_pll_clk(void) +{ + u32 clk = 0; + u32 h_pll_set = ast_scu_read(AST_SCU_H_PLL); + + if (h_pll_set & SCU_H_PLL_OFF) + return 0; + + /* Programming */ + clk = ast_get_clk_source(); + if (h_pll_set & SCU_H_PLL_BYPASS_EN) { + return clk; + } else { + /* P = SCU24[18:13] + * M = SCU24[12:5] + * N = SCU24[4:0] + * hpll = 24MHz * [(M+1) /(N+1)] / (P+1) + */ + clk = ((clk * (SCU_H_PLL_GET_MNUM(h_pll_set) + 1)) / + (SCU_H_PLL_GET_NNUM(h_pll_set) + 1)) / + (SCU_H_PLL_GET_PNUM(h_pll_set) + 1); + } + debug("h_pll = %d\n", clk); + return clk; +} + +u32 ast_get_ahbclk(void) +{ + unsigned int axi_div, ahb_div, hpll; + + hpll = ast_get_h_pll_clk(); + /* AST2500 A1 fix */ + axi_div = 2; + ahb_div = (SCU_HW_STRAP_GET_AXI_AHB_RATIO( + ast_scu_read(AST_SCU_HW_STRAP1)) + 1); + + debug("HPLL=%d, AXI_Div=%d, AHB_DIV = %d, AHB CLK=%d\n", hpll, axi_div, + ahb_div, (hpll / axi_div) / ahb_div); + return ((hpll / axi_div) / ahb_div); +} + +#else /* ! AST_SOC_G5 */ + +u32 ast_get_h_pll_clk(void) +{ + u32 speed, clk = 0; + u32 h_pll_set = ast_scu_read(AST_SCU_H_PLL); + + if (h_pll_set & SCU_H_PLL_OFF) + return 0; + + if (h_pll_set & SCU_H_PLL_PARAMETER) { + /* Programming */ + clk = ast_get_clk_source(); + if (h_pll_set & SCU_H_PLL_BYPASS_EN) { + return clk; + } else { + /* OD == SCU24[4] + * OD = SCU_H_PLL_GET_DIV(h_pll_set); + * Numerator == SCU24[10:5] + * num = SCU_H_PLL_GET_NUM(h_pll_set); + * Denumerator == SCU24[3:0] + * denum = SCU_H_PLL_GET_DENUM(h_pll_set); + * hpll = 24MHz * (2-OD) * ((Numerator+2)/(Denumerator+1)) + */ + clk = ((clk * (2 - SCU_H_PLL_GET_DIV(h_pll_set)) * + (SCU_H_PLL_GET_NUM(h_pll_set) + 2)) / + (SCU_H_PLL_GET_DENUM(h_pll_set) + 1)); + } + } else { + /* HW Trap */ + speed = SCU_HW_STRAP_GET_H_PLL_CLK( + ast_scu_read(AST_SCU_HW_STRAP1)); + switch (speed) { + case 0: + clk = 384000000; + break; + case 1: + clk = 360000000; + break; + case 2: + clk = 336000000; + break; + case 3: + clk = 408000000; + break; + default: + BUG(); + break; + } + } + debug("h_pll = %d\n", clk); + return clk; +} + +u32 ast_get_ahbclk(void) +{ + unsigned int div, hpll; + + hpll = ast_get_h_pll_clk(); + div = SCU_HW_STRAP_GET_CPU_AHB_RATIO(ast_scu_read(AST_SCU_HW_STRAP1)); + div += 1; + + debug("HPLL=%d, Div=%d, AHB CLK=%d\n", hpll, div, hpll / div); + return (hpll / div); +} + +#endif /* AST_SOC_G5 */ + +void ast_scu_show_system_info(void) +{ + +#ifdef AST_SOC_G5 + unsigned int axi_div, ahb_div, h_pll; + + h_pll = ast_get_h_pll_clk(); + + /* AST2500 A1 fix */ + axi_div = 2; + ahb_div = (SCU_HW_STRAP_GET_AXI_AHB_RATIO( + ast_scu_read(AST_SCU_HW_STRAP1)) + 1); + + printf("CPU = %d MHz , AXI = %d MHz, AHB = %d MHz (%d:%d:1)\n", + h_pll / 1000000, + h_pll / axi_div / 1000000, + h_pll / axi_div / ahb_div / 1000000, axi_div, ahb_div); + +#else + u32 h_pll, div; + + h_pll = ast_get_h_pll_clk(); + + div = SCU_HW_STRAP_GET_CPU_AHB_RATIO(ast_scu_read(AST_SCU_HW_STRAP1)); + div += 1; + + printf("CPU = %d MHz ,AHB = %d MHz (%d:1)\n", h_pll / 1000000, + h_pll / div / 1000000, div); +#endif + return; +} + +void ast_scu_multi_func_eth(u8 num) +{ + switch (num) { + case 0: + if (ast_scu_read(AST_SCU_HW_STRAP1) & SCU_HW_STRAP_MAC0_RGMII) { + printf("MAC0 : RGMII\n"); + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) | + SCU_FUN_PIN_MAC0_PHY_LINK, + AST_SCU_FUN_PIN_CTRL1); + } else { + printf("MAC0 : RMII/NCSI\n"); + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) & + ~SCU_FUN_PIN_MAC0_PHY_LINK, + AST_SCU_FUN_PIN_CTRL1); + } + +#ifdef AST_SOC_G5 + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) | + SCU_FUN_PIN_MAC0_PHY_LINK, AST_SCU_FUN_PIN_CTRL1); + +#endif + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL3) | + SCU_FUN_PIN_MAC0_MDIO | SCU_FUN_PIN_MAC0_MDC, + AST_SCU_FUN_PIN_CTRL3); + + break; + case 1: + if (ast_scu_read(AST_SCU_HW_STRAP1) & SCU_HW_STRAP_MAC1_RGMII) { + printf("MAC1 : RGMII\n"); + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) | + SCU_FUN_PIN_MAC1_PHY_LINK, + AST_SCU_FUN_PIN_CTRL1); + } else { + printf("MAC1 : RMII/NCSI\n"); + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) & + ~SCU_FUN_PIN_MAC1_PHY_LINK, + AST_SCU_FUN_PIN_CTRL1); + } + + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) | + SCU_FUN_PIN_MAC1_PHY_LINK, + AST_SCU_FUN_PIN_CTRL1); + + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL5) | + SCU_FUC_PIN_MAC1_MDIO, + AST_SCU_FUN_PIN_CTRL5); + + break; + } +} + +void ast_scu_multi_func_romcs(u8 num) +{ + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL3) | + SCU_FUN_PIN_ROMCS(num), AST_SCU_FUN_PIN_CTRL3); +} + +u32 ast_scu_revision_id(void) +{ + int i; + u32 rev_id = ast_scu_read(AST_SCU_REVISION_ID); + + for (i = 0; i < ARRAY_SIZE(soc_map_table); i++) { + if (rev_id == soc_map_table[i].rev_id) + break; + } + + if (i == ARRAY_SIZE(soc_map_table)) + printf("UnKnown SOC : %x\n", rev_id); + else + printf("SOC : %4s\n", soc_map_table[i].name); + + return rev_id; +} + +void ast_scu_security_info(void) +{ + switch ((ast_scu_read(AST_SCU_HW_STRAP2) >> 18) & 0x3) { + case 1: + printf("SEC : DSS Mode\n"); + break; + case 2: + printf("SEC : UnKnown\n"); + break; + case 3: + printf("SEC : SPI2 Mode\n"); + break; + } +} + +void ast_scu_sys_rest_info(void) +{ + u32 rest = ast_scu_read(AST_SCU_SYS_CTRL); + + if (rest & SCU_SYS_EXT_RESET_FLAG) { + printf("RST : External\n"); + ast_scu_write(SCU_SYS_EXT_RESET_FLAG, AST_SCU_SYS_CTRL); + } else if (rest & SCU_SYS_WDT_RESET_FLAG) { + printf("RST : Watchdog\n"); + ast_scu_write(SCU_SYS_WDT_RESET_FLAG, AST_SCU_SYS_CTRL); + } else if (rest & SCU_SYS_PWR_RESET_FLAG) { + printf("RST : Power On\n"); + ast_scu_write(SCU_SYS_PWR_RESET_FLAG, AST_SCU_SYS_CTRL); + } else { + printf("RST : CLK en\n"); + } +} + +u32 ast_scu_get_vga_memsize(void) +{ + u32 size = 0; + + switch (SCU_HW_STRAP_VGA_SIZE_GET(ast_scu_read(AST_SCU_HW_STRAP1))) { + case VGA_8M_DRAM: + size = 8 * 1024 * 1024; + break; + case VGA_16M_DRAM: + size = 16 * 1024 * 1024; + break; + case VGA_32M_DRAM: + size = 32 * 1024 * 1024; + break; + case VGA_64M_DRAM: + size = 64 * 1024 * 1024; + break; + default: + printf("error vga size\n"); + break; + } + return size; +} + +void ast_scu_get_who_init_dram(void) +{ + switch (SCU_VGA_DRAM_INIT_MASK(ast_scu_read(AST_SCU_VGA0))) { + case 0: + printf("DRAM : init by VBIOS\n"); + break; + case 1: + printf("DRAM : init by SOC\n"); + break; + default: + printf("error vga size\n"); + break; + } +} diff --git a/arch/arm/mach-aspeed/ast-sdmc.c b/arch/arm/mach-aspeed/ast-sdmc.c new file mode 100644 index 0000000000..10f3ddb829 --- /dev/null +++ b/arch/arm/mach-aspeed/ast-sdmc.c @@ -0,0 +1,99 @@ +/******************************************************************************* + * File Name : arch/arm/mach-aspeed/ast-sdmc.c + * Author : Ryan Chen + * Description : AST SDRAM Memory Ctrl + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 + * USA + * + * History : + * 1. 2013/03/15 Ryan Chen Create + * + ******************************************************************************/ +#include +#include +#include +#include + +#include +#include + +//#define AST_SDMC_LOCK + +static inline u32 ast_sdmc_read(u32 reg) +{ + u32 val = readl(AST_SDMC_BASE + reg); + + debug("ast_sdmc_read : reg = 0x%08x, val = 0x%08x\n", reg, val); + return val; +} + +static inline void ast_sdmc_write(u32 val, u32 reg) +{ + debug("ast_sdmc_write : reg = 0x%08x, val = 0x%08x\n", reg, val); +#ifdef CONFIG_AST_SDMC_LOCK + //unlock + writel(SDMC_PROTECT_UNLOCK, AST_SDMC_BASE); + writel(val, AST_SDMC_BASE + reg); + //lock + writel(0xaa, AST_SDMC_BASE); +#else + writel(SDMC_PROTECT_UNLOCK, AST_SDMC_BASE); + + writel(val, AST_SDMC_BASE + reg); +#endif +} + +u32 ast_sdmc_get_mem_size(void) +{ + u32 size = 0; + u32 conf = ast_sdmc_read(AST_SDMC_CONFIG); + + switch (SDMC_CONFIG_MEM_GET(conf)) { + case 0: + size = 64; + break; + case 1: + size = 128; + break; + case 2: + size = 256; + break; + case 3: + size = 512; + break; + default: + printf("error ddr size \n"); + break; + } + + if (conf & SDMC_CONFIG_VER_NEW) { + size <<= 1; + } + + return size * 1024 * 1024; +} + +u8 ast_sdmc_get_eec(void) +{ + return ast_sdmc_read(AST_SDMC_CONFIG) & SDMC_CONFIG_EEC_EN; +} + +u8 ast_sdmc_get_cache(void) +{ + return ast_sdmc_read(AST_SDMC_CONFIG) & SDMC_CONFIG_CACHE_EN; +} diff --git a/arch/arm/mach-aspeed/cpuinfo.c b/arch/arm/mach-aspeed/cpuinfo.c new file mode 100644 index 0000000000..45f70a8183 --- /dev/null +++ b/arch/arm/mach-aspeed/cpuinfo.c @@ -0,0 +1,46 @@ +/* + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + char buf[32]; + ulong size = 0; + + ast_scu_revision_id(); + + ast_scu_sys_rest_info(); + +#ifdef AST_SOC_G5 + ast_scu_security_info(); +#endif + printf("PLL : %4s MHz\n", strmhz(buf, ast_get_clk_source())); + printf("CPU : %4s MHz\n", strmhz(buf, ast_get_h_pll_clk())); +#ifdef AST_SOC_G5 + printf("MEM : %4s MHz, EEC: %s, Cache: %s \n", + strmhz(buf, ast_get_m_pll_clk() * 2), + ast_sdmc_get_eec() ? "Enable" : "Disable", + ast_sdmc_get_cache() ? "Enable" : "Disable"); +#else + printf("MEM : %4s MHz, EEC:%s \n", + strmhz(buf, ast_get_m_pll_clk()), + ast_sdmc_get_eec() ? "Enable" : "Disable"); +#endif + size = ast_scu_get_vga_memsize(); + + puts("VGA : "); + print_size(size, "\n"); + + ast_scu_get_who_init_dram(); + return 0; +} +#endif diff --git a/arch/arm/mach-aspeed/flash.c b/arch/arm/mach-aspeed/flash.c new file mode 100644 index 0000000000..9c5ead6fd7 --- /dev/null +++ b/arch/arm/mach-aspeed/flash.c @@ -0,0 +1,1403 @@ +/* + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * History + * 01/20/2004 - combined variants of original driver. + * 01/22/2004 - Write performance enhancements for parallel chips (Tolunay) + * 01/23/2004 - Support for x8/x16 chips (Rune Raknerud) + * 01/27/2004 - Little endian support Ed Okerson + * + * Tested Architectures + * Port Width Chip Width # of banks Flash Chip Board + * 32 16 1 28F128J3 seranoa/eagle + * 64 16 1 28F128J3 seranoa/falcon + * + */ + +/* The DEBUG define must be before common to enable debugging */ +/* #define DEBUG */ + +#include +#include +#include +#include + +#include +#include + + +/* + * This file implements a Common Flash Interface (CFI) driver for U-Boot. + * The width of the port and the width of the chips are determined at initialization. + * These widths are used to calculate the address for access CFI data structures. + * It has been tested on an Intel Strataflash implementation and AMD 29F016D. + * + * References + * JEDEC Standard JESD68 - Common Flash Interface (CFI) + * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes + * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets + * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet + * + * TODO + * + * Use Primary Extended Query table (PRI) and Alternate Algorithm Query + * Table (ALT) to determine if protection is available + * + * Add support for other command sets Use the PRI and ALT to determine command set + * Verify erase and program timeouts. + */ + +#define CFI_MFR_MACRONIX 0x00C2 +#define CFI_MFR_MICRON 0x0020 +#define CFI_MFR_WINBOND 0x00DA + +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* FLASH chips info */ + +/* Support Flash ID */ +#define STM25P64 0x172020 +#define STM25P128 0x182020 +#define N25Q256 0x19ba20 +#define N25Q512 0x20ba20 +#define S25FL064A 0x160201 +#define S25FL128P 0x182001 +#define S25FL256S 0x190201 +#define W25X16 0x1530ef +#define W25X64 0x1730ef +#define W25Q64BV 0x1740ef +#define W25Q128BV 0x1840ef +#define W25Q256FV 0x1940ef +#define MX25L1605D 0x1520C2 +#define MX25L12805D 0x1820C2 +#define MX25L25635E 0x1920C2 +#define MX66L51235F 0x1A20C2 +#define SST25VF016B 0x4125bf +#define SST25VF064C 0x4b25bf +#define SST25VF040B 0x8d25bf +#define AT25DF161 0x02461F +#define AT25DF321 0x01471F + +/* SPI Define */ +#define CS0_CTRL 0x10 +#define CS1_CTRL 0x14 +#define CS2_CTRL 0x18 + +/* for DMA */ +#define REG_FLASH_INTERRUPT_STATUS 0x08 +#define REG_FLASH_DMA_CONTROL 0x80 +#define REG_FLASH_DMA_FLASH_BASE 0x84 +#define REG_FLASH_DMA_DRAM_BASE 0x88 +#define REG_FLASH_DMA_LENGTH 0x8c + +#define FLASH_STATUS_DMA_BUSY 0x0000 +#define FLASH_STATUS_DMA_READY 0x0800 +#define FLASH_STATUS_DMA_CLEAR 0x0800 + +#define FLASH_DMA_ENABLE 0x01 + +#define CMD_MASK 0xFFFFFFF8 + +#define NORMALREAD 0x00 +#define FASTREAD 0x01 +#define NORMALWRITE 0x02 +#define USERMODE 0x03 + +#define CE_LOW 0x00 +#define CE_HIGH 0x04 + +/* AST2300 only */ +#define IOMODEx1 0x00000000 +#define IOMODEx2 0x20000000 +#define IOMODEx2_dummy 0x30000000 +#define IOMODEx4 0x40000000 +#define IOMODEx4_dummy 0x50000000 + +#define DUMMY_COMMAND_OUT 0x00008000 + +/* specificspi */ +#define SpecificSPI_N25Q512 0x00000001 + +/*-----------------------------------------------------------------------*/ +static u32 ast_spi_calculate_divisor(u32 max_speed_hz) +{ + // [0] ->15 : HCLK , HCLK/16 + u8 SPI_DIV[16] = {16, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0}; + u32 i, hclk, spi_cdvr=0; + + hclk = ast_get_ahbclk(); + for(i=1;i<17;i++) { + if(max_speed_hz >= (hclk/i)) { + spi_cdvr = SPI_DIV[i-1]; +// printf("hclk = %d , spi_cdvr = %d \n",hclk, spi_cdvr); + break; + } + } + +// printf("hclk is %d, divisor is %d, target :%d , cal speed %d\n", hclk, spi_cdvr, max_speed_hz, hclk/i); + return spi_cdvr; +} + +/* create an address based on the offset and the port width */ +inline uchar *flash_make_addr(flash_info_t * info, flash_sect_t sect, uint offset) +{ +#ifdef CONFIG_2SPIFLASH + if (info->start[0] >= PHYS_FLASH_2) + return ((uchar *) (info->start[sect] + (offset * 1) - (PHYS_FLASH_2 - PHYS_FLASH_2_BASE) )); + else + return ((uchar *) (info->start[sect] + (offset * 1))); +#else + return ((uchar *) (info->start[sect] + (offset * 1))); +#endif +} + +static void reset_flash (flash_info_t * info) +{ + ulong ulCtrlData, CtrlOffset = CS0_CTRL; + + switch(info->CE) { + case 0: + CtrlOffset = CS0_CTRL; + break; + case 1: + ast_scu_multi_func_romcs(1); + CtrlOffset = CS1_CTRL; + break; + case 2: + ast_scu_multi_func_romcs(2); + CtrlOffset = CS2_CTRL; + break; + } + + +#if 1 + ulCtrlData = info->iomode | (info->readcmd << 16) | (info->tCK_Read << 8) | (info->dummybyte << 6) | FASTREAD; +#else + ulCtrlData = (info->readcmd << 16) | (info->tCK_Read << 8) | (info->dummybyte << 6) | FASTREAD; + if (info->dualport) + ulCtrlData |= 0x08; +#endif + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + +} + +static void enable_write (flash_info_t * info) +{ + ulong base; + ulong ulCtrlData, CtrlOffset = CS0_CTRL; + uchar jReg; + + switch(info->CE) { + case 0: + CtrlOffset = CS0_CTRL; + break; + case 1: + ast_scu_multi_func_romcs(1); + CtrlOffset = CS1_CTRL; + break; + case 2: + ast_scu_multi_func_romcs(2); + CtrlOffset = CS2_CTRL; + break; + } + + //base = info->start[0]; + base = (ulong) flash_make_addr(info, 0, 0); + + ulCtrlData = (info->tCK_Write << 8); + ulCtrlData |= CE_LOW | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + *(uchar *) (base) = (uchar) (0x06); + udelay(10); + ulCtrlData &= CMD_MASK; + ulCtrlData |= CE_HIGH | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + + ulCtrlData &= CMD_MASK; + ulCtrlData |= CE_LOW | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + *(uchar *) (base) = (uchar) (0x05); + udelay(10); + do { + jReg = *(volatile uchar *) (base); + } while (!(jReg & 0x02)); + ulCtrlData &= CMD_MASK; + ulCtrlData |= CE_HIGH | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + +} + +static void write_status_register (flash_info_t * info, uchar data) +{ + ulong base; + ulong ulCtrlData, CtrlOffset = CS0_CTRL; + uchar jReg; + + switch(info->CE) { + case 0: + CtrlOffset = CS0_CTRL; + break; + case 1: + ast_scu_multi_func_romcs(1); + CtrlOffset = CS1_CTRL; + break; + case 2: + ast_scu_multi_func_romcs(2); + CtrlOffset = CS2_CTRL; + break; + } + + //base = info->start[0]; + base = (ulong) flash_make_addr(info, 0, 0); + + enable_write (info); + + ulCtrlData = (info->tCK_Write << 8); + ulCtrlData |= CE_LOW | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + *(uchar *) (base) = (uchar) (0x01); + udelay(10); + *(uchar *) (base) = (uchar) (data); + ulCtrlData &= CMD_MASK; + ulCtrlData |= CE_HIGH | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + + ulCtrlData &= CMD_MASK; + ulCtrlData |= CE_LOW | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + *(uchar *) (base) = (uchar) (0x05); + udelay(10); + do { + jReg = *(volatile uchar *) (base); + } while (jReg & 0x01); + ulCtrlData &= CMD_MASK; + ulCtrlData |= CE_HIGH | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + +} + +static void enable4b (flash_info_t * info) +{ + ulong base; + ulong ulCtrlData, CtrlOffset = CS0_CTRL; + + switch(info->CE) { + case 0: + CtrlOffset = CS0_CTRL; + break; + case 1: + ast_scu_multi_func_romcs(1); + CtrlOffset = CS1_CTRL; + break; + case 2: + ast_scu_multi_func_romcs(2); + CtrlOffset = CS2_CTRL; + break; + } + + //base = info->start[0]; + base = (ulong) flash_make_addr(info, 0, 0); + + ulCtrlData = (info->tCK_Write << 8); + ulCtrlData |= CE_LOW | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + *(uchar *) (base) = (uchar) (0xb7); + ulCtrlData &= CMD_MASK; + ulCtrlData |= CE_HIGH | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + +} /* enable4b */ + +static void enable4b_spansion (flash_info_t * info) +{ + ulong base; + ulong ulCtrlData, CtrlOffset = CS0_CTRL; + uchar jReg; + + switch(info->CE) { + case 0: + CtrlOffset = CS0_CTRL; + break; + case 1: + ast_scu_multi_func_romcs(1); + CtrlOffset = CS1_CTRL; + break; + case 2: + ast_scu_multi_func_romcs(2); + CtrlOffset = CS2_CTRL; + break; + } + + //base = info->start[0]; + base = (ulong) flash_make_addr(info, 0, 0); + + /* Enable 4B: BAR0 D[7] = 1 */ + ulCtrlData = (info->tCK_Write << 8); + ulCtrlData |= CE_LOW | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + *(uchar *) (base) = (uchar) (0x17); + udelay(10); + *(uchar *) (base) = (uchar) (0x80); + ulCtrlData &= CMD_MASK; + ulCtrlData |= CE_HIGH | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + + ulCtrlData &= CMD_MASK; + ulCtrlData |= CE_LOW | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + *(uchar *) (base) = (uchar) (0x16); + udelay(10); + do { + jReg = *(volatile uchar *) (base); + } while (!(jReg & 0x80)); + ulCtrlData &= CMD_MASK; + ulCtrlData |= CE_HIGH | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + +} /* enable4b_spansion */ + +static void enable4b_numonyx (flash_info_t * info) +{ + ulong base; + ulong ulCtrlData, CtrlOffset = CS0_CTRL; + + switch(info->CE) { + case 0: + CtrlOffset = CS0_CTRL; + break; + case 1: + ast_scu_multi_func_romcs(1); + CtrlOffset = CS1_CTRL; + break; + case 2: + ast_scu_multi_func_romcs(2); + CtrlOffset = CS2_CTRL; + break; + } + + //base = info->start[0]; + base = (ulong) flash_make_addr(info, 0, 0); + + /* Enable Write */ + enable_write (info); + + /* Enable 4B: CMD:0xB7 */ + ulCtrlData = (info->tCK_Write << 8); + ulCtrlData |= CE_LOW | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + *(uchar *) (base) = (uchar) (0xB7); + udelay(10); + ulCtrlData &= CMD_MASK; + ulCtrlData |= CE_HIGH | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + +} /* enable4b_numonyx */ + +/*----------------------------------------------------------------------- + */ +static void flash_write_buffer (flash_info_t *info, uchar *src, ulong addr, int len) +{ + ulong j, base, offset; + ulong ulCtrlData, CtrlOffset = CS0_CTRL; + uchar jReg; + + switch(info->CE) { + case 0: + CtrlOffset = CS0_CTRL; + break; + case 1: + ast_scu_multi_func_romcs(1); + CtrlOffset = CS1_CTRL; + break; + case 2: + ast_scu_multi_func_romcs(2); + CtrlOffset = CS2_CTRL; + break; + } + + base = info->start[0]; + offset = addr - base; + base = (ulong) flash_make_addr(info, 0, 0); + + enable_write (info); + + ulCtrlData = (info->tCK_Write << 8); + + ulCtrlData &= CMD_MASK; + ulCtrlData |= CE_LOW | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + *(uchar *) (base) = (uchar) (0x02); + udelay(10); + if (info->address32) + { + *(uchar *) (base) = (uchar) ((offset & 0xff000000) >> 24); + udelay(10); + } + *(uchar *) (base) = (uchar) ((offset & 0xff0000) >> 16); + udelay(10); + *(uchar *) (base) = (uchar) ((offset & 0x00ff00) >> 8); + udelay(10); + *(uchar *) (base) = (uchar) ((offset & 0x0000ff)); + udelay(10); + + for (j=0; jreg_base + CtrlOffset) = ulCtrlData; + udelay(200); + + ulCtrlData &= CMD_MASK; + ulCtrlData |= CE_LOW | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + *(uchar *) (base) = (uchar) (0x05); + udelay(10); + do { + jReg = *(volatile uchar *) (base); + } while ((jReg & 0x01)); + ulCtrlData &= CMD_MASK; + ulCtrlData |= CE_HIGH | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + + /* RFSR */ + if (info->specificspi == SpecificSPI_N25Q512) + { + ulCtrlData &= CMD_MASK; + ulCtrlData |= CE_LOW | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + *(uchar *) (base) = (uchar) (0x70); + udelay(10); + do { + jReg = *(volatile uchar *) (base); + } while (!(jReg & 0x80)); + ulCtrlData &= CMD_MASK; + ulCtrlData |= CE_HIGH | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + } +} + +/*----------------------------------------------------------------------- + * + * export functions + * + */ + + + +#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE) +static flash_info_t *flash_get_info(ulong base) +{ + int i; + flash_info_t * info = 0; + + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) { + info = & flash_info[i]; + if (info->size && info->start[0] <= base && + base <= info->start[0] + info->size - 1) + break; + } + + return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info; +} +#endif + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int rcode = 0; + int prot; + flash_sect_t sect; + + ulong base, offset; + ulong ulCtrlData, CtrlOffset = CS0_CTRL; + uchar jReg; + + switch(info->CE) { + case 0: + CtrlOffset = CS0_CTRL; + break; + case 1: + ast_scu_multi_func_romcs(1); + CtrlOffset = CS1_CTRL; + break; + case 2: + ast_scu_multi_func_romcs(2); + CtrlOffset = CS2_CTRL; + break; + } + + if ((s_first < 0) || (s_first > s_last)) { + puts ("- no sectors to erase\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + putc ('\n'); + } + + ulCtrlData = (info->tCK_Erase << 8); + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + /* start erasing */ + enable_write(info); + + base = info->start[0]; + offset = info->start[sect] - base; + base = (ulong) flash_make_addr(info, 0, 0); + + ulCtrlData &= CMD_MASK; + ulCtrlData |= CE_LOW | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + *(uchar *) (base) = (uchar) (0xd8); + udelay(10); + if (info->address32) + { + *(uchar *) (base) = (uchar) ((offset & 0xff000000) >> 24); + udelay(10); + } + *(uchar *) (base) = (uchar) ((offset & 0xff0000) >> 16); + udelay(10); + *(uchar *) (base) = (uchar) ((offset & 0x00ff00) >> 8); + udelay(10); + *(uchar *) (base) = (uchar) ((offset & 0x0000ff)); + udelay(10); + + ulCtrlData &= CMD_MASK; + ulCtrlData |= CE_HIGH | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + + ulCtrlData &= CMD_MASK; + ulCtrlData |= CE_LOW | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + *(uchar *) (base) = (uchar) (0x05); + udelay(10); + do { + jReg = *(volatile uchar *) (base); + } while ((jReg & 0x01)); + ulCtrlData &= CMD_MASK; + ulCtrlData |= CE_HIGH | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + + /* RFSR */ + if (info->specificspi == SpecificSPI_N25Q512) + { + ulCtrlData &= CMD_MASK; + ulCtrlData |= CE_LOW | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + *(uchar *) (base) = (uchar) (0x70); + udelay(10); + do { + jReg = *(volatile uchar *) (base); + } while (!(jReg & 0x80)); + ulCtrlData &= CMD_MASK; + ulCtrlData |= CE_HIGH | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + } + + putc ('.'); + } + } + puts (" done\n"); + + reset_flash(info); + + return rcode; +} + +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + printf("%lx : CS#%ld: ", info->start[0] , info->CE); + switch (info->flash_id & 0xff) { + case CFI_MFR_MACRONIX: printf ("MACRONIX "); break; + case CFI_MFR_MICRON: printf ("MICRON "); break; + case CFI_MFR_WINBOND: printf ("WINBOND "); break; + default: printf ("Unknown Vendor %lx", info->flash_id); break; + } + + if (info->size >= (1 << 20)) { + i = 20; + } else { + i = 10; + } + printf (" Size: %ld %cB in %d Sectors\n", + info->size >> i, + (i == 20) ? 'M' : 'k', + info->sector_count); + + return; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + int count; + unsigned char pat[] = {'|', '-', '/', '\\'}; + int patcnt = 0; + ulong BufferSize = info->buffersize; + /* get lower aligned address */ + if (addr & (BufferSize - 1)) + { + count = cnt >= BufferSize ? (BufferSize - (addr & 0xff)):cnt; + flash_write_buffer (info, src, addr, count); + addr+= count; + src += count; + cnt -= count; + } + + /* prog */ + while (cnt > 0) { + count = cnt >= BufferSize ? BufferSize:cnt; + flash_write_buffer (info, src, addr, count); + addr+= count; + src += count; + cnt -= count; + printf("%c\b", pat[(patcnt++) & 0x03]); + } + + reset_flash(info); + + return (0); +} + +static ulong flash_get_size (ulong base, flash_info_t *info) +{ + int j; + unsigned long sector; + int erase_region_size; + ulong ulCtrlData, CtrlOffset = CS0_CTRL; + ulong ulID; + uchar ch[3]; + ulong reg; + ulong WriteClk, EraseClk, ReadClk; + ulong vbase; + + info->start[0] = base; +// printf("base %x \n",base); + vbase = (ulong) flash_make_addr(info, 0, 0); + + switch(info->CE) { + case 0: + CtrlOffset = CS0_CTRL; + break; + case 1: + ast_scu_multi_func_romcs(1); + CtrlOffset = CS1_CTRL; + break; + case 2: + ast_scu_multi_func_romcs(2); + CtrlOffset = CS2_CTRL; + break; + } + + /* Get Flash ID */ + ulCtrlData = *(ulong *) (info->reg_base + CtrlOffset) & CMD_MASK; + ulCtrlData |= CE_LOW | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + *(uchar *) (vbase) = (uchar) (0x9F); + udelay(10); + ch[0] = *(volatile uchar *)(vbase); + udelay(10); + ch[1] = *(volatile uchar *)(vbase); + udelay(10); + ch[2] = *(volatile uchar *)(vbase); + udelay(10); + ulCtrlData = *(ulong *) (info->reg_base + CtrlOffset) & CMD_MASK; + ulCtrlData |= CE_HIGH | USERMODE; + *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; + udelay(200); + ulID = ((ulong)ch[0]) | ((ulong)ch[1] << 8) | ((ulong)ch[2] << 16) ; + info->flash_id = ulID; + +// printf("SPI Flash ID: %x \n", ulID); + + /* init default */ + info->iomode = IOMODEx1; + info->address32 = 0; + info->quadport = 0; + info->specificspi = 0; + + switch (info->flash_id) { + case STM25P64: + info->sector_count = 128; + info->size = 0x800000; + erase_region_size = 0x10000; + info->readcmd = 0x0b; + info->dualport = 0; + info->dummybyte = 1; + info->buffersize = 256; + WriteClk = 40; + EraseClk = 20; + ReadClk = 40; + break; + + case STM25P128: + info->sector_count = 64; + info->size = 0x1000000; + erase_region_size = 0x40000; + info->readcmd = 0x0b; + info->dualport = 0; + info->dummybyte = 1; + info->buffersize = 256; + WriteClk = 50; + EraseClk = 20; + ReadClk = 50; + break; + + case N25Q256: + info->sector_count = 256; + info->size = 0x1000000; + erase_region_size = 0x10000; + info->readcmd = 0x0b; + info->dualport = 0; + info->dummybyte = 1; + info->buffersize = 256; + WriteClk = 50; + EraseClk = 20; + ReadClk = 50; +#if 1 + info->sector_count = 512; + info->size = 0x2000000; + info->address32 = 1; +#endif + break; + + case N25Q512: + info->sector_count = 256; + info->size = 0x1000000; + erase_region_size = 0x10000; + info->readcmd = 0x0b; + info->dualport = 0; + info->dummybyte = 1; + info->buffersize = 256; + info->specificspi = SpecificSPI_N25Q512; + WriteClk = 50; + EraseClk = 20; + ReadClk = 50; +#if 1 + info->sector_count = 1024; + info->size = 0x4000000; + info->address32 = 1; +#endif + break; + + case W25X16: + info->sector_count = 32; + info->size = 0x200000; + erase_region_size = 0x10000; + info->readcmd = 0x3b; + info->dualport = 1; + info->dummybyte = 1; + info->iomode = IOMODEx2; + info->buffersize = 256; + WriteClk = 50; + EraseClk = 25; + ReadClk = 50; + break; + + case W25X64: + info->sector_count = 128; + info->size = 0x800000; + erase_region_size = 0x10000; + info->readcmd = 0x3b; + info->dualport = 1; + info->dummybyte = 1; + info->iomode = IOMODEx2; + info->buffersize = 256; + WriteClk = 50; + EraseClk = 25; + ReadClk = 50; + break; + + case W25Q64BV: + info->sector_count = 128; + info->size = 0x800000; + erase_region_size = 0x10000; + info->readcmd = 0x3b; + info->dualport = 1; + info->dummybyte = 1; + info->iomode = IOMODEx2; + info->buffersize = 256; + WriteClk = 80; + EraseClk = 40; + ReadClk = 80; + break; + + case W25Q128BV: + info->sector_count = 256; + info->size = 0x1000000; + erase_region_size = 0x10000; + info->readcmd = 0x3b; + info->dualport = 1; + info->dummybyte = 1; + info->iomode = IOMODEx2; + info->buffersize = 256; + WriteClk = 104; + EraseClk = 50; + ReadClk = 104; + break; + + case W25Q256FV: + info->sector_count = 256; + info->size = 0x1000000; + erase_region_size = 0x10000; + info->readcmd = 0x0b; + info->dualport = 0; + info->dummybyte = 1; + info->buffersize = 256; + WriteClk = 50; + EraseClk = 20; + ReadClk = 50; +#if 1 + info->sector_count = 512; + info->size = 0x2000000; + info->address32 = 1; +#endif + break; + + case S25FL064A: + info->sector_count = 128; + info->size = 0x800000; + erase_region_size = 0x10000; + info->readcmd = 0x0b; + info->dualport = 0; + info->dummybyte = 1; + info->buffersize = 256; + WriteClk = 50; + EraseClk = 25; + ReadClk = 50; + break; + + case S25FL128P: + info->sector_count = 256; + info->size = 0x1000000; + erase_region_size = 0x10000; + info->readcmd = 0x0b; + info->dualport = 0; + info->dummybyte = 1; + info->buffersize = 256; + WriteClk = 100; + EraseClk = 40; + ReadClk = 100; + break; + + case S25FL256S: + info->sector_count = 256; + info->size = 0x1000000; + erase_region_size = 0x10000; + info->readcmd = 0x0b; + info->dualport = 0; + info->dummybyte = 1; + info->buffersize = 256; + WriteClk = 50; + EraseClk = 20; + ReadClk = 50; +#if 1 + info->sector_count = 512; + info->size = 0x2000000; + info->address32 = 1; +#endif + break; + + case MX25L25635E: + info->sector_count = 256; + info->size = 0x1000000; + erase_region_size = 0x10000; + info->readcmd = 0x0b; + info->dualport = 0; + info->dummybyte = 1; + info->buffersize = 256; + WriteClk = 50; + EraseClk = 20; + ReadClk = 50; +#if 1 + info->sector_count = 512; + info->size = 0x2000000; + info->address32 = 1; +#if defined(CONFIG_FLASH_SPIx2_Dummy) + info->readcmd = 0xbb; + info->dummybyte = 1; + info->dualport = 1; + info->iomode = IOMODEx2_dummy; +#elif defined(CONFIG_FLASH_SPIx4_Dummy) + info->readcmd = 0xeb; + info->dummybyte = 3; + info->dualport = 0; + info->iomode = IOMODEx4_dummy; + info->quadport = 1; + info->dummydata = 0xaa; +#endif +#endif + break; + + case MX66L51235F: + erase_region_size = 0x10000; + info->readcmd = 0x0b; + info->dualport = 0; + info->dummybyte = 1; + info->buffersize = 512; + WriteClk = 50; + EraseClk = 20; + ReadClk = 50; +#if 1 + info->sector_count = 1024; + info->size = 0x4000000; + info->address32 = 1; +#if defined(CONFIG_FLASH_SPIx2_Dummy) + info->readcmd = 0xbb; + info->dummybyte = 1; + info->dualport = 1; + info->iomode = IOMODEx2_dummy; +#elif defined(CONFIG_FLASH_SPIx4_Dummy) + info->readcmd = 0xeb; + info->dummybyte = 3; + info->dualport = 0; + info->iomode = IOMODEx4_dummy; + info->quadport = 1; + info->dummydata = 0xaa; +#endif +#endif + break; + + case MX25L12805D: + info->sector_count = 256; + info->size = 0x1000000; + erase_region_size = 0x10000; + info->readcmd = 0x0b; + info->dualport = 0; + info->dummybyte = 1; + info->buffersize = 256; + + WriteClk = 50; + EraseClk = 20; + ReadClk = 50; + +#if 1 +#if defined(CONFIG_FLASH_SPIx2_Dummy) + info->readcmd = 0xbb; + info->dummybyte = 1; + info->dualport = 1; + info->iomode = IOMODEx2_dummy; +#elif defined(CONFIG_FLASH_SPIx4_Dummy) + info->readcmd = 0xeb; + info->dummybyte = 3; + info->dualport = 0; + info->iomode = IOMODEx4_dummy; + info->quadport = 1; + info->dummydata = 0xaa; +#endif +#endif + break; + + case MX25L1605D: + info->sector_count = 32; + info->size = 0x200000; + erase_region_size = 0x10000; + info->readcmd = 0x0b; + info->dualport = 0; + info->dummybyte = 1; + info->buffersize = 256; + WriteClk = 50; + EraseClk = 20; + ReadClk = 50; + break; + + case SST25VF016B: + info->sector_count = 32; + info->size = 0x200000; + erase_region_size = 0x10000; + info->readcmd = 0x0b; + info->dualport = 0; + info->dummybyte = 1; + info->buffersize = 1; + WriteClk = 50; + EraseClk = 25; + ReadClk = 50; + break; + + case SST25VF064C: + info->sector_count = 128; + info->size = 0x800000; + erase_region_size = 0x10000; + info->readcmd = 0x0b; + info->dualport = 0; + info->dummybyte = 1; + info->buffersize = 1; + WriteClk = 50; + EraseClk = 25; + ReadClk = 50; + break; + + case SST25VF040B: + info->sector_count = 8; + info->size = 0x80000; + erase_region_size = 0x10000; + info->readcmd = 0x0b; + info->dualport = 0; + info->dummybyte = 1; + info->buffersize = 1; + WriteClk = 50; + EraseClk = 25; + ReadClk = 50; + break; + + case AT25DF161: + info->sector_count = 32; + info->size = 0x200000; + erase_region_size = 0x10000; + info->readcmd = 0x0b; + info->dualport = 0; + info->dummybyte = 1; + info->buffersize = 1; + WriteClk = 50; + EraseClk = 25; + ReadClk = 50; + break; + + case AT25DF321: + info->sector_count = 32; + info->size = 0x400000; + erase_region_size = 0x10000; + info->readcmd = 0x0b; + info->dualport = 0; + info->dummybyte = 1; + info->buffersize = 1; + WriteClk = 50; + EraseClk = 25; + ReadClk = 50; + break; + + default: /* use JEDEC ID */ + printf("Unsupported SPI Flash!! 0x%08lx\n", info->flash_id); + erase_region_size = 0x10000; + info->readcmd = 0x0b; + info->dualport = 0; + info->dummybyte = 1; + info->buffersize = 1; + WriteClk = 50; + EraseClk = 25; + ReadClk = 50; + if ((info->flash_id & 0xFF) == 0x1F) { + /* Atmel */ + switch (info->flash_id & 0x001F00) { + case 0x000400: + info->sector_count = 8; + info->size = 0x80000; + break; + case 0x000500: + info->sector_count = 16; + info->size = 0x100000; + break; + case 0x000600: + info->sector_count = 32; + info->size = 0x200000; + break; + case 0x000700: + info->sector_count = 64; + info->size = 0x400000; + break; + case 0x000800: + info->sector_count = 128; + info->size = 0x800000; + break; + case 0x000900: + info->sector_count = 256; + info->size = 0x1000000; + break; + default: + printf("Can't support this SPI Flash!! \n"); + return 0; + } + } else { + /* JDEC */ + switch (info->flash_id & 0xFF0000) + { + case 0x120000: + info->sector_count = 4; + info->size = 0x40000; + break; + case 0x130000: + info->sector_count = 8; + info->size = 0x80000; + break; + case 0x140000: + info->sector_count =16; + info->size = 0x100000; + break; + case 0x150000: + info->sector_count =32; + info->size = 0x200000; + break; + case 0x160000: + info->sector_count =64; + info->size = 0x400000; + break; + case 0x170000: + info->sector_count =128; + info->size = 0x800000; + break; + case 0x180000: + info->sector_count =256; + info->size = 0x1000000; + break; + case 0x190000: + info->sector_count =256; + info->size = 0x1000000; +#if 1 + info->sector_count = 512; + info->size = 0x2000000; + info->address32 = 1; +#if defined(CONFIG_FLASH_SPIx2_Dummy) + info->readcmd = 0xbb; + info->dummybyte = 1; + info->dualport = 1; + info->iomode = IOMODEx2_dummy; +#elif defined(CONFIG_FLASH_SPIx4_Dummy) + info->readcmd = 0xeb; + info->dummybyte = 3; + info->dualport = 0; + info->iomode = IOMODEx4_dummy; + info->quadport = 1; + info->dummydata = 0xaa; +#endif +#endif + break; + + case 0x200000: + info->sector_count =256; + info->size = 0x1000000; + if ((info->flash_id & 0xFF) == 0x20) /* numonyx */ + info->specificspi = SpecificSPI_N25Q512; +#if 1 + info->sector_count = 1024; + info->size = 0x4000000; + info->address32 = 1; +#if defined(CONFIG_FLASH_SPIx2_Dummy) + info->readcmd = 0xbb; + info->dummybyte = 1; + info->dualport = 1; + info->iomode = IOMODEx2_dummy; +#elif defined(CONFIG_FLASH_SPIx4_Dummy) + info->readcmd = 0xeb; + info->dummybyte = 3; + info->dualport = 0; + info->iomode = IOMODEx4_dummy; + info->quadport = 1; + info->dummydata = 0xaa; +#endif +#endif + break; + + default: + printf("Can't support this SPI Flash!! \n"); + return 0; + } + } /* JDEC */ + } + + sector = base; + for (j = 0; j < info->sector_count; j++) { + + info->start[j] = sector; + sector += erase_region_size; + info->protect[j] = 0; /* default: not protected */ + } + + /* limit Max SPI CLK to 50MHz (Datasheet v1.2) */ + if (WriteClk > 50) WriteClk = 50; + if (EraseClk > 50) EraseClk = 50; + if (ReadClk > 50) ReadClk = 50; + + info->tCK_Write = ast_spi_calculate_divisor(WriteClk*1000000); + info->tCK_Erase = ast_spi_calculate_divisor(EraseClk*1000000); + info->tCK_Read = ast_spi_calculate_divisor(ReadClk*1000000); + + /* unprotect flash */ + write_status_register(info, 0); + + if (info->quadport) + write_status_register(info, 0x40); /* enable QE */ + + if (info->address32) { +#ifndef AST_SOC_G5 + reg = *((volatile ulong*) 0x1e6e2070); /* set H/W Trappings */ + reg |= 0x10; + *((volatile ulong*) 0x1e6e2070) = reg; +#endif + reg = *((volatile ulong*) (info->reg_base + 0x4)); /* enable 32b control bit*/ + reg |= (0x01 << info->CE); + *((volatile ulong*) (info->reg_base + 0x4)) = reg; + + /* set flash chips to 32bits addressing mode */ + if ((info->flash_id & 0xFF) == 0x01) /* Spansion */ + enable4b_spansion(info); + else if ((info->flash_id & 0xFF) == 0x20) /* Numonyx */ + enable4b_numonyx(info); + else /* MXIC, Winbond */ + enable4b(info); + } + + reset_flash(info); +// printf("%08x \n", info->size); + return (info->size); +} + +/*-----------------------------------------------------------------------*/ +unsigned long flash_init (void) +{ + unsigned long size = 0; + int i; + + *((volatile ulong*) AST_FMC_BASE) |= 0x800f0000; /* enable Flash Write */ + + /* Init: FMC */ + /* BANK 0 : FMC CS0 , 1: FMC CS1, */ + for (i = 0; i < CONFIG_FMC_CS; ++i) { + flash_info[i].sysspi = 0; + flash_info[i].reg_base = AST_FMC_BASE; + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].CE = i; + switch(i) { + case 0: + size += flash_info[i].size = flash_get_size(AST_FMC_CS0_BASE, &flash_info[i]); + break; + case 1: + size += flash_info[i].size = flash_get_size(AST_FMC_CS1_BASE, &flash_info[i]); + break; + default: + printf("TODO ~~~~ \n"); + break; + } + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", + i, flash_info[i].size, flash_info[i].size << 20); + } + } + + /* BANK 2:SYSSPI CS0 */ +#ifdef CONFIG_SPI0_CS + //pin switch by trap[13:12] -- [0:1] Enable SPI Master + ast_scu_spi_master(1); /* enable SPI master */ + *((volatile ulong*) AST_FMC_SPI0_BASE) |= 0x10000; /* enable Flash Write */ + flash_info[CONFIG_FMC_CS].sysspi = 1; + flash_info[CONFIG_FMC_CS].reg_base = AST_FMC_SPI0_BASE; + flash_info[CONFIG_FMC_CS].flash_id = FLASH_UNKNOWN; + flash_info[CONFIG_FMC_CS].CE = 0; + size += flash_info[CONFIG_FMC_CS].size = flash_get_size(AST_SPI0_CS0_BASE, &flash_info[CONFIG_FMC_CS]); + if (flash_info[2].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 2 SYS SPI - Size = 0x%08lx = %ld MB\n", + flash_info[CONFIG_FMC_CS].size, flash_info[CONFIG_FMC_CS].size << 20); + } +#endif + + /* Monitor protection ON by default */ +#if (CONFIG_MONITOR_BASE >= AST_FMC_CS0_BASE) + flash_protect (FLAG_PROTECT_SET, + CONFIG_MONITOR_BASE, + CONFIG_MONITOR_BASE + monitor_flash_len - 1, + flash_get_info(CONFIG_MONITOR_BASE)); +#endif + + /* Environment protection ON by default */ +#ifdef CONFIG_ENV_IS_IN_FLASH + flash_protect (FLAG_PROTECT_SET, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, + flash_get_info(CONFIG_ENV_ADDR)); +#endif + + /* Redundant environment protection ON by default */ +#ifdef CONFIG_ENV_ADDR_REDUND + flash_protect (FLAG_PROTECT_SET, + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1, + flash_get_info(CONFIG_ENV_ADDR_REDUND)); +#endif + + return (size); +} + +void memmove_dma(void * dest,const void *src,size_t count) +{ + ulong count_align, poll_time, data; + + count_align = (count + 3) & 0xFFFFFFFC; /* 4-bytes align */ + poll_time = 100; /* set 100 us as default */ + + /* force end of burst read */ + *(volatile ulong *) (AST_FMC_BASE + CS0_CTRL) |= CE_HIGH; + *(volatile ulong *) (AST_FMC_BASE + CS0_CTRL) &= ~CE_HIGH; + + *(ulong *) (AST_FMC_BASE + REG_FLASH_DMA_CONTROL) = (ulong) (~FLASH_DMA_ENABLE); + *(ulong *) (AST_FMC_BASE + REG_FLASH_DMA_FLASH_BASE) = (ulong) (src); + *(ulong *) (AST_FMC_BASE + REG_FLASH_DMA_DRAM_BASE) = (ulong) (dest); + *(ulong *) (AST_FMC_BASE + REG_FLASH_DMA_LENGTH) = (ulong) (count_align); + *(ulong *) (AST_FMC_BASE + REG_FLASH_DMA_CONTROL) = (ulong) (FLASH_DMA_ENABLE); + + /* wait poll */ + do { + udelay(poll_time); + data = *(ulong *) (AST_FMC_BASE + REG_FLASH_INTERRUPT_STATUS); + } while (!(data & FLASH_STATUS_DMA_READY)); + + /* clear status */ + *(ulong *) (AST_FMC_BASE + REG_FLASH_INTERRUPT_STATUS) |= FLASH_STATUS_DMA_CLEAR; +} diff --git a/arch/arm/mach-aspeed/platform_g4.S b/arch/arm/mach-aspeed/platform_g4.S new file mode 100644 index 0000000000..cbe6786f9a --- /dev/null +++ b/arch/arm/mach-aspeed/platform_g4.S @@ -0,0 +1,3092 @@ +/* + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +/* + * Board specific setup info + * + ****************************************************************************** + * ASPEED Technology Inc. + * AST2300/AST2400 DDR2/DDR3 SDRAM controller initialization and calibration sequence + * + * Gary Hsu, + * + * Release date: 2015.02.09 formal release for SDK0.61 + * + * Modified list from v0.23 + * EC1. Modify DQIDLY and DQSI-MCLK2X calibration algorithm + * EC2. Remove pass 2 DQIDLY finetune process + * EC3. Modify ECC code + * EC4. Add AST2400 supporting + * EC5. Add SPI timing calibration for AST2400 + * EC6. Remove AST2300-A0 PCI-e workaround + * EC7. Add CK duty calibration for AST2400 + * EC8. Remove #define CONFIG_DRAM_UART_OUT, default has message output to UART5 + * EC9. Add DRAM size auto-detection + * EC10. Add GPIO register clear when watchdog reboot (only for AST2400) + * EC11. Move the "Solve ASPM" code position of AST2300 to avoid watchdog reset + * + * Modified list from v0.53 + * EC1. Add solution of LPC lock issue due to watchdog reset. (AP note A2300-11) + * + * Modified list from v0.56 + * EC1. Fix read DQS input mask window too late issue if DRAM's t_DQSCK is earlier too much + * (ex. Nanya NT5CB64M16FP) + * 1. Change init value of MCR18[4] from '1' to '0' + * 2. Add CBR4 code to finetune MCR18[4] + * + * Modified list from v0.59 + * EC1. Add DQS input gating window delay tuning (1/2 T) when CBR retry + * EC2. Modify DLL1 MAdj = 0x4C + * + * Modified list from v0.60 + * EC1. Modify DDR2 init preliminary size to 1Gbit, and BL=4. + * + * Optional define variable + * 1. DRAM Speed // + * CONFIG_DRAM_336 // 336MHz (DDR-667) + * CONFIG_DRAM_408 // 408MHz (DDR-800) (default) + * 2. ECC Function enable + * CONFIG_DRAM_ECC // define to enable ECC function + * // when enabled, must define the ECC protected memory size at 0x1e6e0054 + * 3. UART5 message output // + * CONFIG_DRAM_UART_38400 // set the UART baud rate to 38400, default is 115200 + ****************************************************************************** + */ + +#include +#include +/****************************************************************************** + Calibration Macro Start + Usable registers: + r0, r1, r2, r3, r5, r6, r7, r8, r9, r10, r11 + ******************************************************************************/ +/* PATTERN_TABLE, + init_delay_timer, + check_delay_timer, + clear_delay_timer, + record_dll2_pass_range, + record_dll2_pass_range_h, + are for DRAM calibration */ + +PATTERN_TABLE: + .word 0xff00ff00 + .word 0xcc33cc33 + .word 0xaa55aa55 + .word 0x88778877 + .word 0x92cc4d6e @ 5 + .word 0x543d3cde + .word 0xf1e843c7 + .word 0x7c61d253 + .word 0x00000000 @ 8 + + .macro init_delay_timer + ldr r0, =0x1e782024 @ Set Timer3 Reload + str r2, [r0] + + ldr r0, =0x1e6c0038 @ Clear Timer3 ISR + ldr r1, =0x00040000 + str r1, [r0] + + ldr r0, =0x1e782030 @ Enable Timer3 + ldr r1, [r0] + mov r2, #7 + orr r1, r1, r2, lsl #8 + str r1, [r0] + + ldr r0, =0x1e6c0090 @ Check ISR for Timer3 timeout + .endm + + .macro check_delay_timer + ldr r1, [r0] + bic r1, r1, #0xFFFBFFFF + mov r2, r1, lsr #18 + cmp r2, #0x01 + .endm + + .macro clear_delay_timer + ldr r0, =0x1e782030 @ Disable Timer3 + ldr r1, [r0] + bic r1, r1, #0x00000F00 + str r1, [r0] + + ldr r0, =0x1e6c0038 @ Clear Timer3 ISR + ldr r1, =0x00040000 + str r1, [r0] + .endm + + .macro record_dll2_pass_range + ldr r1, [r0] + bic r2, r1, #0xFFFFFF00 + cmp r2, r3 @ record min + bicgt r1, r1, #0x000000FF + orrgt r1, r1, r3 + bic r2, r1, #0xFFFF00FF + cmp r3, r2, lsr #8 @ record max + bicgt r1, r1, #0x0000FF00 + orrgt r1, r1, r3, lsl #8 + str r1, [r0] + .endm + + .macro record_dll2_pass_range_h + ldr r1, [r0] + bic r2, r1, #0xFF00FFFF + mov r2, r2, lsr #16 + cmp r2, r3 @ record min + bicgt r1, r1, #0x00FF0000 + orrgt r1, r1, r3, lsl #16 + bic r2, r1, #0x00FFFFFF + cmp r3, r2, lsr #24 @ record max + bicgt r1, r1, #0xFF000000 + orrgt r1, r1, r3, lsl #24 + str r1, [r0] + .endm + + .macro init_spi_checksum + ldr r0, =0x1e620084 + ldr r1, =0x20010000 + str r1, [r0] + ldr r0, =0x1e62008C + ldr r1, =0x20000200 + str r1, [r0] + ldr r0, =0x1e620080 + ldr r1, =0x0000000D + orr r2, r2, r7 + orr r1, r1, r2, lsl #8 + and r2, r6, #0xF + orr r1, r1, r2, lsl #4 + str r1, [r0] + ldr r0, =0x1e620008 + ldr r2, =0x00000800 + .endm + +/****************************************************************************** + Calibration Macro End + ******************************************************************************/ +LPC_Patch: @ load to SRAM base 0x1e720400 + str r1, [r0] + str r3, [r2] + bic r1, r1, #0xFF +LPC_Patch_S1: + subs r5, r5, #0x01 + moveq pc, r8 + ldr r3, [r2] + tst r3, #0x01 + movne pc, r8 + mov pc, r7 +LPC_Patch_S2: @ load to SRAM base 0x1e720480 + str r1, [r0] + mov pc, r9 +LPC_Patch_E: + +.globl lowlevel_init +lowlevel_init: + +init_dram: + /* save lr */ + mov r4, lr +/* Test - DRAM initial time */ + ldr r0, =0x1e782044 + ldr r1, =0xFFFFFFFF + str r1, [r0] + + ldr r0, =0x1e782030 + ldr r1, [r0] + bic r1, r1, #0x0000F000 + str r1, [r0] + mov r2, #3 + orr r1, r1, r2, lsl #12 + str r1, [r0] +/* Test - DRAM initial time */ + + /*Set Scratch register Bit 7 before initialize*/ + ldr r0, =0x1e6e2000 + ldr r1, =0x1688a8a8 + str r1, [r0] + + ldr r0, =0x1e6e2040 + ldr r1, [r0] + orr r1, r1, #0x80 + str r1, [r0] + + /* Fix LPC lock issue for AST2300 */ + ldr r0, =0x1e6e207c @ Check AST2300 + ldr r1, [r0] + mov r1, r1, lsr #24 + cmp r1, #0x01 + bne lpc_recover_end @ not match AST2300 + + mov r3, #0x0 +lpc_recover_check: + ldr r0, =0x1e78900c @ check HICR3[4]=0x1 + ldr r1, [r0] + tst r1, #0x10 + beq lpc_recover_end + ldr r0, =0x1e789004 @ check HICR1[7]=0x1 + ldr r1, [r0] + tst r1, #0x80 + beq lpc_recover_end + ldr r0, =0x1e7890a0 @ check LHCR0[27:24]=0x6 + ldr r1, [r0] + mov r1, r1, lsr #24 + and r1, r1, #0xF + cmp r1, #0x06 + bne lpc_recover_end + add r3, r3, #0x01 + cmp r3, #0x5 @ repeat 5 times + ble lpc_recover_check + + mov r3, #0x0 +lpc_recover_init: + ldr r0, =0x1e7890a4 @ set LHCR1[1:0]=0x0 + ldr r1, =0x00000000 + str r1, [r0] + add r3, r3, #0x01 + cmp r3, #0x20 + bge lpc_recover_end + ldr r1, [r0] + tst r1, #0x01 + bne lpc_recover_init + + ldr r0, =0x1e7890b0 @ set LHCR4[7:0]=0xFF + ldr r1, =0x000000FF + str r1, [r0] + ldr r0, =0x1e7890b4 @ set LHCR5[31:0]=0xFFFFFFFF + ldr r1, =0xFFFFFFFF + str r1, [r0] + ldr r0, =0x1e7890b8 @ set LHCR6[31:0]=0xFFFFFFFF + str r1, [r0] + + adr r6, LPC_Patch + adr r7, LPC_Patch_S2 + ldr r0, =0x1e720400 +copy_lpc_patch_1: + ldr r1, [r6] + str r1, [r0] + add r6, r6, #0x4 + add r0, r0, #0x4 + cmp r6, r7 + bne copy_lpc_patch_1 + + adr r6, LPC_Patch_S2 + adr r7, LPC_Patch_E + ldr r0, =0x1e720480 +copy_lpc_patch_2: + ldr r1, [r6] + str r1, [r0] + add r6, r6, #0x4 + add r0, r0, #0x4 + cmp r6, r7 + bne copy_lpc_patch_2 + + ldr r0, =0x1e7890a0 @ set LHCR0[31:0]=0xFFFFFF01 + ldr r1, =0xFFFFFF01 + add r2, r0, #0x4 + mov r3, #0x01 + mov r5, #0x10 + adr r9, lpc_recover_end + adr r6, LPC_Patch + adr r7, LPC_Patch_S1 + sub r6, r7, r6 + ldr r7, =0x1e720400 + add r7, r7, r6 + ldr r8, =0x1e720480 + ldr pc, =0x1e720400 + +lpc_recover_end: + ldr r0, =0x1e7890a0 @ set LHCR0[31:0]=0xFFFFFF00 + ldr r1, =0xFFFFFF00 + str r1, [r0] + /* Fix LPC lock issue for AST2300 */ + + /* Check Scratch Register Bit 6 */ + ldr r0, =0x1e6e2040 + ldr r1, [r0] + bic r1, r1, #0xFFFFFFBF + mov r2, r1, lsr #6 + cmp r2, #0x01 + beq platform_exit + + ldr r2, =0x033103F1 @ load PLL parameter for 24Mhz CLKIN (396:324) +/* ldr r2, =0x019001F0 @ load PLL parameter for 24Mhz CLKIN (408:336) */ + ldr r0, =0x1e6e207c @ Check Revision ID + ldr r1, [r0] + mov r1, r1, lsr #24 + cmp r1, #0x02 + bne set_MPLL @ not match AST2400 + + ldr r0, =0x1e6e2070 @ Check CLKIN freq + ldr r1, [r0] + mov r1, r1, lsr #23 + tst r1, #0x01 + ldrne r2, =0x017001D0 @ load PLL parameter for 25Mhz CLKIN (400:325) + +set_MPLL: + ldr r0, =0x1e6e2020 @ M-PLL (DDR SDRAM) Frequency + ldr r1, =0xFFFF +#if defined(CONFIG_DRAM_336) + mov r2, r2, lsr #16 +#endif + and r1, r2, r1 + str r1, [r0] + +/* Debug - UART console message */ + ldr r0, =0x1e78400c + mov r1, #0x83 + str r1, [r0] + + ldr r0, =0x1e6e202c + ldr r2, [r0] + mov r2, r2, lsr #12 + tst r2, #0x01 + ldr r0, =0x1e784000 + moveq r1, #0x0D @ Baudrate 115200 + movne r1, #0x01 @ Baudrate 115200, div13 +#if defined(CONFIG_DRAM_UART_38400) + moveq r1, #0x27 @ Baudrate 38400 + movne r1, #0x03 @ Baudrate 38400 , div13 +#endif + str r1, [r0] + + ldr r0, =0x1e784004 + mov r1, #0x00 + str r1, [r0] + + ldr r0, =0x1e78400c + mov r1, #0x03 + str r1, [r0] + + ldr r0, =0x1e784008 + mov r1, #0x07 + str r1, [r0] + + ldr r0, =0x1e784000 + mov r1, #0x0D @ '\r' + str r1, [r0] + mov r1, #0x0A @ '\n' + str r1, [r0] + mov r1, #0x44 @ 'D' + str r1, [r0] + mov r1, #0x52 @ 'R' + str r1, [r0] + mov r1, #0x41 @ 'A' + str r1, [r0] + mov r1, #0x4D @ 'M' + str r1, [r0] + mov r1, #0x20 @ ' ' + str r1, [r0] + mov r1, #0x49 @ 'I' + str r1, [r0] + mov r1, #0x6E @ 'n' + str r1, [r0] + mov r1, #0x69 @ 'i' + str r1, [r0] + mov r1, #0x74 @ 't' + str r1, [r0] + mov r1, #0x2D @ '-' + str r1, [r0] + mov r1, #0x44 @ 'D' + str r1, [r0] + mov r1, #0x44 @ 'D' + str r1, [r0] + mov r1, #0x52 @ 'R' + str r1, [r0] +/* Debug - UART console message */ + + /* Delay about 100us */ + ldr r0, =0x1e782030 @ Init Timer3 Control + ldr r1, [r0] + bic r1, r1, #0x00000F00 + str r1, [r0] + + ldr r2, =0x00000064 @ Set Timer3 Reload = 100 us + init_delay_timer +delay_0: + check_delay_timer + bne delay_0 + clear_delay_timer + /* end delay 100us */ + +/****************************************************************************** + Init DRAM common registers + ******************************************************************************/ + ldr r0, =0x1e6e0000 + ldr r1, =0xfc600309 + str r1, [r0] + + /* Reset MMC */ + ldr r1, =0x00000000 + ldr r0, =0x1e6e0034 + str r1, [r0] + ldr r0, =0x1e6e0018 + str r1, [r0] + ldr r0, =0x1e6e0024 + str r1, [r0] + ldr r0, =0x1e6e0064 @ REG_MADJ, power down DLL + str r1, [r0] + + ldr r1, =0x00034C4C @ REG_MADJ, reset DLL + str r1, [r0] + + ldr r0, =0x1e6e0068 @ REG_SADJ + ldr r1, =0x00001800 + str r1, [r0] + + /* Delay about 10us */ + ldr r2, =0x0000000B @ Set Timer3 Reload = 10 us + init_delay_timer +delay_1: + check_delay_timer + bne delay_1 + clear_delay_timer + /* end delay 10us */ + + ldr r0, =0x1e6e0064 @ REG_MADJ | 0xC0000, enable DLL + ldr r1, [r0] + ldr r2, =0xC0000 + orr r1, r1, r2 + str r1, [r0] + + ldr r0, =0x1e6e0008 + ldr r1, =0x0090040f /* VGA */ + str r1, [r0] + + ldr r0, =0x1e6e0018 + ldr r1, =0x4000A120 + str r1, [r0] + + ldr r0, =0x1e6e0018 + ldr r1, =0x00000120 + str r1, [r0] + + ldr r0, =0x1e6e0038 + ldr r1, =0x00000000 + str r1, [r0] + + ldr r0, =0x1e6e0040 + ldr r1, =0xFF444444 + str r1, [r0] + + ldr r0, =0x1e6e0044 + ldr r1, =0x22222222 + str r1, [r0] + + ldr r0, =0x1e6e0048 + ldr r1, =0x22222222 + str r1, [r0] + + ldr r0, =0x1e6e004c + ldr r1, =0x22222222 + str r1, [r0] + + ldr r0, =0x1e6e0050 + ldr r1, =0x80000000 + str r1, [r0] + + ldr r0, =0x1e6e0050 + ldr r1, =0x00000000 + str r1, [r0] + + ldr r0, =0x1e6e0054 + ldr r1, =0x00000000 + str r1, [r0] + + ldr r0, =0x1e6e0060 @ REG_DRV + ldr r1, =0x000000FA @ 408 MHz +#if defined(CONFIG_DRAM_336) + ldr r1, =0x000000FA +#endif + str r1, [r0] + + ldr r0, =0x1e6e0070 + ldr r1, =0x00000000 + str r1, [r0] + + ldr r0, =0x1e6e0074 + ldr r1, =0x00000000 + str r1, [r0] + + ldr r0, =0x1e6e0078 + ldr r1, =0x00000000 + str r1, [r0] + + ldr r0, =0x1e6e007c + ldr r1, =0x00000000 + str r1, [r0] + + ldr r0, =0x1e6e0080 + ldr r1, =0x00000000 + str r1, [r0] + + ldr r0, =0x1e6e0084 + ldr r1, =0x00FFFFFF + str r1, [r0] + + ldr r0, =0x1e6e0088 @ REG_DQIDLY + ldr r1, =0x00000089 @ 408 MHz +#if defined(CONFIG_DRAM_336) + ldr r1, =0x00000074 +#endif + str r1, [r0] + + ldr r0, =0x1e6e0020 @ REG_DQSIC + ldr r1, =0x000000E2 @ 408 MHz +#if defined(CONFIG_DRAM_336) + ldr r1, =0x000000BA +#endif + str r1, [r0] + + /* Delay about 10us */ + ldr r2, =0x0000000B @ Set Timer3 Reload = 10 us + init_delay_timer +delay_2: + check_delay_timer + bne delay_2 + clear_delay_timer + /* end delay 10us */ + + /* Check DRAM Type by H/W Trapping */ + ldr r0, =0x1e6e2070 + ldr r1, [r0] + bic r1, r1, #0xFEFFFFFF @ bit[24]=1 => DDR2 + mov r2, r1, lsr #24 + cmp r2, #0x01 + beq ddr2_init + b ddr3_init +.LTORG + +/****************************************************************************** + DDR3 Init + + tRCD = 15 ns + tRAS = 37.5 ns + tRRD = max(4 CK,10 ns) + tRP = 15 ns + tRFC = 110ns/1Gbit, 160ns/2Gbit, 300ns/4Gbit + tRTP = max(4 CK,7.5 ns) + tWR = 15 ns + tXSNR = max(10 CK,200 ns) + tWTR = max(4 CK,7.5 ns) + tFAW = 50 ns + tMRD = max(15 CK,20 ns) + ******************************************************************************/ +ddr3_init: +/* Debug - UART console message */ + ldr r0, =0x1e784000 + mov r1, #0x33 @ '3' + str r1, [r0] + mov r1, #0x0D @ '\r' + str r1, [r0] + mov r1, #0x0A @ '\n' + str r1, [r0] +/* Debug - UART console message */ + + ldr r0, =0x1e6e0004 + ldr r1, =0x00000531 @ Default set to 1Gbit + str r1, [r0] + + ldr r0, =0x1e6e0010 @ REG_AC1 + ldr r1, =0x33302825 @ 408 MHz +#if defined(CONFIG_DRAM_336) + ldr r1, =0x22202725 +#endif + str r1, [r0] + + /* Check DRAM CL Timing by H/W Trapping */ + ldr r0, =0x1e6e2070 + ldr r1, [r0] + bic r1, r1, #0xF9FFFFFF + mov r2, r1, lsr #9 @ Set CL + ldr r1, =0x00020000 + add r2, r2, r1 + ldr r1, [r0] + bic r1, r1, #0xFBFFFFFF + mov r1, r1, lsr #6 @ Set CWL + orr r2, r2, r1 + ldr r1, =0x00300000 + add r2, r2, r1 + + ldr r0, =0x1e6e0014 @ REG_AC2 + ldr r1, =0xCC00963F @ 408 MHz +#if defined(CONFIG_DRAM_336) + ldr r1, =0xAA007636 +#endif + orr r1, r1, r2 + str r1, [r0] + + ldr r0, =0x1e6e0004 @ check 2400 mode + ldr r2, [r0] + mov r2, r2, lsr #10 + + ldr r0, =0x1e6e006c @ REG_IOZ + ldr r1, =0x00002312 @ 408 MHz +#if defined(CONFIG_DRAM_336) + ldr r1, =0x00002312 +#endif + tst r2, #0x01 + moveq r1, r1, lsr #8 + str r1, [r0] + + ldr r0, =0x1e6e0120 + mov r1, #0 + str r1, [r0] + tst r2, #0x01 @ check AST2300 + beq CBRDLL1_2300_Start + ldr r0, =0x1e6e207c @ check AST2400 revision A0 + ldr r1, [r0] + mov r1, r1, lsr #16 + and r1, r1, #0xFF + cmp r1, #0x0 + beq CBRDLL1_2300_Start + b CBRDLL1_2400_Start +MCLK2X_Phase_CBR_Done_DDR3: + ldr r0, =0x1e6e0018 + ldr r1, [r0] + orr r1, r1, #0x40 + str r1, [r0] + + ldr r0, =0x1e6e0034 + ldr r1, =0x00000001 + str r1, [r0] + + ldr r0, =0x1e6e000c + ldr r1, =0x00000040 + str r1, [r0] + + /* Delay about 400us */ + ldr r2, =0x00000190 @ Set Timer3 Reload = 400 us + init_delay_timer +delay3_4: + check_delay_timer + bne delay3_4 + clear_delay_timer + /* end delay 400us */ + + /* Check DRAM CL Timing by H/W Trapping */ + ldr r0, =0x1e6e2070 + ldr r1, [r0] + bic r1, r1, #0xF9FFFFFF + mov r2, r1, lsr #21 @ Set CL + ldr r1, =0x00000010 + add r2, r2, r1 + ldr r1, [r0] + bic r1, r1, #0xFBFFFFFF + mov r1, r1, lsr #7 @ Set CWL + orr r2, r2, r1 + + ldr r0, =0x1e6e002c @ REG_MRS + ldr r1, =0x04001700 @ 408 MHz +#if defined(CONFIG_DRAM_336) + ldr r1, =0x04001500 +#endif + orr r1, r1, r2 + str r1, [r0] + + ldr r0, =0x1e6e0030 @ REG_EMRS + ldr r1, =0x00000000 @ 408 MHz +#if defined(CONFIG_DRAM_336) + ldr r1, =0x00000000 +#endif + str r1, [r0] + + ldr r0, =0x1e6e0028 @ Set EMRS2 + ldr r1, =0x00000005 + str r1, [r0] + + ldr r0, =0x1e6e0028 @ Set EMRS3 + ldr r1, =0x00000007 + str r1, [r0] + + ldr r0, =0x1e6e0028 @ Set EMRS + ldr r1, =0x00000003 + str r1, [r0] + + ldr r0, =0x1e6e0028 @ Set MRS + ldr r1, =0x00000001 + str r1, [r0] + + ldr r0, =0x1e6e002c @ REG_MRS + ldr r1, =0x04001600 @ 408 MHz +#if defined(CONFIG_DRAM_336) + ldr r1, =0x04001400 +#endif + orr r1, r1, r2 + str r1, [r0] + + ldr r0, =0x1e6e000c @ Refresh 8 times + ldr r1, =0x00005C48 + str r1, [r0] + + ldr r0, =0x1e6e0028 @ Set MRS + ldr r1, =0x00000001 + str r1, [r0] + + ldr r0, =0x1e6e000c @ Set refresh cycle + ldr r1, =0x00002001 + str r1, [r0] + + ldr r0, =0x1e6e0014 + ldr r1, [r0] + bic r1, r1, #0xFFF9FFFF + mov r2, r1, lsr #3 @ get CL + + ldr r0, =0x1e6e0034 @ REG_PWC + ldr r1, =0x00000303 @ 408 MHz +#if defined(CONFIG_DRAM_336) + ldr r1, =0x00000303 +#endif + orr r1, r1, r2 + str r1, [r0] + + b Calibration_Start +.LTORG +/****************************************************************************** + End DDR3 Init + ******************************************************************************/ + +/****************************************************************************** + DDR2 Init + + tRCD = 15 ns + tRAS = 45 ns + tRRD = 10 ns + tRP = 15 ns + tRFC = 105ns/512Mbit, 127.5ns/1Gbit, 197.5ns/2Gbit, 327.5ns/4Gbit + tRTP = 7.5 ns + tWR = 15 ns + tXSNR = 200 ns + tWTR = 7.5 ns + tFAW = 50 ns + tMRD = 4 CK + ******************************************************************************/ +ddr2_init: +/* Debug - UART console message */ + ldr r0, =0x1e784000 + mov r1, #0x32 @ '2' + str r1, [r0] + mov r1, #0x0D @ '\r' + str r1, [r0] + mov r1, #0x0A @ '\n' + str r1, [r0] +/* Debug - UART console message */ + + ldr r0, =0x1e6e0004 + ldr r1, =0x00000521 @ Default set to 1Gbit + str r1, [r0] + + ldr r0, =0x1e6e0010 @ REG_AC1 + ldr r1, =0x33302714 @ 408 MHz +#if defined(CONFIG_DRAM_336) + ldr r1, =0x22201613 +#endif + str r1, [r0] + + /* Check DRAM CL Timing by H/W Trapping */ + ldr r0, =0x1e6e2070 + ldr r1, [r0] + bic r1, r1, #0xF9FFFFFF + mov r2, r1, lsr #5 @ Set CL + mov r1, r2, lsr #4 @ Set CWL + orr r2, r2, r1 + ldr r1, =0x00110000 + add r2, r2, r1 + + ldr r0, =0x1e6e0014 @ REG_AC2 + ldr r1, =0xCC00B03F @ 408 MHz +#if defined(CONFIG_DRAM_336) + ldr r1, =0xAA00903B +#endif + orr r1, r1, r2 + str r1, [r0] + + ldr r0, =0x1e6e0004 @ check 2400 mode + ldr r2, [r0] + mov r2, r2, lsr #10 + + ldr r0, =0x1e6e006c @ REG_IOZ + ldr r1, =0x00002312 @ 408 MHz +#if defined(CONFIG_DRAM_336) + ldr r1, =0x00002312 +#endif + tst r2, #0x01 + moveq r1, r1, lsr #8 + str r1, [r0] + + ldr r0, =0x1e6e0120 + mov r1, #1 + str r1, [r0] + tst r2, #0x01 @ check AST2300 + beq CBRDLL1_2300_Start + ldr r0, =0x1e6e207c @ check AST2400 revision A0 + ldr r1, [r0] + mov r1, r1, lsr #16 + and r1, r1, #0xFF + cmp r1, #0x0 + beq CBRDLL1_2300_Start + b CBRDLL1_2400_Start +MCLK2X_Phase_CBR_Done_DDR2: + + ldr r0, =0x1e6e0034 + ldr r1, =0x00000001 + str r1, [r0] + + ldr r0, =0x1e6e000c + ldr r1, =0x00000000 + str r1, [r0] + + /* Delay about 400us */ + ldr r2, =0x00000190 @ Set Timer3 Reload = 400 us + init_delay_timer +delay2_4: + check_delay_timer + bne delay2_4 + clear_delay_timer + /* end delay 400us */ + + /* Check DRAM CL Timing by H/W Trapping */ + ldr r0, =0x1e6e2070 + ldr r1, [r0] + bic r1, r1, #0xF9FFFFFF + mov r2, r1, lsr #21 @ Set CL + ldr r1, =0x00000040 + orr r2, r2, r1 + + ldr r0, =0x1e6e002c @ REG_MRS + ldr r1, =0x00000D02 @ 408 MHz +#if defined(CONFIG_DRAM_336) + ldr r1, =0x00000B02 +#endif + orr r1, r1, r2 + str r1, [r0] + + ldr r0, =0x1e6e0030 @ REG_EMRS + ldr r1, =0x00000040 @ 408 MHz +#if defined(CONFIG_DRAM_336) + ldr r1, =0x00000040 +#endif + str r1, [r0] + + ldr r0, =0x1e6e0028 @ Set EMRS2 + ldr r1, =0x00000005 + str r1, [r0] + + ldr r0, =0x1e6e0028 @ Set EMRS3 + ldr r1, =0x00000007 + str r1, [r0] + + ldr r0, =0x1e6e0028 @ Set EMRS + ldr r1, =0x00000003 + str r1, [r0] + + ldr r0, =0x1e6e0028 @ Set MRS + ldr r1, =0x00000001 + str r1, [r0] + + ldr r0, =0x1e6e000c @ Refresh 8 times + ldr r1, =0x00005C08 + str r1, [r0] + + ldr r0, =0x1e6e002c @ REG_MRS + ldr r1, =0x00000C02 @ 408 MHz +#if defined(CONFIG_DRAM_336) + ldr r1, =0x00000A02 +#endif + orr r1, r1, r2 + str r1, [r0] + + ldr r0, =0x1e6e0028 @ Set MRS + ldr r1, =0x00000001 + str r1, [r0] + + ldr r0, =0x1e6e0030 @ REG_EMRS + ldr r1, =0x000003C0 @ 408 MHz +#if defined(CONFIG_DRAM_336) + ldr r1, =0x000003C0 +#endif + str r1, [r0] + + ldr r0, =0x1e6e0028 @ Set EMRS + ldr r1, =0x00000003 + str r1, [r0] + + ldr r0, =0x1e6e0030 @ REG_EMRS + ldr r1, =0x00000040 @ 408 MHz +#if defined(CONFIG_DRAM_336) + ldr r1, =0x00000040 +#endif + str r1, [r0] + + ldr r0, =0x1e6e0028 @ Set EMRS + ldr r1, =0x00000003 + str r1, [r0] + + ldr r0, =0x1e6e000c @ Set refresh cycle + ldr r1, =0x00002001 + str r1, [r0] + + ldr r0, =0x1e6e0014 + ldr r1, [r0] + bic r1, r1, #0xFFF9FFFF + mov r2, r1, lsr #3 @ get CL + + ldr r0, =0x1e6e0034 @ REG_PWC + ldr r1, =0x00000503 @ 408 MHz +#if defined(CONFIG_DRAM_336) + ldr r1, =0x00000503 +#endif + orr r1, r1, r2 + str r1, [r0] + + b Calibration_Start +.LTORG +/****************************************************************************** + End DDR2 Init + ******************************************************************************/ +/****************************************************************************** + DDR CK duty finetune program + SRAM buffer definition + 0x1E720204 : gdll golden DLL1 record + 0x1E720208 : gduty golden duty setting record + 0x1E72020C : gdutysum golden duty data record + 0x1E720210 : duty record of delay 0 invert + 0x1E720214 : duty record of delay 1 invert + .... + 0x1E72024C : duty record of delay 15 invert + 0x1E720250 : duty record of delay 0 + 0x1E720254 : duty record of delay 1 + .... + 0x1E72028C : duty record of delay 15 + + Register usage + r0 - r3 = free + r4 = record the return pc value, do not use + r5 = free + r6 = free + r7 = duty count + r8 = gdll + r9 = gduty + r10 = gdutysum + ******************************************************************************/ +CBRDLL1_2400_Start: + ldr r0, =0x1e6e0120 + ldr r1, [r0] + orr r1, r1, #0x02 + str r1, [r0] + + ldr r1, =0x00000000 + ldr r0, =0x1e720204 + ldr r2, =0x1e7202a0 +init_sram_start0: + str r1, [r0] + add r0, r0, #4 + cmp r0, r2 + blt init_sram_start0 + + ldr r0, =0x1e6e0034 + mov r1, #0x20 + str r1, [r0] + + ldr r0, =0x1e6e0060 + ldr r1, [r0] + mov r2, #0x01 + orr r1, r1, r2, lsl #13 + str r1, [r0] + + mov r7, #0x0 @ init duty count + mov r8, #0x0 @ init gdll + mov r9, #0x0 @ init gduty + mov r10, #0x0 @ init gdutysum +cbrdll1_duty_start: + cmp r7, #32 + bge cbrdll1_duty_end + + ldr r0, =0x1e6e0018 + ldr r1, =0x00008120 + str r1, [r0] + + ldr r0, =0x1e6e0060 + ldr r1, [r0] + bic r1, r1, #0x00001F00 + orr r1, r1, r7, lsl #8 + mov r2, #0x10 + eor r1, r1, r2, lsl #8 + str r1, [r0] + + ldr r0, =0x1e6e0000 @ dummy read + ldr r1, [r0] + + b CBRDLL1_2300_Start +CBRDLL1_2400_Call: + + mov r5, #0x01 @ init dqidly count + mov r6, #0x00 @ init duty sum +cbrdll1_duty_cal_start: + cmp r5, #0x05 + bge cbrdll1_duty_cal_end + + ldr r0, =0x1e6e0018 + ldr r1, =0x00200120 + orr r1, r1, r5, lsl #16 + str r1, [r0] + + ldr r0, =0x1e6e0000 + ldr r1, [r0] + + ldr r0, =0x1e6e0018 + ldr r1, [r0] + mov r2, #0x10 + orr r1, r1, r2, lsl #24 + str r1, [r0] + + ldr r0, =0x1e6e0080 + ldr r1, =0x80000000 @ init duty cal waiting +cbrdll1_duty_cal_wait: + ldr r2, [r0] + tst r2, r1 + beq cbrdll1_duty_cal_wait + + ldr r0, =0x1e6e008c + ldr r2, [r0] + + ldr r0, =0x1e720210 + add r0, r0, r7, lsl #2 + str r2, [r0] + + ldr r1, =0xFFFF + and r3, r1, r2 + cmp r3, r1 + moveq r2, r2, lsr #16 + and r3, r1, r2 + add r6, r6, r3 + ldr r1, =0xF000 + cmp r3, r1 + blt cbrdll1_duty_cal_end + add r5, r5, #0x01 + b cbrdll1_duty_cal_start + +cbrdll1_duty_cal_end: + mov r6, r6, lsr #2 @ get dutysum + cmp r6, r10 @ check dutysum > gdutysum + ble cbrdll1_duty_next + ldr r0, =0x1e6e0068 + ldr r8, [r0] + eor r9, r7, #0x10 + mov r10, r6 + +cbrdll1_duty_next: + add r7, r7, #0x01 + cmp r7, #16 @ check duty >= 15 + blt cbrdll1_duty_start + ldr r0, =0xFA00 @ check gdutysum > 0xFA00 + cmp r10, r0 + blt cbrdll1_duty_start + +cbrdll1_duty_end: + ldr r0, =0x1e6e0060 + ldr r1, [r0] + bic r1, r1, #0x00001F00 + orr r1, r1, r9, lsl #8 + str r1, [r0] + + ldr r0, =0x1e6e0068 + bic r8, r8, #0xFF000000 + bic r8, r8, #0x00FF0000 + str r8, [r0] + + ldr r0, =0x1e720204 @ record result + str r8, [r0] + add r0, r0, #0x04 + str r9, [r0] + add r0, r0, #0x04 + str r10, [r0] + + ldr r0, =0x1e6e0018 + ldr r1, =0x00008120 + str r1, [r0] + ldr r0, =0x1e6e0000 @ dummy read + ldr r1, [r0] + ldr r0, =0x1e6e0018 + ldr r1, =0x00000120 + str r1, [r0] + + ldr r0, =0x1e6e0120 + ldr r1, [r0] + cmp r1, #0x3 + beq MCLK2X_Phase_CBR_Done_DDR2 + b MCLK2X_Phase_CBR_Done_DDR3 + +/****************************************************************************** + MCLK2X lock to MCLK program + r0 - r3 = free + r5 = madjmax + r6 = dllend + 0x1E720200 = 0x96cnt:failcnt:dllmax:dllmin + ******************************************************************************/ +CBRDLL1_2300_Start: + ldr r0, =0x1e6e0064 + ldr r5, [r0] + and r5, r5, #0xFF @ init madjmax + mov r6, r5 @ init dllend + + ldr r1, =0x000000ff + ldr r0, =0x1e720200 + str r1, [r0] @ init dllcnt2:dllmax:dllmin + + mov r3, #0x0 @ init loop count +cbrdll1_scan_start: + cmp r3, r6 + bge cbrdll1_scan_end + + ldr r0, =0x1e6e0018 + ldr r1, =0x00008120 + str r1, [r0] + + ldr r0, =0x1e6e0068 + mov r1, r3 + cmp r1, r5 + subge r1, r1, r5 + str r1, [r0] + + ldr r0, =0x1e6e0000 @ dummy read + ldr r1, [r0] + + ldr r0, =0x1e6e0018 + ldr r1, =0x00000120 + str r1, [r0] + + ldr r0, =0x1e6e0000 @ dummy read + ldr r1, [r0] + ldr r0, =0x1e6e0000 @ dummy read + ldr r1, [r0] + + ldr r0, =0x1e6e001c + ldr r1, [r0] + mov r1, r1, lsr #16 + and r1, r1, #0xFF + + and r2, r1, #0x96 + cmp r2, #0x96 + beq cbrdll1_scan_pass @ if (mclk2x_phase & 0x96) == 0x96 + ldr r0, =0x1e720200 + ldr r1, [r0] + mov r2, r1, lsr #8 + ands r2, r2, #0xFF @ get dllmax + beq cbrdll1_scan_next @ if dllmax == 0 + mov r2, r1, lsr #16 + and r2, r2, #0xFF + add r2, r2, #0x01 + cmp r2, #0x02 + movge r6, r3 + bic r1, r1, #0x00FF0000 + orr r1, r1, r2, lsl #16 + str r1, [r0] + b cbrdll1_scan_next + +cbrdll1_scan_pass: + cmp r3, #0x0 @ if dll = 0 + moveq r3, #0x0F + addeq r6, r6, #0x10 + beq cbrdll1_scan_next + ldr r0, =0x1e720200 + ldr r2, [r0] + cmp r1, #0x96 + bne cbrdll1_scan_pass2 + mov r1, r2, lsr #24 + add r1, r1, #0x01 + bic r2, r2, #0xFF000000 + orr r2, r2, r1, lsl #24 + cmp r1, #0x03 @ check (phase == 0x96) count == 3 + bicge r2, r2, #0x0000FF00 + bicge r2, r2, #0x000000FF + orrge r2, r2, r3, lsl #8 + orrge r2, r2, r3 + str r2, [r0] + bge cbrdll1_scan_end + +cbrdll1_scan_pass2: + and r1, r2, #0xFF @ if(dllmin > dll) + cmp r1, r3 + bicgt r2, r2, #0x000000FF + orrgt r2, r2, r3 + + mov r1, r2, lsr #8 @ if(dllmax < dll) + and r1, r1, #0xFF + cmp r1, r3 + biclt r2, r2, #0x0000FF00 + orrlt r2, r2, r3, lsl #8 + + bic r2, r2, #0x00FF0000 + str r2, [r0] + +cbrdll1_scan_next: + add r3, r3, #0x01 + b cbrdll1_scan_start + +cbrdll1_scan_end: + ldr r0, =0x1e720200 + ldr r1, [r0] + mov r2, r1, lsr #8 @ get dllmax + ands r2, r2, #0xFF + bne cbrdll1_scan_done @ if(dllmax != 0) + ldr r0, =0x1e6e0064 + ldr r3, [r0] + bic r1, r3, #0x000C0000 + str r1, [r0] + add r0, r0, #0x04 + mov r1, #0x0 + str r1, [r0] + + /* Delay about 10us */ + ldr r2, =0x0000000A @ Set Timer3 Reload = 10 us + init_delay_timer +delay0_1: + check_delay_timer + bne delay0_1 + clear_delay_timer + /* end delay 10us */ + + ldr r0, =0x1e6e0064 + str r3, [r0] + + /* Delay about 10us */ + ldr r2, =0x0000000A @ Set Timer3 Reload = 10 us + init_delay_timer +delay0_2: + check_delay_timer + bne delay0_2 + clear_delay_timer + /* end delay 10us */ + + b CBRDLL1_2300_Start + +cbrdll1_scan_done: + and r1, r1, #0xFF + add r1, r1, r2 + mov r6, r1, lsr #1 @ dll1.0 = (dllmin + dllmax) >> 1 + cmp r6, r5 + subge r6, r6, r5 + add r3, r6, r5, lsr #2 @ dll1.1 = dll1.0 + (MADJ >> 2) + + ldr r0, =0x1e6e0004 + ldr r1, [r0] + mov r1, r1, lsr #10 + tst r1, #0x1 + bne cbrdll1_scan_set_2400 + cmp r3, r5 + subge r3, r3, r5 + mov r2, #0x0 + tst r3, #0x08 + beq cbrdll1_scan_set_2300_2 @ if !(dll & 8) +cbrdll1_scan_set_2300_1: @ if (dll & 8) + mov r1, #0x0 + tst r3, #0x08 + addeq r1, r1, #0x01 + cmp r2, #0x05 + addge r1, r1, #0x01 + cmp r1, #0x02 + beq cbrdll1_scan_set + add r2, r2, #0x01 + add r3, r3, #0x01 + cmp r3, r5 + subge r3, r3, r5 + b cbrdll1_scan_set_2300_1 + +cbrdll1_scan_set_2300_2: + and r1, r3, #0x07 + cmp r1, #0x07 + beq cbrdll1_scan_set + cmp r2, #0x05 + bge cbrdll1_scan_set + add r2, r2, #0x01 + add r3, r3, #0x01 + cmp r3, r5 + subge r3, r3, r5 + b cbrdll1_scan_set_2300_2 + +cbrdll1_scan_set_2400: + add r3, r3, #0x05 @ dll1.1 = dll1.0 + (MADJ >> 2) + 5 + cmp r3, r5 + subge r3, r3, r5 + +cbrdll1_scan_set: + orr r1, r6, r3, lsl #8 + ldr r0, =0x1e6e0068 + str r1, [r0] + + ldr r0, =0x1e6e0120 + ldr r1, [r0] + cmp r1, #0x0 + beq MCLK2X_Phase_CBR_Done_DDR3 + cmp r1, #0x1 + beq MCLK2X_Phase_CBR_Done_DDR2 + b CBRDLL1_2400_Call + +.LTORG + +/****************************************************************************** + Calibration Code Start + SRAM buffer definition + 0x1E720000 : Pass 1, DLLI MIN value range + 0x1E720008 : DQS0 DLL valid range, 2nd time CBR + 0x1E72000C : DQS1 DLL valid range, 2nd time CBR + 0x1E720010 : DQ0 DLL valid range, Pass 1 + 0x1E720014 : DQ1 DLL valid range, Pass 1 + .... + 0x1E720048 : DQ14 DLL valid range, Pass 1 + 0x1E72004C : DQ15 DLL valid range, Pass 1 + 0x1E720090 : DLL1 SAdj record + 0x1E720094 : DQL Pass1 finetune result + 0x1E720098 : DQH Pass1 finetune result + 0x1E72009C : DRAM initial time, (us) + 0x1E7200A0 : CBR3 retry counter + 0x1E7200A4 : DRAM initial time, (us) + 0x1E7200A8 : Released date + 0x1E7200AC : Released SDK version + 0x1E7200B0 : DQS input mask window for MCR18[4] = 0 + 0x1E7200B4 : DQS input mask window for MCR18[4] = 1 + 0x1E720100 : DQIDLY=00, DLL valid range + 0x1E720104 : DQIDLY=01, DLL valid range + .... + 0x1E720178 : DQIDLY=30, DLL valid range + 0x1E72017C : DQIDLY=31, DLL valid range + 0x1E720180 : DQSI-MCLK2X P-phase pass record DLL2= 0-31 + 0x1E720184 : DQSI-MCLK2X P-phase pass record DLL2=32-63 + 0x1E720188 : DQSI-MCLK2X N-phase pass record DLL2= 0-31 + 0x1E72018C : DQSI-MCLK2X N-phase pass record DLL2=32-63 + ******************************************************************************/ +Calibration_Start_pre: @ Toggle DQSI mask delay + ldr r0, =0x1e6e0018 + ldr r1, [r0] + eor r1, r1, #0x10 + str r1, [r0] + +Calibration_Start: +/* Init SRAM buffer */ + ldr r1, =0x000000ff + ldr r0, =0x1e720000 + ldr r2, =0x1e720100 +init_sram_start: + str r1, [r0] + add r0, r0, #4 + cmp r0, r2 + blt init_sram_start + + ldr r1, =0x00ff00ff + ldr r0, =0x1e720100 + ldr r2, =0x1e720180 +init_sram_start2: + str r1, [r0] + add r0, r0, #4 + cmp r0, r2 + blt init_sram_start2 + + ldr r1, =0x00000000 + ldr r0, =0x1e720180 + ldr r2, =0x1e720200 +init_sram_start3: + str r1, [r0] + add r0, r0, #4 + cmp r0, r2 + blt init_sram_start3 + + ldr r0, =0x1e6e0068 @ save the DLL1 SAdj initial value + ldr r1, [r0] + ldr r0, =0x1e720090 + str r1, [r0] + +/* Start + r0 = free + r1 = free + r2 = free + r3 = free + r4 = record the return pc value, do not use + r5 = pattern table index + r6 = pass count + r7 = dram DLL2 parameter index (0x1e6e0068), max is 0x4C +*/ +/****************************************************************************** + Fine DQI delay and DQSI-MCLK phase + r8 = DQIDLY count + r9 = DQSI-MCLK2X phase count + r10 = pattern fail retry counter, initialize to 2 (fail 2 times) + r11 = passcnt accumulator for each DQIDLY + *****************************************************************************/ +CBR0_START: +/* Debug - UART console message */ + ldr r0, =0x1e784000 + mov r1, #0x43 @ 'C' + str r1, [r0] + mov r1, #0x42 @ 'B' + str r1, [r0] + mov r1, #0x52 @ 'R' + str r1, [r0] + mov r1, #0x30 @ '0' + str r1, [r0] + mov r1, #0x2D @ '-' + str r1, [r0] +/* Debug - UART console message */ + + ldr r0, =0x1e6e0018 + ldr r1, [r0] + bic r1, r1, #0xFF000000 + bic r1, r1, #0x00FF0000 + str r1, [r0] + + ldr r0, =0x1e6e0074 @ set the testing DRAM size = 1KB + ldr r1, =0x000003FF + str r1, [r0] + + mov r8, #0x00 @ init DQIDLY + mov r9, #0x00 @ init DQSI-MCLK2X phase + mov r11, #0x01 @ init passcnt accumulator + +cbr0_next_dqidly: + cmp r9, #0x00 + bne cbr0_next_dqsiphase + cmp r11, #0x00 + addeq r8, r8, #0x01 @ jump 1 stage if no pass at previous stage + mov r11, #0x00 + add r8, r8, #0x01 + cmp r8, #0x1F @ max DQIDLY = 31 + bgt CBR0_END + +/* Debug - UART console message */ + ldr r0, =0x1e784000 + and r1, r8, #0x07 + add r1, r1, #0x30 @ '0-7' + str r1, [r0] +/* Debug - UART console message */ + + ldr r0, =0x1e6e0018 + ldr r1, [r0] + bic r1, r1, #0x00FF0000 + orr r1, r1, r8, lsl #16 + str r1, [r0] + mov r9, #0x01 @ '1':p_phase, '0':n_phase + + /* Delay about 3us */ @ wait DQIDLY load + ldr r2, =0x00000003 @ Set Timer4 Reload = 3 us + init_delay_timer +delay_4: + check_delay_timer + bne delay_4 + clear_delay_timer + /* end delay 3us */ + + b cbr0_dll2_scan_start + +cbr0_next_dqsiphase: + ldr r0, =0x1e6e0018 + ldr r1, [r0] + orr r1, r1, r9, lsl #23 @ set DQSI-MCLK2X phase + str r1, [r0] + mov r9, #0x00 + +cbr0_dll2_scan_start: + mov r6, #0x00 @ init pass count + mov r7, #0x00 @ init DLL2 parameter index + +/**************************** + DLL2 delay margin test loop + ***************************/ +cbr0_next_dll2_parameter: + ldr r0, =0x1e6e0068 @ load DLL2 parameter + ldr r1, [r0] + bic r1, r1, #0x00FF0000 + bic r1, r1, #0xFF000000 + orr r1, r1, r7, lsl #16 + str r1, [r0] + ldr r2, =0x40404040 @ DLL2 max is 0x40404040 + cmp r7, r2 + bge cbr0_next_dqidly + ldr r2, =0x01010101 + add r7, r7, r2 + +/* CBRScan3() start */ + adrl r5, PATTERN_TABLE @ init pattern table index +/**************************** + Test pattern iteration loop + ***************************/ +cbr0_next_test_pattern: + mov r10, #2 @ set the retry loop = 2 of each pattern + ldr r1, [r5] @ load test pattern + ldr r0, =0x1e6e007c + str r1, [r0] + cmp r1, #0x00 @ the last data in pattern is 0x00 + bne cbr0_test_burst + + and r3, r7, #0xFF + sub r3, r3, #0x01 @ we add 1 after loop check so we need to decrease 1 + cmp r3, #0x00 + beq cbr0_next_dqidly @ pass at dlli = 0, invalid + add r6, r6, #0x01 @ increment pass count + add r11, r11, #0x01 @ increment pass count + + ldr r0, =0x1e720180 @ record DLL2 pass window + cmp r9, #0x00 @ DQSI-MCLK2X phase check + addeq r0, r0, #0x08 + cmp r3, #32 + addge r0, r0, #0x4 + and r1, r3, #0x1F + mov r2, #0x1 + mov r2, r2, lsl r1 + ldr r1, [r0] + orr r1, r1, r2 + str r1, [r0] + + ldr r0, =0x1e720100 @ record DLL2 min:max value for each DQIDLY + add r0, r0, r8, lsl #2 + cmp r9, #0x00 @ DQSI-MCLK2X phase check + beq cbr0_test_pass_dqsin + record_dll2_pass_range + b cbr0_next_dll2_parameter + +cbr0_test_pass_dqsin: + record_dll2_pass_range_h + b cbr0_next_dll2_parameter + +cbr0_test_pattern_fail: + cmp r6, #5 @ passcnt >= 5 + bge cbr0_next_dqidly + ldr r0, =0x1e720100 @ reset DLL2 min:max value + add r0, r0, r8, lsl #2 + ldr r1, [r0] + ldr r2, =0xFFFF0000 + ldr r3, =0x000000FF + cmp r9, #0x00 + moveq r2, r2, lsr #16 + moveq r3, r3, lsl #16 + and r1, r1, r2 + orr r1, r1, r3 + str r1, [r0] + b cbr0_next_dll2_parameter @ CBRScan3() end and test result fail, go to next step + +/**************************** + Test fail retry loop + ***************************/ +cbr0_pattern_fail_retry: + +/* CBRTest3() start */ +cbr0_test_burst: + ldr r0, =0x1e6e0070 + ldr r1, =0x00000000 + str r1, [r0] + ldr r1, =0x000000C1 + str r1, [r0] + ldr r3, =0x3000 +cbr0_wait_engine_idle_0: + ldr r2, [r0] + tst r2, r3 @ D[12] = idle bit + beq cbr0_wait_engine_idle_0 + + ldr r2, [r0] @ read fail bit status + mov r1, #0x0 + str r1, [r0] + mov r2, r2, lsr #13 @ D[13] = fail bit + cmp r2, #0x00 + bne cbr0_test_fail + +cbr0_test_single: + ldr r0, =0x1e6e0070 + ldr r1, =0x00000000 + str r1, [r0] + ldr r1, =0x00000085 + str r1, [r0] + ldr r3, =0x3000 +cbr0_wait_engine_idle_1: + ldr r2, [r0] + tst r2, r3 @ D[12] = idle bit + beq cbr0_wait_engine_idle_1 + + ldr r2, [r0] @ read fail bit status + mov r1, #0x0 + str r1, [r0] + mov r2, r2, lsr #13 @ D[13] = fail bit + cmp r2, #0x00 + beq cbr0_test_pass + +/* CBRTest3() end */ + +cbr0_test_fail: + subs r10, r10, #1 + bne cbr0_pattern_fail_retry + b cbr0_test_pattern_fail @ CBRScan3() return(0) + +cbr0_test_pass: + add r5, r5, #0x04 @ increase the test pattern index + b cbr0_next_test_pattern + +CBR0_END: + mov r5, #0x0 @ init DQIDLY search count + mov r6, #0x0 @ init max_margin:g_margin + mov r8, #0x0 @ init g_side + mov r7, #0x0 @ init maximum margin DQIDLY,DQSI-MCLK2X phase +cbr0_search_dll_margin_s: + ldr r0, =0x1e720100 + add r0, r0, r5, lsl #2 + ldr r1, [r0] + and r2, r1, #0xFF @ get dllmin_p + mov r1, r1, lsr #8 + and r3, r1, #0xFF @ get dllmax_p + subs r2, r3, r2 @ get margin-P + movmi r2, #0x0 + mov r1, r1, lsr #8 + and r3, r1, #0xFF @ get dllmin_n + mov r1, r1, lsr #8 + and r1, r1, #0xFF @ get dllmax_n + subs r3, r1, r3 @ get margin-N + movmi r3, #0x0 + add r1, r2, r3 + cmp r1, #0x0 + beq cbr0_search_dll_margin_e @ if margin-P = 0 && margin-N = 0 + + ldr r9, [r0] + ldr r0, =0x1e720180 + cmp r2, r3 + orrlt r5, r5, #0x80 @ margin-N > margin-P + addlt r0, r0, #0x08 + movlt r9, r9, lsr #16 + movge r3, r2 @ max(margin-P/N) + add r2, r3, #0x2 @ define +/- 2 steps of variation + mov r1, r6, lsr #16 + cmp r2, r1 + blt cbr0_search_dll_margin_e @ if max(margin-P/N) + 2 < max_margin + + and r1, r9, #0xFF @ r1 = dlli counter + cmp r1, #32 + ldrge r2, [r0, #0x4] @ load pass window + ldrlt r2, [r0] + and r1, r1, #0x1F + mov r10, #0x1 @ init test bit mask + mov r10, r10, lsl r1 + and r1, r9, #0xFF +cbr0_search_dllmin_margin_s: + tst r2, r10 + beq cbr0_search_dllmin_margin_e + mov r10, r10, lsr #1 + cmp r1, #32 + ldreq r2, [r0] + ldreq r10, =0x80000000 + subs r1, r1, #0x1 + bne cbr0_search_dllmin_margin_s + +cbr0_search_dllmin_margin_e: + and r2, r9, #0xFF + sub r11, r2, r1 @ get dllmin side margin + + mov r9, r9, lsr #8 + and r1, r9, #0xFF @ r1 = dlli counter + cmp r1, #32 + ldrge r2, [r0, #0x4] @ load pass window + ldrlt r2, [r0] + and r1, r1, #0x1F + mov r10, #0x1 @ init test bit mask + mov r10, r10, lsl r1 + and r1, r9, #0xFF +cbr0_search_dllmax_margin_s: + tst r2, r10 + beq cbr0_search_dllmax_margin_e + mov r10, r10, lsl #1 + cmp r1, #31 + ldreq r2, [r0, #0x4] + ldreq r10, =0x00000001 + add r1, r1, #0x1 + cmp r1, #64 + bne cbr0_search_dllmax_margin_s + +cbr0_search_dllmax_margin_e: + and r2, r9, #0xFF + sub r1, r1, r2 @ get dllmax side margin + cmp r1, r11 + movlt r11, r1 @ get side_margin + +cbr0_check_dll_margin: @ if max(margin-P/N) > g_margin && side_margin >= g_side && dqidly <= 20 + cmp r5, #20 + bgt cbr0_check_dll_margin2 + and r1, r6, #0xFF + cmp r3, r1 + ble cbr0_check_dll_margin3 + cmp r11, r8 + bge cbr0_set_dll_margin + +cbr0_check_dll_margin2: @ if max(margin-P/N) > g_margin+1 && side_margin >= g_side) + and r1, r6, #0xFF + add r2, r1, #0x1 + cmp r3, r2 + ble cbr0_check_dll_margin3 + cmp r11, r8 + bge cbr0_set_dll_margin + +cbr0_check_dll_margin3: @ if side_margin > g_side && g_side < 8 + cmp r8, #8 + bge cbr0_search_dll_margin_e + cmp r11, r8 + ble cbr0_search_dll_margin_e + +cbr0_set_dll_margin: + mov r1, r6, lsr #16 + cmp r3, r1 + bicgt r6, r6, #0x00FF0000 + orrgt r6, r6, r3, lsl #16 + bic r6, r6, #0x000000FF + orr r6, r6, r3 + mov r7, r5 + mov r8, r11 + +cbr0_search_dll_margin_e: + and r5, r5, #0x7F + add r5, r5, #0x01 + cmp r5, #0x20 @ last DQIDLY + blt cbr0_search_dll_margin_s + + ldr r0, =0x1e6e0018 + ldr r1, [r0] + bic r1, r1, #0x00FF0000 + orr r1, r1, r7, lsl #16 + str r1, [r0] + + ldr r0, =0x1e6e0068 + ldr r1, [r0] + bic r1, r1, #0x00FF0000 + bic r1, r1, #0xFF000000 + str r1, [r0] + + /* Delay about 5us */ + ldr r2, =0x00000005 @ Set Timer5 Reload = 5 us + init_delay_timer +delay_5: + check_delay_timer + bne delay_5 + clear_delay_timer + /* end delay 5us */ + + ldr r0, =0x1e6e000c @ Set refresh cycle + ldr r1, =0x00005C01 + str r1, [r0] + +/****************************************************************************** + Fine tune per bit DQ input delay -- Pass 1, left edge align + r8 = free + r9 = DQ fail bit accumulator + r10 = pattern fail counter, initialize to 5 (fail 5 times) + r11 = free + *****************************************************************************/ +CBR1_START: +/* Debug - UART console message */ + ldr r0, =0x1e784000 + mov r1, #0x0D @ '\r' + str r1, [r0] + mov r1, #0x0A @ '\n' + str r1, [r0] + mov r1, #0x43 @ 'C' + str r1, [r0] + mov r1, #0x42 @ 'B' + str r1, [r0] + mov r1, #0x52 @ 'R' + str r1, [r0] + mov r1, #0x31 @ '1' + str r1, [r0] +/* Debug - UART console message */ + + mov r6, #0x00 @ init pass count + mov r7, #0x00 @ init DLL2 parameter index + +/**************************** + DLL2 delay margin test loop + ***************************/ +cbr1_next_dll2_parameter: + ldr r0, =0x1e6e0068 @ load DLL2 parameter + ldr r1, [r0] + bic r1, r1, #0x00FF0000 + bic r1, r1, #0xFF000000 + orr r1, r1, r7, lsl #16 + str r1, [r0] + ldr r2, =0x40404040 @ parameter's max is to 0x40404040 + cmp r7, r2 + bge CBR1_END + ldr r2, =0x01010101 + add r7, r7, r2 + + ldr r0, =0x1e6e0074 @ set the testing DRAM size = 4KB + ldr r1, =0x00000FFF + str r1, [r0] + +/* CBRScan2() start */ + ldr r9, =0xFFFF @ init test status + adrl r5, PATTERN_TABLE @ init pattern table index +/**************************** + Test pattern iteration loop + ***************************/ +cbr1_next_test_pattern: + mov r10, #5 @ set the retry loop of each pattern + ldr r1, [r5] @ load test pattern + ldr r0, =0x1e6e007c + str r1, [r0] + cmp r1, #0x00 @ the last data in pattern is 0x00 + bne cbr1_test_single + +cbr1_test_pattern_end: + cmp r9, #0x00 + bne cbr1_test_pass_dqi + cmp r6, #10 + bge CBR1_END + b cbr1_next_dll2_parameter @ CBRScan2() end and test result fail, go to next step + +cbr1_test_pass_dqi: + and r3, r7, #0xFF + sub r3, r3, #0x01 @ we add 1 after loop check so we need to decrease 1 + add r6, r6, #0x01 @ increment pass count + ldr r0, =0x1e720010 + mov r8, #0x01 +cbr1_test_pass_dqi_loop_s: + tst r9, r8 + beq cbr1_test_pass_dqi_loop_e + record_dll2_pass_range + +cbr1_test_pass_dqi_loop_e: + add r0, r0, #0x04 + mov r8, r8, lsl #1 + ldr r1, =0xFFFF + tst r8, r1 + bne cbr1_test_pass_dqi_loop_s + b cbr1_next_dll2_parameter + +/**************************** + Test fail retry loop + ***************************/ +cbr1_pattern_fail_retry: + +/* CBRTest2() start */ +cbr1_test_single: + ldr r0, =0x1e6e0070 + ldr r1, =0x00000000 + str r1, [r0] + ldr r1, =0x00000005 + str r1, [r0] + ldr r3, =0x1000 + ldr r1, =0x1000 +cbr1_wait_engine_idle_0: + subs r1, r1, #1 + beq cbr1_test_single_end + ldr r2, [r0] + tst r2, r3 @ D[12] = idle bit + beq cbr1_wait_engine_idle_0 + +cbr1_test_single_end: + ldr r0, =0x1e6e0078 @ read fail bit status + ldr r11, [r0] + orr r11, r11, r11, lsr #16 + bic r11, r11, #0xFF000000 + bic r11, r11, #0x00FF0000 + + ldr r1, =0xFFFF + cmp r11, r1 + beq cbr1_test_fail + +cbr1_test_burst: + ldr r0, =0x1e6e0070 + ldr r2, =0x00000000 + str r2, [r0] + ldr r2, =0x00000041 + str r2, [r0] + ldr r3, =0x1000 + ldr r1, =0x1000 +cbr1_wait_engine_idle_1: + subs r1, r1, #1 + beq cbr1_test_burst_end + ldr r2, [r0] + tst r2, r3 @ D[12] = idle bit + beq cbr1_wait_engine_idle_1 + +cbr1_test_burst_end: + ldr r0, =0x1e6e0078 @ read fail bit status + ldr r2, [r0] + orr r2, r2, r2, lsr #16 + bic r2, r2, #0xFF000000 + bic r2, r2, #0x00FF0000 + orr r11, r11, r2 + + ldr r2, =0xFFFF + cmp r11, r2 + bne cbr1_test_pass +/* CBRTest2() end */ + +cbr1_test_fail: + subs r10, r10, #1 + bne cbr1_pattern_fail_retry + mov r9, #0x00 + b cbr1_test_pattern_end @ CBRScan2() return(0) + +cbr1_test_pass: + ldr r1, =0xFFFF @ record the pass bit + eor r11, r11, r1 + and r9, r9, r11 @ DQ pass bit + cmp r9, #0x00 + beq cbr1_test_pattern_end @ CBRScan2() return(0) + + add r5, r5, #0x04 @ increase the test pattern index + b cbr1_next_test_pattern + +CBR1_END: + mov r5, #0x0 @ init DQ DLL_min sum + mov r6, #0x0 @ init DQ DLL_min valid count + ldr r0, =0x1e72000c + ldr r3, =0x1e720050 +cbr1_search_dllmin_s: + add r0, r0, #0x04 + cmp r0, r3 + beq cbr1_search_dllmin_e + ldr r1, [r0] + mov r2, r1, lsr #8 + and r2, r2, #0xFF @ get dllmax + and r1, r1, #0xFF @ get dllmin + subs r2, r2, r1 @ dllmax - dllmin + bmi cbr1_search_dllmin_s @ no valid margin found, bypass fine tune + cmp r2, #10 @ (dllmax - dllmin) < 10 + blt cbr1_search_dllmin_s @ no enough margin found, bypass fine tune + add r5, r5, r1 + add r6, r6, #1 + b cbr1_search_dllmin_s + +cbr1_search_dllmin_e: + cmp r6, #16 + bne Calibration_Start_pre @ not all bits valid, retry again + + mov r5, r5, lsr #4 + ldr r0, =0x1e720000 + str r5, [r0] + + mov r6, #0x00 @ init DQL CBR value + ldr r0, =0x1e720030 + ldr r7, =0x1e72000c +cbr1_set_result_dql: + sub r0, r0, #4 + cmp r0, r7 + beq cbr1_set_result_next + mov r6, r6, lsl #3 + ldr r1, [r0] + mov r2, r1, lsr #8 + and r2, r2, #0xFF @ get dllmax + and r1, r1, #0xFF @ get dllmin + mov r3, r1 @ dll = dllmin + cmp r5, r3 + blt cbr1_set_result_dql_neg + sub r1, r5, r3 + mov r2, #19 + mul r1, r2, r1 + mov r1, r1, lsr #5 @ dqi_tune = ((gold_dll - dll) * 19) >> 5 + cmp r1, #2 @ dqi_tune max = 2 + movgt r1, #2 + orr r6, r6, r1 + b cbr1_set_result_dql + +cbr1_set_result_dql_neg: + sub r1, r3, r5 + mov r2, #19 + mul r1, r2, r1 + mov r1, r1, lsr #5 @ dqi_tune = ((gold_dll - dll) * 19) >> 5 + cmp r1, #2 @ dqi_tune max = -2 + movgt r1, #2 + mov r2, #8 + sub r1, r2, r1 + and r1, r1, #7 + orr r6, r6, r1 + b cbr1_set_result_dql + +cbr1_set_result_next: + ldr r0, =0x1e6e0080 @ save DQL fine tune result + str r6, [r0] + ldr r0, =0x1e720094 + str r6, [r0] + + mov r6, #0x00 @ init DQH CBR value + ldr r0, =0x1e720050 + ldr r7, =0x1e72002c +cbr1_set_result_dqh: + sub r0, r0, #4 + cmp r0, r7 + beq cbr1_set_result_end + mov r6, r6, lsl #3 + ldr r1, [r0] + mov r2, r1, lsr #8 + and r2, r2, #0xFF @ get dllmax + and r1, r1, #0xFF @ get dllmin + mov r3, r1 @ dll = dllmin + cmp r5, r3 + blt cbr1_set_result_dqh_neg + sub r1, r5, r3 + mov r2, #19 + mul r1, r2, r1 + mov r1, r1, lsr #5 @ dqi_tune = ((gold_dll - dll) * 19) >> 5 + cmp r1, #3 @ dqi_tune max = 2 + movgt r1, #3 + subs r1, r1, #1 + movmi r1, #7 + orr r6, r6, r1 + b cbr1_set_result_dqh + +cbr1_set_result_dqh_neg: + sub r1, r3, r5 + mov r2, #19 + mul r1, r2, r1 + mov r1, r1, lsr #5 @ dqi_tune = ((gold_dll - dll) * 19) >> 5 + add r1, r1, #1 + cmp r1, #2 @ dqi_tune max = -2 + movgt r1, #2 + mov r2, #8 + sub r1, r2, r1 + and r1, r1, #7 + orr r6, r6, r1 + b cbr1_set_result_dqh + +cbr1_set_result_end: + ldr r0, =0x1e6e0084 @ save DQH fine tune result + str r6, [r0] + ldr r0, =0x1e720098 + str r6, [r0] + +/****************************************************************************** + Search the DLL2 detail margin + *****************************************************************************/ + ldr r0, =0x1e7200a0 + mov r1, #0 + str r1, [r0] + +CBR3_START: +/* Debug - UART console message */ + ldr r0, =0x1e784000 + mov r1, #0x33 @ '3' + str r1, [r0] +/* Debug - UART console message */ + + mov r6, #0x00 @ init pass count + mov r7, #0x00 @ init DLL2 parameter index + ldr r1, =0x000000ff + ldr r0, =0x1e720008 @ init DQL dllmax,dllmin + str r1, [r0] + ldr r0, =0x1e72000c @ init DQH dllmax,dllmin + str r1, [r0] + + ldr r0, =0x1e7200a0 @ CBR3 iteration counter + ldr r1, [r0] + add r1, r1, #1 + str r1, [r0] + +/**************************** + DLL2 delay margin test loop + ***************************/ +cbr3_next_dll2_parameter: + ldr r0, =0x1e6e0068 @ load DLL2 parameter + ldr r1, [r0] + bic r1, r1, #0x00FF0000 + bic r1, r1, #0xFF000000 + orr r1, r1, r7, lsl #16 + str r1, [r0] + ldr r2, =0x40404040 @ parameter's max is to 0x40404040 + cmp r7, r2 + bge CBR3_END + ldr r2, =0x01010101 + add r7, r7, r2 + + ldr r0, =0x1e6e0074 @ set the testing DRAM size = 64KB + ldr r1, =0x0000FFFF + str r1, [r0] + +/* CBRScan() start */ + mov r9, #0x03 @ init test status + adrl r5, PATTERN_TABLE @ init pattern table index +/**************************** + Test pattern iteration loop + ***************************/ +cbr3_next_test_pattern: + mov r10, #5 @ set the retry loop of each pattern + ldr r1, [r5] @ load test pattern + ldr r0, =0x1e6e007c + str r1, [r0] + cmp r1, #0x00 @ the last data in pattern is 0x00 + bne cbr3_test_single + +cbr3_test_pattern_end: + cmp r9, #0x00 + bne cbr3_test_pass_dql + cmp r6, #10 + bge CBR3_END + b cbr3_next_dll2_parameter @ CBRScan() end and test result fail, go to next step + +cbr3_test_pass_dql: + and r3, r7, #0xFF + sub r3, r3, #0x01 @ we add one after loop check so we need to decrease 1 + add r6, r6, #0x01 @ increment pass count + tst r9, #0x01 + beq cbr3_test_pass_dqh + + ldr r0, =0x1E720008 + record_dll2_pass_range + +cbr3_test_pass_dqh: + tst r9, #0x02 + beq cbr3_next_dll2_parameter + ldr r0, =0x1E72000c + record_dll2_pass_range + b cbr3_next_dll2_parameter + +/**************************** + Test fail retry loop + ***************************/ +cbr3_pattern_fail_retry: + +/* CBRTest() start */ +cbr3_test_single: + ldr r0, =0x1e6e0070 + ldr r1, =0x00000000 + str r1, [r0] + ldr r1, =0x00000005 + str r1, [r0] + ldr r3, =0x1000 + ldr r8, =0x10000 +cbr3_wait_engine_idle_0: + subs r8, r8, #1 + beq cbr3_test_single_end + ldr r2, [r0] + tst r2, r3 @ D[12] = idle bit + beq cbr3_wait_engine_idle_0 + +cbr3_test_single_end: + ldr r0, =0x1e6e0078 @ read fail bit status + ldr r11, [r0] + orr r11, r11, r11, lsr #16 + bic r11, r11, #0xFF000000 + bic r11, r11, #0x00FF0000 + + ldr r1, =0xFF + tst r11, r1 + beq cbr3_test_burst + tst r11, r1, lsl #8 + bne cbr3_test_fail + +cbr3_test_burst: + mov r1, #0x00 @ initialize loop index, r1 is loop's index +cbr3_test_burst_loop: + ldr r0, =0x1e6e0070 + ldr r2, =0x00000000 + str r2, [r0] + mov r2, r1, lsl #3 + orr r2, r2, #0x41 @ test command = 0x41 | (datagen << 3) + str r2, [r0] + ldr r3, =0x1000 + ldr r8, =0x10000 +cbr3_wait_engine_idle_1: + subs r8, r8, #1 + beq cbr3_test_burst_end + ldr r2, [r0] + tst r2, r3 @ D[12] = idle bit + beq cbr3_wait_engine_idle_1 + +cbr3_test_burst_end: + ldr r0, =0x1e6e0078 @ read fail bit status + ldr r2, [r0] + orr r2, r2, r2, lsr #16 + bic r2, r2, #0xFF000000 + bic r2, r2, #0x00FF0000 + orr r11, r11, r2 + + ldr r2, =0xFF + tst r11, r2 + beq cbr3_next_test_burst_mode + tst r11, r2, lsl #8 + beq cbr3_next_test_burst_mode +/* CBRTest() end */ + +cbr3_test_fail: + subs r10, r10, #1 + bne cbr3_pattern_fail_retry + mov r9, #0x00 + b cbr3_test_pattern_end @ CBRScan() return(0) + +cbr3_next_test_burst_mode: + add r1, r1, #1 @ increase the test mode index + cmp r1, #0x08 @ there are 8 modes + bne cbr3_test_burst_loop + + ldr r1, =0xFF @ record the pass byte + tst r11, r1 + andne r9, r9, #0x02 @ DQL fail + tst r11, r1, lsl #8 + andne r9, r9, #0x01 @ DQH fail + cmp r9, #0x00 + beq cbr3_test_pattern_end @ CBRScan() return(0) + + add r5, r5, #0x04 @ increase the test pattern index + b cbr3_next_test_pattern + +CBR3_END: + ldr r0, =0x1e72000c @ check DQH margin + ldr r1, [r0] + mov r2, r1, lsr #8 + and r2, r2, #0xFF @ get dllmax + and r1, r1, #0xFF @ get dllmin + subs r5, r2, r1 @ dllmax - dllmin + bmi CBR3_START @ no valid margin found, retry again + cmp r5, #10 @ (dllmax - dllmin) < 10 + blt CBR3_START @ no enough margin found, retry again + add r2, r1, r2 @ (dllmin[1] + dllmax[1] + 1) >> 1 + add r2, r2, #0x01 + mov r1, r2, lsr #1 + mov r3, r1, lsl #8 + ldr r1, [r0] @ store the dll search result + bic r1, r1, #0xFF000000 + bic r1, r1, #0x00FF0000 + orr r1, r1, r3, lsl #8 + str r1, [r0] + + ldr r0, =0x1e720008 @ check DQL margin + ldr r1, [r0] + mov r2, r1, lsr #8 + and r2, r2, #0xFF @ get dllmax + and r1, r1, #0xFF @ get dllmin + subs r5, r2, r1 @ dllmax - dllmin + bmi CBR3_START @ no valid margin found, retry again + cmp r5, #10 @ (dllmax - dllmin) < 10 + blt CBR3_START @ no enough margin found, retry again + add r2, r1, r2 @ (dllmin[0] + dllmax[0] + 1) >> 1 + add r2, r2, #0x01 + mov r1, r2, lsr #1 + ldr r2, [r0] @ store the dll search result + bic r2, r2, #0xFF000000 + bic r2, r2, #0x00FF0000 + orr r2, r2, r1, lsl #16 + str r2, [r0] + orr r3, r3, r1 + + ldr r0, =0x1e6e0068 @ save the result dll value + ldr r1, [r0] + bic r1, r1, #0xFF000000 + bic r1, r1, #0x00FF0000 + orr r1, r1, r3, lsl #16 + str r1, [r0] + b CBR4_START + +.LTORG + +/****************************************************************************** + Search the DQS input mask margin + *****************************************************************************/ +CBR4_START: +/* Debug - UART console message */ + ldr r0, =0x1e784000 + mov r1, #0x34 @ '4' + str r1, [r0] +/* Debug - UART console message */ + + ldr r0, =0x1e6e0074 @ set the testing DRAM size = 4KB + ldr r1, =0x00000FFF + str r1, [r0] + + mov r8, #0x00 @ init MCR18[4] + ldr r1, =0x000000ff + ldr r0, =0x1e7200b0 @ init MCR18[4]=0 max,min + str r1, [r0] + ldr r0, =0x1e7200b4 @ init MCR18[4]=1 max,min + str r1, [r0] + + ldr r0, =0x1e6e0018 + ldr r1, [r0] + bic r1, r1, #0x0000001F + str r1, [r0] + + b cbr4_scan_start + +cbr4_next_maskdly: + add r8, r8, #0x01 + and r2, r8, #0x01 + ldr r0, =0x1e6e0018 + ldr r1, [r0] + bic r1, r1, #0x0000001F + orr r1, r1, r2, lsl #4 + str r1, [r0] + cmp r8, #0x02 + bge CBR4_END + +cbr4_scan_start: + mov r6, #0x00 @ init pass count + mov r7, #0x00 @ init mask delay + +/**************************** + DQS Mask delay margin test loop + ***************************/ +cbr4_next_parameter: + cmp r7, #0x10 @ max delay = 0xF + bge cbr4_next_maskdly + ldr r0, =0x1e6e0018 @ load MCR18 parameter + ldr r1, [r0] + bic r1, r1, #0x0000000F + orr r1, r1, r7 + str r1, [r0] + add r7, r7, #0x01 + +/* CBRScan3() start */ + adrl r5, PATTERN_TABLE @ init pattern table index +/**************************** + Test pattern iteration loop + ***************************/ +cbr4_next_test_pattern: + mov r10, #2 @ set the retry loop = 2 of each pattern + ldr r1, [r5] @ load test pattern + ldr r0, =0x1e6e007c + str r1, [r0] + cmp r1, #0x00 @ the last data in pattern is 0x00 + bne cbr4_test_burst + + and r3, r7, #0xFF + sub r3, r3, #0x01 @ we add 1 after loop check so we need to decrease 1 + add r6, r6, #0x01 @ increment pass count + + ldr r0, =0x1e7200b0 @ record pass window + add r0, r0, r8, lsl #2 + record_dll2_pass_range + mov r2, #0x01 + add r1, r1, r2, lsl #16 + str r1, [r0] + b cbr4_next_parameter + +cbr4_test_pattern_fail: + cmp r6, #5 @ passcnt >= 5 + bge cbr4_next_maskdly + b cbr4_next_parameter + +/**************************** + Test fail retry loop + ***************************/ +cbr4_pattern_fail_retry: + +/* CBRTest3() start */ +cbr4_test_burst: + ldr r0, =0x1e6e0070 + ldr r1, =0x00000000 + str r1, [r0] + ldr r1, =0x000000C1 + str r1, [r0] + ldr r3, =0x3000 +cbr4_wait_engine_idle_0: + ldr r2, [r0] + tst r2, r3 @ D[12] = idle bit + beq cbr4_wait_engine_idle_0 + + ldr r2, [r0] @ read fail bit status + mov r1, #0x0 + str r1, [r0] + mov r2, r2, lsr #13 @ D[13] = fail bit + cmp r2, #0x00 + bne cbr4_test_fail + +cbr4_test_single: + ldr r0, =0x1e6e0070 + ldr r1, =0x00000000 + str r1, [r0] + ldr r1, =0x00000085 + str r1, [r0] + ldr r3, =0x3000 +cbr4_wait_engine_idle_1: + ldr r2, [r0] + tst r2, r3 @ D[12] = idle bit + beq cbr4_wait_engine_idle_1 + + ldr r2, [r0] @ read fail bit status + mov r1, #0x0 + str r1, [r0] + mov r2, r2, lsr #13 @ D[13] = fail bit + cmp r2, #0x00 + beq cbr4_test_pass + +/* CBRTest3() end */ + +cbr4_test_fail: + subs r10, r10, #1 + bne cbr4_pattern_fail_retry + b cbr4_test_pattern_fail @ CBRScan3() return(0) + +cbr4_test_pass: + add r5, r5, #0x04 @ increase the test pattern index + b cbr4_next_test_pattern + +CBR4_END: + ldr r0, =0x1e7200b0 @ check mask margin + ldr r1, [r0] + add r0, r0, #0x04 + ldr r2, [r0] + ands r6, r2, #0xFF @ get min of MCR18[4] = 1 + bne cbr4_noset_delay + ands r5, r1, #0xFF @ get min of MCR18[4] = 0 + bne cbr4_set_delay + mov r1, r1, lsr #8 @ get max of MCR18[4] = 0 + and r1, r1, #0xFF + mov r2, r2, lsr #8 @ get max of MCR18[4] = 1 + and r2, r2, #0xFF + sub r1, r1, r5 + sub r2, r2, r6 + cmp r1, r2 + bge cbr4_noset_delay + +cbr4_set_delay: + ldr r0, =0x1e6e0018 + ldr r1, [r0] + orr r1, r1, #0x10 + str r1, [r0] + +cbr4_noset_delay: + ldr r0, =0x1e6e0070 + ldr r1, =0x00000000 + str r1, [r0] + +/****************************************************************************** + CBR Finish + *****************************************************************************/ +/****************************************************************************** + Check DRAM Size + *****************************************************************************/ + ldr r0, =0x1e6e2070 + ldr r1, [r0] + bic r1, r1, #0xFEFFFFFF @ bit[24]=1 => DDR2 + mov r2, r1, lsr #24 + cmp r2, #0x01 + beq check_ddr2_size + + ldr r0, =0x1e6e0004 + ldr r5, [r0] + bic r5, r5, #0x00000003 @ record MCR04 + orr r1, r5, #0x3 + str r1, [r0] @ set to 4Gbit + ldr r6, =0x003F2217 +#if defined(CONFIG_DRAM_336) + ldr r6, =0x00361C13 +#endif + b check_dram_size + +check_ddr2_size: + ldr r0, =0x1e6e0004 + ldr r5, [r0] + bic r5, r5, #0x00000023 @ record MCR04 + orr r1, r5, #0x23 + str r1, [r0] @ set to 4Gbit + ldr r6, =0x3F2B1B16 +#if defined(CONFIG_DRAM_336) + ldr r6, =0x3B231612 +#endif + + ldr r0, =0x40000000 + ldr r1, =0x1817191A + str r1, [r0] + ldr r0, =0x40002000 + ldr r1, =0x73616532 + str r1, [r0] + ldr r0, =0x40000000 + ldr r1, =0x1817191A + ldr r2, [r0] + cmp r1, r2 + bne check_dram_size_end @ == 512Mbit + orr r5, r5, #0x20 @ >= 1Gbit + mov r6, r6, lsr #8 + +check_dram_size: + ldr r0, =0x50100000 + ldr r1, =0x41424344 + str r1, [r0] + ldr r0, =0x48100000 + ldr r1, =0x25262728 + str r1, [r0] + ldr r0, =0x40100000 + ldr r1, =0x191A1B1C + str r1, [r0] + ldr r0, =0x50100000 + ldr r1, =0x41424344 + ldr r2, [r0] + cmp r2, r1 @ == 4Gbit + orreq r5, r5, #0x03 + moveq r6, r6, lsr #16 + beq check_dram_size_end + ldr r0, =0x48100000 + ldr r1, =0x25262728 + ldr r2, [r0] + cmp r2, r1 @ == 2Gbit + orreq r5, r5, #0x02 + moveq r6, r6, lsr #8 + beq check_dram_size_end + orr r5, r5, #0x01 @ == 1Gbit + +check_dram_size_end: + ldr r0, =0x1e6e0004 + str r5, [r0] + ldr r0, =0x1e6e0014 + ldr r1, [r0] + bic r1, r1, #0x000000FF + and r6, r6, #0xFF + orr r1, r1, r6 + str r1, [r0] + + ldr r0, =0x1e6e0120 @ VGA Compatible Mode + ldr r1, =0x000050C0 @ 408 MHz +#if defined(CONFIG_DRAM_336) + ldr r1, =0x00004DC0 +#endif + str r1, [r0] + +/****************************************************************************** + Version Number + *****************************************************************************/ + ldr r0, =0x1e7200a8 + ldr r1, =0x20150209 @ released date + str r1, [r0] + + add r0, r0, #4 + ldr r1, =0x00000061 @ released SDK version + str r1, [r0] + +/****************************************************************************** + Calibration Code End + ******************************************************************************/ + +set_scratch: + /*Set Scratch register Bit 6 after ddr initial finished */ + ldr r0, =0x1e6e2040 + ldr r1, [r0] + orr r1, r1, #0x40 + str r1, [r0] + +/* Debug - UART console message */ + ldr r0, =0x1e784000 + mov r1, #0x44 @ 'D' + str r1, [r0] + mov r1, #0x6F @ 'o' + str r1, [r0] + mov r1, #0x6E @ 'n' + str r1, [r0] + mov r1, #0x65 @ 'e' + str r1, [r0] + mov r1, #0x0D @ '\r' + str r1, [r0] + mov r1, #0x0A @ '\n' + str r1, [r0] +/* Debug - UART console message */ + +/****************************************************************************** + Solve PCIe ASPM issue, only applied to AST2300 series + ******************************************************************************/ + ldr r0, =0x1e6e207c @ Check bounding for AST1150 existence + ldr r1, [r0] + mov r2, r1, lsr #24 + cmp r2, #0x01 + bne platform_exit @ not match AST2300 + bic r1, r1, #0xFFFFFCFF + mov r1, r1, lsr #8 + cmp r1, #0x02 + beq platform_exit @ match AST1050 + + ldr r0, =0x1e6e2004 @ Disable I2C controller reset + ldr r1, [r0] + orr r1, r1, #0x04 + str r1, [r0] + bic r1, r1, #0x04 + str r1, [r0] + + ldr r0, =0x1e78a054 @ Check I2C bus state, if busy then quit + ldr r1, [r0] + mov r1, r1, lsr #17 + and r1, r1, #0x03 + cmp r1, #0x03 + bne platform_exit + + ldr r0, =0x1e78a040 @ Init I2C1 controller + mov r1, #0x01 + orr r1, r1, r1, lsl #16 + str r1, [r0] + + ldr r0, =0x1e78a044 + ldr r1, =0x77776704 + str r1, [r0] + + mov r1, #0x0 + ldr r0, =0x1e78a048 + str r1, [r0] + ldr r0, =0x1e78a04c + str r1, [r0] + + ldr r0, =0x1e78a050 + ldr r1, =0xFFFFFFFF + str r1, [r0] + + ldr r0, =0x1e78a200 @ Set AST1150 I2C password + ldr r1, =0x00A88FA8 + str r1, [r0] + + ldr r0, =0x1e78a05c + ldr r1, =0x00000200 @ Enable buffer mode transfering 3 bytes + str r1, [r0] + + ldr r0, =0x1e78a054 + ldr r1, =0x00000063 @ Fire commmand + str r1, [r0] + + ldr r0, =0x1e78a050 +i2c_wait_cmddone_1: + ldr r1, [r0] + tst r1, #0x38 + beq i2c_wait_cmddone_1 + tst r1, #0x2A @ transmit error + bne platform_exit2 + ldr r1, =0xFFFFFFFF + str r1, [r0] + + ldr r0, =0x1e78a200 @ Disable ASPM capability + ldr r1, =0x04005DA8 + str r1, [r0] + + ldr r0, =0x1e78a204 + ldr r1, =0x00000024 + str r1, [r0] + + ldr r0, =0x1e78a05c + ldr r1, =0x00000200 @ Enable buffer mode transfering 3 bytes + str r1, [r0] + + ldr r0, =0x1e78a054 + ldr r1, =0x00000063 @ Fire commmand + str r1, [r0] + + ldr r0, =0x1e78a050 +i2c_wait_cmddone_2: + ldr r1, [r0] + tst r1, #0x38 + beq i2c_wait_cmddone_2 + tst r1, #0x2A @ transmit error + bne platform_exit2 + ldr r1, =0xFFFFFFFF + str r1, [r0] + +platform_exit2: + ldr r0, =0x1e78a040 @ Disable I2C1 controller + mov r1, #0x00 + str r1, [r0] + + b platform_exit +.LTORG + +platform_exit: +#ifdef CONFIG_DRAM_ECC + ldr r0, =0x1e6e0004 + ldr r1, [r0] + orr r1, r1, #0x80 + str r1, [r0] + + ldr r0, =0x1e6e0054 + ldr r1, =0x05000000 /* ECC protected memory size, default set at 80M */ + str r1, [r0] + + ldr r0, =0x1e6e007C + ldr r1, =0x00000000 + str r1, [r0] + ldr r0, =0x1e6e0074 + str r1, [r0] + + ldr r0, =0x1e6e0070 + ldr r1, =0x00000221 + str r1, [r0] + + ldr r0, =0x1e6e0070 + ldr r2, =0x00001000 +ECC_Init_Flag: + ldr r1, [r0] + tst r1, r2 @ D[12] = 1, Done + beq ECC_Init_Flag + + ldr r0, =0x1e6e0070 + ldr r1, =0x00000000 + str r1, [r0] + + ldr r0, =0x1e6e0050 + ldr r1, =0x80000000 + str r1, [r0] + + ldr r0, =0x1e6e0050 + ldr r1, =0x00000000 + str r1, [r0] + + ldr r0, =0x1e6e0070 + ldr r1, =0x00000400 + str r1, [r0] +#endif + ldr r0, =0x1e6e2008 @ Set Video ECLK phase + ldr r1, [r0] + ldr r2, =0xfffffff3 + and r1, r1, r2 + orr r1, r1, #0x08 + str r1, [r0] + + ldr r0, =0x1e6e2004 + ldr r1, [r0] + ldr r2, =0xFFBFFFFF @ Enable JTAG Master, solve ARM stucked by JTAG issue + and r1, r1, r2 + str r1, [r0] + + ldr r0, =0x1e6e2048 @ Set MAC interface delay timing + ldr r1, =0x2255 + str r1, [r0] + + ldr r0, =0x1e6e2070 @ Set MAC AHB bus clock + ldr r1, [r0] + mov r2, #0x04 @ Default RMII, set MHCLK = HPLL/10 + tst r1, #0xC0 + movne r2, #0x02 @ if RGMII, set MHCLK = HPLL/6 + ldr r0, =0x1e6e2008 + ldr r1, [r0] + bic r1, r1, #0x00070000 + orr r1, r1, r2, lsl #16 + str r1, [r0] + +/* Test - DRAM initial time */ + ldr r0, =0x1e782040 + ldr r1, [r0] + ldr r0, =0xFFFFFFFF + sub r1, r0, r1 + ldr r0, =0x1e72009c + str r1, [r0] + ldr r0, =0x1e7200a4 + str r1, [r0] + ldr r0, =0x1e782030 + ldr r1, [r0] + bic r1, r1, #0x0000F000 + str r1, [r0] +/* Test - DRAM initial time */ + +/****************************************************************************** + Reset GPIO registers when watchdog reset + ******************************************************************************/ + ldr r0, =0x1e6e207c @ Check Revision ID + ldr r1, [r0] + mov r1, r1, lsr #24 + cmp r1, #0x02 + bne platform_exit3 @ not match AST2400 + + ldr r0, =0x1e6e203c @ Check watchdog reset event + ldr r1, [r0] + and r1, r1, #0x06 + cmp r1, #0x0 + beq platform_exit3 @ no watchdog reset event + + ldr r0, =0x1e6e209c @ Check watchdog GPIO selection + ldr r1, [r0] + mov r1, r1, lsr #21 + tst r1, #0x01 + beq platform_exit3 @ no watchdog reset selection + + ldr r1, =0x00000000 @ clear GPIO register reset by PRST_N + ldr r2, =0xFFFFFFFF + ldr r0, =0x1e780008 + str r1, [r0] + ldr r0, =0x1e78000c + str r1, [r0] + ldr r0, =0x1e780010 + str r1, [r0] + ldr r0, =0x1e780014 + str r1, [r0] + ldr r0, =0x1e780018 + str r2, [r0] + ldr r0, =0x1e780028 + str r1, [r0] + ldr r0, =0x1e78002c + str r1, [r0] + ldr r0, =0x1e780030 + str r1, [r0] + ldr r0, =0x1e780034 + str r1, [r0] + ldr r0, =0x1e780038 + str r2, [r0] + ldr r0, =0x1e780040 + str r1, [r0] + ldr r0, =0x1e780044 + str r1, [r0] + ldr r0, =0x1e780048 + str r1, [r0] + ldr r0, =0x1e78004c + str r1, [r0] + ldr r0, =0x1e780050 + str r1, [r0] + ldr r0, =0x1e780054 + str r1, [r0] + ldr r0, =0x1e780058 + str r1, [r0] + ldr r0, =0x1e780060 + str r1, [r0] + ldr r0, =0x1e780064 + str r1, [r0] + ldr r0, =0x1e780068 + str r1, [r0] + ldr r0, =0x1e78006c + str r1, [r0] + ldr r0, =0x1e780090 + str r1, [r0] + ldr r0, =0x1e780094 + str r1, [r0] + ldr r0, =0x1e780098 + str r1, [r0] + ldr r0, =0x1e78009c + str r1, [r0] + ldr r0, =0x1e7800a0 + str r1, [r0] + ldr r0, =0x1e7800a4 + str r1, [r0] + ldr r0, =0x1e7800a8 + str r2, [r0] + ldr r0, =0x1e7800b0 + str r1, [r0] + ldr r0, =0x1e7800b4 + str r1, [r0] + ldr r0, =0x1e7800b8 + str r1, [r0] + ldr r0, =0x1e7800e0 + str r1, [r0] + ldr r0, =0x1e7800e4 + str r1, [r0] + ldr r0, =0x1e7800e8 + str r1, [r0] + ldr r0, =0x1e7800ec + str r1, [r0] + ldr r0, =0x1e7800f0 + str r1, [r0] + ldr r0, =0x1e7800f4 + str r1, [r0] + ldr r0, =0x1e7800f8 + str r2, [r0] + ldr r0, =0x1e780100 + str r1, [r0] + ldr r0, =0x1e780104 + str r1, [r0] + ldr r0, =0x1e780108 + str r1, [r0] + ldr r0, =0x1e780110 + str r1, [r0] + ldr r0, =0x1e780114 + str r1, [r0] + ldr r0, =0x1e780118 + str r1, [r0] + ldr r0, =0x1e78011c + str r1, [r0] + ldr r0, =0x1e780120 + str r1, [r0] + ldr r0, =0x1e780124 + str r1, [r0] + ldr r0, =0x1e780128 + str r2, [r0] + ldr r0, =0x1e780130 + str r1, [r0] + ldr r0, =0x1e780134 + str r1, [r0] + ldr r0, =0x1e780138 + str r1, [r0] + ldr r0, =0x1e780140 + str r1, [r0] + ldr r0, =0x1e780144 + str r1, [r0] + ldr r0, =0x1e780148 + str r1, [r0] + ldr r0, =0x1e78014c + str r1, [r0] + ldr r0, =0x1e780150 + str r1, [r0] + ldr r0, =0x1e780154 + str r1, [r0] + ldr r0, =0x1e780158 + str r2, [r0] + ldr r0, =0x1e780160 + str r1, [r0] + ldr r0, =0x1e780164 + str r1, [r0] + ldr r0, =0x1e780168 + str r1, [r0] + ldr r0, =0x1e780170 + str r1, [r0] + ldr r0, =0x1e780174 + str r1, [r0] + ldr r0, =0x1e780178 + str r1, [r0] + ldr r0, =0x1e78017c + str r1, [r0] + ldr r0, =0x1e780180 + str r1, [r0] + ldr r0, =0x1e780184 + str r1, [r0] + ldr r0, =0x1e780188 + str r2, [r0] + ldr r0, =0x1e780190 + str r1, [r0] + ldr r0, =0x1e780194 + str r1, [r0] + ldr r0, =0x1e780198 + str r1, [r0] + ldr r0, =0x1e7801d0 + str r1, [r0] + ldr r0, =0x1e7801d4 + str r1, [r0] + + ldr r0, =0x1e780204 @ clear SGPIOM register reset by PRST_N + str r1, [r0] + ldr r0, =0x1e780208 + str r1, [r0] + ldr r0, =0x1e78020c + str r1, [r0] + ldr r0, =0x1e780210 + str r1, [r0] + ldr r0, =0x1e780214 + str r2, [r0] + ldr r0, =0x1e780220 + str r1, [r0] + ldr r0, =0x1e780224 + str r1, [r0] + ldr r0, =0x1e780228 + str r1, [r0] + ldr r0, =0x1e78022c + str r1, [r0] + ldr r0, =0x1e780230 + str r2, [r0] + ldr r0, =0x1e78023c + str r1, [r0] + ldr r0, =0x1e780240 + str r1, [r0] + ldr r0, =0x1e780244 + str r1, [r0] + ldr r0, =0x1e780248 + str r1, [r0] + ldr r0, =0x1e78024c + str r2, [r0] + ldr r0, =0x1e780254 + ldr r3, =0x01000040 + str r3, [r0] + ldr r0, =0x1e780258 + str r1, [r0] + ldr r0, =0x1e78025c + str r1, [r0] + ldr r0, =0x1e780260 + str r1, [r0] + + ldr r0, =0x1e780300 @ clear SGPIOS register reset by PRST_N + str r1, [r0] + ldr r0, =0x1e780304 + str r1, [r0] + ldr r0, =0x1e780308 + str r1, [r0] + ldr r0, =0x1e78030c + str r1, [r0] + ldr r0, =0x1e780310 + str r1, [r0] + ldr r0, =0x1e780314 + str r1, [r0] + ldr r0, =0x1e780318 + str r2, [r0] + ldr r0, =0x1e78031c + str r2, [r0] + ldr r0, =0x1e780320 + str r2, [r0] + +platform_exit3: + +/****************************************************************************** + SPI Timing Calibration, not applicable to AST2300 series + ******************************************************************************/ + ldr r0, =0x1e6e207c @ Check Revision ID + ldr r1, [r0] + mov r1, r1, lsr #24 + cmp r1, #0x02 + blt platform_exit4 @ not match AST2400 or later + + ldr r0, =0x1e6e2070 @ Check SPI flash + ldr r1, [r0] + and r1, r1, #0x03 + cmp r1, #0x02 + bne platform_exit4 + + mov r2, #0x0 + mov r6, #0x0 + mov r7, #0x0 + init_spi_checksum +spi_checksum_wait_0: + ldr r1, [r0] + tst r1, r2 + beq spi_checksum_wait_0 + ldr r0, =0x1e620090 + ldr r5, [r0] @ record golden checksum + ldr r0, =0x1e620080 + mov r1, #0x0 + str r1, [r0] + + ldr r0, =0x1e620010 @ set to fast read mode + ldr r1, =0x000B0041 + str r1, [r0] + + ldr r6, =0x00F7E6D0 @ Init spiclk loop + mov r8, #0x0 @ Init delay record + +spi_cbr_next_clkrate: + mov r6, r6, lsr #0x4 + cmp r6, #0x0 + beq spi_cbr_end + + mov r7, #0x0 @ Init delay loop + mov r8, r8, lsl #4 + +spi_cbr_next_delay_s: + mov r2, #0x8 + init_spi_checksum +spi_checksum_wait_1: + ldr r1, [r0] + tst r1, r2 + beq spi_checksum_wait_1 + ldr r0, =0x1e620090 + ldr r2, [r0] @ read checksum + ldr r0, =0x1e620080 + mov r1, #0x0 + str r1, [r0] + cmp r2, r5 + bne spi_cbr_next_delay_e + + mov r2, #0x0 + init_spi_checksum +spi_checksum_wait_2: + ldr r1, [r0] + tst r1, r2 + beq spi_checksum_wait_2 + ldr r0, =0x1e620090 + ldr r2, [r0] @ read checksum + ldr r0, =0x1e620080 + mov r1, #0x0 + str r1, [r0] + cmp r2, r5 + bne spi_cbr_next_delay_e + + orr r8, r8, r7 @ record passed delay + b spi_cbr_next_clkrate + +spi_cbr_next_delay_e: + add r7, r7, #0x1 + cmp r7, #0x6 + blt spi_cbr_next_delay_s + b spi_cbr_next_clkrate + +spi_cbr_end: + ldr r0, =0x1e620094 + str r8, [r0] + ldr r0, =0x1e620010 + mov r1, #0x0 + str r1, [r0] + +platform_exit4: + + /* restore lr */ + mov lr, r4 + + /* back to arch calling code */ + mov pc, lr diff --git a/arch/arm/mach-aspeed/platform_g5.S b/arch/arm/mach-aspeed/platform_g5.S new file mode 100644 index 0000000000..c810f44b9a --- /dev/null +++ b/arch/arm/mach-aspeed/platform_g5.S @@ -0,0 +1,1999 @@ +/* + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +/* + * Board specific setup info + * + ****************************************************************************** + * ASPEED Technology Inc. + * AST25x0 DDR3/DDR4 SDRAM controller initialization sequence + * + * Gary Hsu, + * + * Version : 11 + * Release date: 2016.05.10 + * + * Change List : + * V2|2014.07.25 : 1. Modify HPLL config sequence + * V2|2014.07.30 : 1. Modify DDR3 AC parameters table + * | 2. Turn on ZQCS mode + * V2|2014.08.13 : 1. Add disable XDMA + * V2|2014.09.09 : 1. Disable CKE dynamic power down + * V2|2014.10.31 : 1. Enable VGA wide screen support (SCU40[0]=1) + * V2|2015.03.26 : 1. Revise AC timing table + * | 2. Add check code to bypass A0 patch + * | 3. Add MPLL parameter of A1 + * | 4. Set X-DMA into VGA memory domain + * V2|2015.04.24 : 1. Add disabling all DRAM requests during PHY init + * | 2. Set MCR1C & MCR38 + * V3|2015.05.13 : 1. Modify DDR4 PHY Vref training algorithm + * | 2. Enable CKE dynamic power down + * V4|2015.06.15 : 1. Add MAC timing setting + * V5|2015.07.09 : 1. Modify MHCLK divider ratio + * | 2. Add DDR read margin report + * V6|2015.08.13 : 1. Disable MMC password before exit + * V6|2015.08.24 : 1. Fix SCU160 parameter value for CLKIN=25MHz condition + * V7|2015.09.18 : 1. Clear AHB bus lock condition at power up time + * | 2. Add reset MMC controller to solve init DRAM again during VGA ON + * V7|2015.09.22 : 1. Add watchdog full reset for resolving reset incomplete issue at fast reset condition + * | 2. Add DRAM stress test after train complete, and redo DRAM initial if stress fail + * | 3. Enable JTAG master mode + * | 4. Add DDR4 Vref trainig retry timeout + * V8|2015.11.02 : 1. Clear software strap flag before doing watchdog full reset + * |2015.12.10 : 1. Add USB PHY initial code + * |2016.01.27 : 1. Modify the first reset from full chip reset to SOC reset + * | 2. Remove HPLL/MPLL patch code for revision A0 + * | 3. Move the reset_mmc code to be after MPLL initialized + * V9|2016.02.19 : 1. Remove definietion "CONFIG_FIRMWARE_2ND_BOOT" + * V10|2016.04.21 : 1. Add USB PHY initial code - port B, to prevent wrong state on USB pins + * V11|2016.05.10 : 1. Add DRAM Extended temperature range support + * + * Optional define variable + * 1. DRAM Speed // + * CONFIG_DRAM_1333 // + * CONFIG_DRAM_1600 // (default) + * 2. ECC Function enable + * CONFIG_DRAM_ECC // define to enable ECC function + * CONFIG_DRAM_ECC_SIZE // define the ECC protected memory size + * 3. UART5 message output // + * CONFIG_DRAM_UART_38400 // set the UART baud rate to 38400, default is 115200 + * 4. DRAM Type + * CONFIG_DDR3_8GSTACK // DDR3 8Gbit Stack die + * CONFIG_DDR4_4GX8 // DDR4 4Gbit X8 dual part + * 5. Firmware 2nd boot flash + * CONFIG_FIRMWARE_2ND_BOOT (Removed) + * 6. Enable DRAM extended temperature range mode + * CONFIG_DRAM_EXT_TEMP + ****************************************************************************** + */ + +#include +#include + +/****************************************************************************** + r4 : return program counter + r5 : DDR speed timing table base address + Free registers: + r0, r1, r2, r3, r6, r7, r8, r9, r10, r11 + ******************************************************************************/ +#define ASTMMC_INIT_VER 0x0B @ 8bit verison number +#define ASTMMC_INIT_DATE 0x20160510 @ Release date + +#define ASTMMC_REGIDX_010 0x00 +#define ASTMMC_REGIDX_014 0x04 +#define ASTMMC_REGIDX_018 0x08 +#define ASTMMC_REGIDX_020 0x0C +#define ASTMMC_REGIDX_024 0x10 +#define ASTMMC_REGIDX_02C 0x14 +#define ASTMMC_REGIDX_030 0x18 +#define ASTMMC_REGIDX_214 0x1C +#define ASTMMC_REGIDX_2E0 0x20 +#define ASTMMC_REGIDX_2E4 0x24 +#define ASTMMC_REGIDX_2E8 0x28 +#define ASTMMC_REGIDX_2EC 0x2C +#define ASTMMC_REGIDX_2F0 0x30 +#define ASTMMC_REGIDX_2F4 0x34 +#define ASTMMC_REGIDX_2F8 0x38 +#define ASTMMC_REGIDX_RFC 0x3C +#define ASTMMC_REGIDX_PLL 0x40 + +TIME_TABLE_DDR3_1333: + .word 0x53503C37 @ 0x010 + .word 0xF858D47F @ 0x014 + .word 0x00010000 @ 0x018 + .word 0x00000000 @ 0x020 + .word 0x00000000 @ 0x024 + .word 0x02101C60 @ 0x02C + .word 0x00000040 @ 0x030 + .word 0x00000020 @ 0x214 + .word 0x02001000 @ 0x2E0 + .word 0x0C000085 @ 0x2E4 + .word 0x000BA018 @ 0x2E8 + .word 0x2CB92104 @ 0x2EC + .word 0x07090407 @ 0x2F0 + .word 0x81000700 @ 0x2F4 + .word 0x0C400800 @ 0x2F8 + .word 0x7F5E3A27 @ tRFC + .word 0x00005B80 @ PLL +TIME_TABLE_DDR3_1600: + .word 0x64604D38 @ 0x010 + .word 0x29690599 @ 0x014 + .word 0x00000300 @ 0x018 + .word 0x00000000 @ 0x020 + .word 0x00000000 @ 0x024 + .word 0x02181E70 @ 0x02C + .word 0x00000040 @ 0x030 + .word 0x00000024 @ 0x214 + .word 0x02001300 @ 0x2E0 + .word 0x0E0000A0 @ 0x2E4 + .word 0x000E001B @ 0x2E8 + .word 0x35B8C105 @ 0x2EC + .word 0x08090408 @ 0x2F0 + .word 0x9B000800 @ 0x2F4 + .word 0x0E400A00 @ 0x2F8 + .word 0x9971452F @ tRFC + .word 0x000071C1 @ PLL + +TIME_TABLE_DDR4_1333: + .word 0x53503D26 @ 0x010 + .word 0xE878D87F @ 0x014 + .word 0x00019000 @ 0x018 + .word 0x08000000 @ 0x020 + .word 0x00000400 @ 0x024 + .word 0x00000200 @ 0x02C + .word 0x00000101 @ 0x030 + .word 0x00000020 @ 0x214 + .word 0x03002200 @ 0x2E0 + .word 0x0C000085 @ 0x2E4 + .word 0x000BA01A @ 0x2E8 + .word 0x2CB92106 @ 0x2EC + .word 0x07060606 @ 0x2F0 + .word 0x81000700 @ 0x2F4 + .word 0x0C400800 @ 0x2F8 + .word 0x7F5E3A3A @ tRFC + .word 0x00005B80 @ PLL +TIME_TABLE_DDR4_1600: + .word 0x63604E37 @ 0x010 + .word 0xE97AFA99 @ 0x014 + .word 0x00019000 @ 0x018 + .word 0x08000000 @ 0x020 + .word 0x00000400 @ 0x024 + .word 0x00000410 @ 0x02C + .word 0x00000101 @ 0x030 + .word 0x00000024 @ 0x214 + .word 0x03002900 @ 0x2E0 + .word 0x0E0000A0 @ 0x2E4 + .word 0x000E001C @ 0x2E8 + .word 0x35B8C106 @ 0x2EC + .word 0x08080607 @ 0x2F0 + .word 0x9B000900 @ 0x2F4 + .word 0x0E400A00 @ 0x2F8 + .word 0x99714545 @ tRFC + .word 0x000071C1 @ PLL + + .macro init_delay_timer + ldr r0, =0x1e782024 @ Set Timer3 Reload + str r2, [r0] + + ldr r0, =0x1e6c0038 @ Clear Timer3 ISR + ldr r1, =0x00040000 + str r1, [r0] + + ldr r0, =0x1e782030 @ Enable Timer3 + mov r2, #7 + mov r1, r2, lsl #8 + str r1, [r0] + + ldr r0, =0x1e6c0090 @ Check ISR for Timer3 timeout + .endm + + .macro check_delay_timer + ldr r1, [r0] + bic r1, r1, #0xFFFBFFFF + mov r2, r1, lsr #18 + cmp r2, #0x01 + .endm + + .macro clear_delay_timer + ldr r0, =0x1e78203C @ Disable Timer3 + mov r2, #0xF + mov r1, r2, lsl #8 + str r1, [r0] + + ldr r0, =0x1e6c0038 @ Clear Timer3 ISR + ldr r1, =0x00040000 + str r1, [r0] + .endm + + .macro init_spi_checksum + ldr r0, =0x1e620084 + ldr r1, =0x20010000 + str r1, [r0] + ldr r0, =0x1e62008C + ldr r1, =0x20000200 + str r1, [r0] + ldr r0, =0x1e620080 + ldr r1, =0x0000000D + orr r2, r2, r7 + orr r1, r1, r2, lsl #8 + and r2, r6, #0xF + orr r1, r1, r2, lsl #4 + str r1, [r0] + ldr r0, =0x1e620008 + ldr r2, =0x00000800 + .endm + + .macro print_hex_char + and r1, r1, #0xF + cmp r1, #9 + addgt r1, r1, #0x37 + addle r1, r1, #0x30 + str r1, [r0] + .endm + +/****************************************************************************** + Calibration Macro End + ******************************************************************************/ + +.globl lowlevel_init +lowlevel_init: + +init_dram: + /* save lr */ + mov r4, lr + + /* Clear AHB bus lock condition */ + ldr r0, =0x1e600000 + ldr r1, =0xAEED1A03 + str r1, [r0] + ldr r0, =0x1e600084 + ldr r1, =0x00010000 + str r1, [r0] + add r0, r0, #0x4 + mov r1, #0x0 + str r1, [r0] + + ldr r0, =0x1e6e2000 + ldr r1, =0x1688a8a8 + str r1, [r0] + + /* Reset again */ + ldr r0, =0x1e6e2070 @ check fast reset flag + ldr r2, =0x08000000 + ldr r1, [r0] + tst r1, r2 + beq bypass_first_reset + + ldr r0, =0x1e785010 + ldr r3, [r0] + cmp r3, #0x0 + beq start_first_reset + add r0, r0, #0x04 + mov r3, #0x77 + str r3, [r0] + ldr r0, =0x1e720004 + str r1, [r0] + add r0, r0, #0x04 + str r1, [r0] + add r0, r0, #0x04 + str r1, [r0] + ldr r0, =0x1e6e207c @ clear fast reset flag + str r2, [r0] + ldr r0, =0x1e6e203c @ clear watchdog reset flag + ldr r1, [r0] + and r1, r1, #0x01 + str r1, [r0] + b bypass_first_reset + +start_first_reset: + ldr r0, =0x1e62009c @ clear software strap flag for doing again after reset + ldr r1, =0xAEEDFC20 + str r1, [r0] + ldr r0, =0x1e785004 + ldr r1, =0x00000001 + str r1, [r0] + ldr r0, =0x1e785008 + ldr r1, =0x00004755 + str r1, [r0] + ldr r0, =0x1e78500c @ enable soc reset + ldr r1, =0x00000013 + str r1, [r0] +wait_first_reset: + b wait_first_reset + +bypass_first_reset: + /* Enable Timer separate clear mode */ + ldr r0, =0x1e782038 + mov r1, #0xAE + str r1, [r0] + +/* Test - DRAM initial time */ + ldr r0, =0x1e78203c + ldr r1, =0x0000F000 + str r1, [r0] + + ldr r0, =0x1e782044 + ldr r1, =0xFFFFFFFF + str r1, [r0] + + ldr r0, =0x1e782030 + mov r2, #3 + mov r1, r2, lsl #12 + str r1, [r0] +/* Test - DRAM initial time */ + + /*Set Scratch register Bit 7 before initialize*/ + ldr r0, =0x1e6e2000 + ldr r1, =0x1688a8a8 + str r1, [r0] + + ldr r0, =0x1e6e2040 + ldr r1, [r0] + orr r1, r1, #0x80 + str r1, [r0] + + /* Configure USB ports to the correct pin state */ + ldr r0, =0x1e6e200c @ enable portA clock + ldr r2, =0x00004000 + ldr r1, [r0] + orr r1, r1, r2 + str r1, [r0] + ldr r0, =0x1e6e2094 @ set portB as host mode + ldr r1, =0x00004000 + str r1, [r0] + ldr r0, =0x1e6e2070 + ldr r2, =0x00800000 + ldr r1, [r0] + tst r1, r2 + beq bypass_USB_init + ldr r0, =0x1e6e207c + str r2, [r0] + + /* Delay about 1ms */ + clear_delay_timer + ldr r2, =0x000003E8 @ Set Timer3 Reload = 1 ms + init_delay_timer +wait_usb_init: + check_delay_timer + bne wait_usb_init + clear_delay_timer + /* end delay 1ms */ + + ldr r0, =0x1e6e2070 + ldr r1, =0x00800000 + str r1, [r0] + +bypass_USB_init: + /* Enable AXI_P */ + ldr r0, =0x00000016 + mrc p15, 0, r1, c15, c2, 4 + mcr p15, 0, r0, c15, c2, 4 + +/****************************************************************************** + Disable WDT2 for 2nd boot function + ******************************************************************************/ +#ifndef CONFIG_FIRMWARE_2ND_BOOT + ldr r0, =0x1e78502c + mov r1, #0 + str r1, [r0] +#endif +/****************************************************************************** + Disable WDT3 for SPI Address mode (3 or 4 bytes) detection function + ******************************************************************************/ + ldr r0, =0x1e78504c + mov r1, #0 + str r1, [r0] + + ldr r0, =0x1e6e0000 + ldr r1, =0xFC600309 + str r1, [r0] + + /* Check Scratch Register Bit 6 */ + ldr r0, =0x1e6e2040 + ldr r1, [r0] + bic r1, r1, #0xFFFFFFBF + mov r2, r1, lsr #6 + cmp r2, #0x01 + beq platform_exit + + /* Disable VGA display */ + ldr r0, =0x1e6e202c + ldr r1, [r0] + orr r1, r1, #0x40 + str r1, [r0] + + /* Set M-PLL */ +#if defined (CONFIG_DRAM_1333) + ldr r2, =0xC48066C0 @ load PLL parameter for 24Mhz CLKIN (330) +#else + ldr r2, =0x93002400 @ load PLL parameter for 24Mhz CLKIN (396) +#endif + + ldr r0, =0x1e6e2070 @ Check CLKIN = 25MHz + ldr r1, [r0] + mov r1, r1, lsr #23 + tst r1, #0x01 + beq set_MPLL +#if defined (CONFIG_DRAM_1333) + ldr r2, =0xC4806680 @ load PLL parameter for 25Mhz CLKIN (331) +#else + ldr r2, =0x930023E0 @ load PLL parameter for 25Mhz CLKIN (400) +#endif + ldr r0, =0x1e6e2160 @ set 24M Jitter divider (HPLL=825MHz) + ldr r1, =0x00011320 + str r1, [r0] + +set_MPLL: + ldr r0, =0x1e6e2020 @ M-PLL (DDR SDRAM) Frequency + str r2, [r0] + + clear_delay_timer + + /* Delay about 3ms */ + ldr r2, =0x00000BB8 @ Set Timer3 Reload = 3 ms + init_delay_timer +wait_mpll_init: + check_delay_timer + bne wait_mpll_init + clear_delay_timer + /* end delay 3ms */ + + /* Reset MMC */ +reset_mmc: + ldr r0, =0x1e78505c + ldr r1, =0x00000004 + str r1, [r0] + ldr r0, =0x1e785044 + ldr r1, =0x00000001 + str r1, [r0] + ldr r0, =0x1e785048 + ldr r1, =0x00004755 + str r1, [r0] + ldr r0, =0x1e78504c + ldr r1, =0x00000013 + str r1, [r0] +wait_mmc_reset: + ldr r1, [r0] + tst r1, #0x02 + bne wait_mmc_reset + + ldr r0, =0x1e78505c + ldr r1, =0x023FFFF3 + str r1, [r0] + ldr r0, =0x1e785044 + ldr r1, =0x000F4240 + str r1, [r0] + ldr r0, =0x1e785048 + ldr r1, =0x00004755 + str r1, [r0] + ldr r0, =0x1e785054 + ldr r1, =0x00000077 + str r1, [r0] + + ldr r0, =0x1e6e0000 + ldr r1, =0xFC600309 +wait_mmc_reset_done: + str r1, [r0] + ldr r2, [r0] + cmp r2, #0x1 + bne wait_mmc_reset_done + + ldr r0, =0x1e6e0034 @ disable MMC request + ldr r1, =0x00020000 + str r1, [r0] + +/* Debug - UART console message */ + ldr r0, =0x1e78400c + mov r1, #0x83 + str r1, [r0] + + ldr r0, =0x1e6e202c + ldr r2, [r0] + mov r2, r2, lsr #12 + tst r2, #0x01 + ldr r0, =0x1e784000 + moveq r1, #0x0D @ Baudrate 115200 + movne r1, #0x01 @ Baudrate 115200, div13 +#ifdef CONFIG_DRAM_UART_38400 + moveq r1, #0x27 @ Baudrate 38400 + movne r1, #0x03 @ Baudrate 38400 , div13 +#endif + str r1, [r0] + + ldr r0, =0x1e784004 + mov r1, #0x00 + str r1, [r0] + + ldr r0, =0x1e78400c + mov r1, #0x03 + str r1, [r0] + + ldr r0, =0x1e784008 + mov r1, #0x07 + str r1, [r0] + + ldr r0, =0x1e784000 + mov r1, #0x0D @ '\r' + str r1, [r0] + mov r1, #0x0A @ '\n' + str r1, [r0] + mov r1, #0x44 @ 'D' + str r1, [r0] + mov r1, #0x52 @ 'R' + str r1, [r0] + mov r1, #0x41 @ 'A' + str r1, [r0] + mov r1, #0x4D @ 'M' + str r1, [r0] + mov r1, #0x20 @ ' ' + str r1, [r0] + mov r1, #0x49 @ 'I' + str r1, [r0] + mov r1, #0x6E @ 'n' + str r1, [r0] + mov r1, #0x69 @ 'i' + str r1, [r0] + mov r1, #0x74 @ 't' + str r1, [r0] + mov r1, #0x2D @ '-' + str r1, [r0] + mov r1, #0x56 @ 'V' + str r1, [r0] + mov r1, #ASTMMC_INIT_VER + mov r1, r1, lsr #4 + print_hex_char + mov r1, #ASTMMC_INIT_VER + print_hex_char + mov r1, #0x2D @ '-' + str r1, [r0] + ldr r0, =0x1e784014 +wait_print: + ldr r1, [r0] + tst r1, #0x40 + beq wait_print + ldr r0, =0x1e784000 + mov r1, #0x44 @ 'D' + str r1, [r0] + mov r1, #0x44 @ 'D' + str r1, [r0] + mov r1, #0x52 @ 'R' + str r1, [r0] +/* Debug - UART console message */ + +/****************************************************************************** + Init DRAM common registers + ******************************************************************************/ + ldr r0, =0x1e6e0034 @ disable SDRAM reset + ldr r1, =0x00020080 + str r1, [r0] + + ldr r0, =0x1e6e0008 + ldr r1, =0x2003000F /* VGA */ + str r1, [r0] + + ldr r0, =0x1e6e0038 @ disable all DRAM requests except CPU during PHY init + ldr r1, =0xFFFFEBFF + str r1, [r0] + + ldr r0, =0x1e6e0040 + ldr r1, =0x88448844 + str r1, [r0] + + ldr r0, =0x1e6e0044 + ldr r1, =0x24422288 + str r1, [r0] + + ldr r0, =0x1e6e0048 + ldr r1, =0x22222222 + str r1, [r0] + + ldr r0, =0x1e6e004c + ldr r1, =0x22222222 + str r1, [r0] + + ldr r0, =0x1e6e0050 + ldr r1, =0x80000000 + str r1, [r0] + + ldr r1, =0x00000000 + ldr r0, =0x1e6e0208 @ PHY Setting + str r1, [r0] + ldr r0, =0x1e6e0218 + str r1, [r0] + ldr r0, =0x1e6e0220 + str r1, [r0] + ldr r0, =0x1e6e0228 + str r1, [r0] + ldr r0, =0x1e6e0230 + str r1, [r0] + ldr r0, =0x1e6e02a8 + str r1, [r0] + ldr r0, =0x1e6e02b0 + str r1, [r0] + + ldr r0, =0x1e6e0240 + ldr r1, =0x86000000 + str r1, [r0] + + ldr r0, =0x1e6e0244 + ldr r1, =0x00008600 + str r1, [r0] + + ldr r0, =0x1e6e0248 + ldr r1, =0x80000000 + str r1, [r0] + + ldr r0, =0x1e6e024c + ldr r1, =0x80808080 + str r1, [r0] + + /* Check DRAM Type by H/W Trapping */ + ldr r0, =0x1e6e2070 + ldr r1, [r0] + ldr r2, =0x01000000 @ bit[24]=1 => DDR4 + tst r1, r2 + bne ddr4_init + b ddr3_init +.LTORG + +/****************************************************************************** + DDR3 Init + ******************************************************************************/ +ddr3_init: +/* Debug - UART console message */ + ldr r0, =0x1e784000 + mov r1, #0x33 @ '3' + str r1, [r0] + mov r1, #0x0D @ '\r' + str r1, [r0] + mov r1, #0x0A @ '\n' + str r1, [r0] +/* Debug - UART console message */ + +#if defined (CONFIG_DRAM_1333) + adrl r5, TIME_TABLE_DDR3_1333 @ Init DRAM parameter table +#else + adrl r5, TIME_TABLE_DDR3_1600 +#endif + + ldr r0, =0x1e6e0004 +#ifdef CONFIG_DDR3_8GSTACK + ldr r1, =0x00000323 @ Init to 8GB stack +#else + ldr r1, =0x00000303 @ Init to 8GB +#endif + str r1, [r0] + + ldr r0, =0x1e6e0010 + ldr r1, [r5, #ASTMMC_REGIDX_010] + str r1, [r0] + + ldr r0, =0x1e6e0014 + ldr r1, [r5, #ASTMMC_REGIDX_014] + str r1, [r0] + + ldr r0, =0x1e6e0018 + ldr r1, [r5, #ASTMMC_REGIDX_018] + str r1, [r0] + + /* DRAM Mode Register Setting */ + ldr r0, =0x1e6e0020 @ MRS_4/6 + ldr r1, [r5, #ASTMMC_REGIDX_020] + str r1, [r0] + + ldr r0, =0x1e6e0024 @ MRS_5 + ldr r1, [r5, #ASTMMC_REGIDX_024] + str r1, [r0] + + ldr r0, =0x1e6e002c @ MRS_0/2 + ldr r1, [r5, #ASTMMC_REGIDX_02C] + mov r2, #0x1 + orr r1, r1, r2, lsl #8 + str r1, [r0] + + ldr r0, =0x1e6e0030 @ MRS_1/3 + ldr r1, [r5, #ASTMMC_REGIDX_030] + str r1, [r0] + + /* Start DDR PHY Setting */ + ldr r0, =0x1e6e0200 + ldr r1, =0x02492AAE + str r1, [r0] + + ldr r0, =0x1e6e0204 +#ifdef CONFIG_DDR3_8GSTACK + ldr r1, =0x10001001 +#else + ldr r1, =0x00001001 +#endif + str r1, [r0] + + ldr r0, =0x1e6e020c + ldr r1, =0x55E00B0B + str r1, [r0] + + ldr r0, =0x1e6e0210 + ldr r1, =0x20000000 + str r1, [r0] + + ldr r0, =0x1e6e0214 + ldr r1, [r5, #ASTMMC_REGIDX_214] + str r1, [r0] + + ldr r0, =0x1e6e02e0 + ldr r1, [r5, #ASTMMC_REGIDX_2E0] + str r1, [r0] + + ldr r0, =0x1e6e02e4 + ldr r1, [r5, #ASTMMC_REGIDX_2E4] + str r1, [r0] + + ldr r0, =0x1e6e02e8 + ldr r1, [r5, #ASTMMC_REGIDX_2E8] + str r1, [r0] + + ldr r0, =0x1e6e02ec + ldr r1, [r5, #ASTMMC_REGIDX_2EC] + str r1, [r0] + + ldr r0, =0x1e6e02f0 + ldr r1, [r5, #ASTMMC_REGIDX_2F0] + str r1, [r0] + + ldr r0, =0x1e6e02f4 + ldr r1, [r5, #ASTMMC_REGIDX_2F4] + str r1, [r0] + + ldr r0, =0x1e6e02f8 + ldr r1, [r5, #ASTMMC_REGIDX_2F8] + str r1, [r0] + + ldr r0, =0x1e6e0290 + ldr r1, =0x00100008 + str r1, [r0] + + ldr r0, =0x1e6e02c0 + ldr r1, =0x00000006 + str r1, [r0] + + /* Controller Setting */ + ldr r0, =0x1e6e0060 @ Fire DDRPHY Init + ldr r1, =0x00000005 + str r1, [r0] + + ldr r0, =0x1e6e0034 + ldr r1, =0x00020091 + str r1, [r0] + +/* Debug - UART console message */ + ldr r0, =0x1e784000 + mov r1, #0x30 @ '0' + str r1, [r0] +/* Debug - UART console message */ + + ldr r0, =0x1e6e0120 + mov r1, #0x00 + str r1, [r0] + b ddr_phy_init_process + +ddr3_phyinit_done: + +/* Debug - UART console message */ + ldr r0, =0x1e784000 + mov r1, #0x31 @ '1' + str r1, [r0] +/* Debug - UART console message */ + + ldr r0, =0x1e6e000c + ldr r1, =0x00000040 + str r1, [r0] + +#ifdef CONFIG_DDR3_8GSTACK + ldr r0, =0x1e6e0028 + ldr r1, =0x00000025 + str r1, [r0] + + ldr r0, =0x1e6e0028 + ldr r1, =0x00000027 + str r1, [r0] + + ldr r0, =0x1e6e0028 + ldr r1, =0x00000023 + str r1, [r0] + + ldr r0, =0x1e6e0028 + ldr r1, =0x00000021 + str r1, [r0] +#endif + + ldr r0, =0x1e6e0028 + ldr r1, =0x00000005 + str r1, [r0] + + ldr r0, =0x1e6e0028 + ldr r1, =0x00000007 + str r1, [r0] + + ldr r0, =0x1e6e0028 + ldr r1, =0x00000003 + str r1, [r0] + + ldr r0, =0x1e6e0028 + ldr r1, =0x00000011 + str r1, [r0] + + ldr r0, =0x1e6e000c + ldr r1, =0x00005C41 + str r1, [r0] + + ldr r0, =0x1e6e0034 + ldr r2, =0x70000000 +ddr3_check_dllrdy: + ldr r1, [r0] + tst r1, r2 + bne ddr3_check_dllrdy + + ldr r0, =0x1e6e000c +#ifdef CONFIG_DRAM_EXT_TEMP + ldr r1, =0x42AA2F81 +#else + ldr r1, =0x42AA5C81 +#endif + str r1, [r0] + + ldr r0, =0x1e6e0034 + ldr r1, =0x0001AF93 + str r1, [r0] + + ldr r0, =0x1e6e0120 @ VGA Compatible Mode + ldr r1, [r5, #ASTMMC_REGIDX_PLL] + str r1, [r0] + + b Calibration_End +.LTORG +/****************************************************************************** + End DDR3 Init + ******************************************************************************/ +/****************************************************************************** + DDR4 Init + ******************************************************************************/ +ddr4_init: +/* Debug - UART console message */ + ldr r0, =0x1e784000 + mov r1, #0x34 @ '4' + str r1, [r0] + mov r1, #0x0D @ '\r' + str r1, [r0] + mov r1, #0x0A @ '\n' + str r1, [r0] +/* Debug - UART console message */ + +#if defined (CONFIG_DRAM_1333) + adrl r5, TIME_TABLE_DDR4_1333 @ Init DRAM parameter table +#else + adrl r5, TIME_TABLE_DDR4_1600 +#endif + + ldr r0, =0x1e6e0004 +#ifdef CONFIG_DDR4_4GX8 + ldr r1, =0x00002313 @ Init to 8GB +#else + ldr r1, =0x00000313 @ Init to 8GB +#endif + str r1, [r0] + + ldr r0, =0x1e6e0010 + ldr r1, [r5, #ASTMMC_REGIDX_010] + str r1, [r0] + + ldr r0, =0x1e6e0014 + ldr r1, [r5, #ASTMMC_REGIDX_014] + str r1, [r0] + + ldr r0, =0x1e6e0018 + ldr r1, [r5, #ASTMMC_REGIDX_018] + str r1, [r0] + + /* DRAM Mode Register Setting */ + ldr r0, =0x1e6e0020 @ MRS_4/6 + ldr r1, [r5, #ASTMMC_REGIDX_020] + str r1, [r0] + + ldr r0, =0x1e6e0024 @ MRS_5 + ldr r1, [r5, #ASTMMC_REGIDX_024] + str r1, [r0] + + ldr r0, =0x1e6e002c @ MRS_0/2 + ldr r1, [r5, #ASTMMC_REGIDX_02C] + mov r2, #0x1 + orr r1, r1, r2, lsl #8 + str r1, [r0] + + ldr r0, =0x1e6e0030 @ MRS_1/3 + ldr r1, [r5, #ASTMMC_REGIDX_030] + str r1, [r0] + + /* Start DDR PHY Setting */ + ldr r0, =0x1e6e0200 + ldr r1, =0x42492AAE + str r1, [r0] + + ldr r0, =0x1e6e0204 + ldr r1, =0x09002000 + str r1, [r0] + + ldr r0, =0x1e6e020c + ldr r1, =0x55E00B0B + str r1, [r0] + + ldr r0, =0x1e6e0210 + ldr r1, =0x20000000 + str r1, [r0] + + ldr r0, =0x1e6e0214 + ldr r1, [r5, #ASTMMC_REGIDX_214] + str r1, [r0] + + ldr r0, =0x1e6e02e0 + ldr r1, [r5, #ASTMMC_REGIDX_2E0] + str r1, [r0] + + ldr r0, =0x1e6e02e4 + ldr r1, [r5, #ASTMMC_REGIDX_2E4] + str r1, [r0] + + ldr r0, =0x1e6e02e8 + ldr r1, [r5, #ASTMMC_REGIDX_2E8] + str r1, [r0] + + ldr r0, =0x1e6e02ec + ldr r1, [r5, #ASTMMC_REGIDX_2EC] + str r1, [r0] + + ldr r0, =0x1e6e02f0 + ldr r1, [r5, #ASTMMC_REGIDX_2F0] + str r1, [r0] + + ldr r0, =0x1e6e02f4 + ldr r1, [r5, #ASTMMC_REGIDX_2F4] + str r1, [r0] + + ldr r0, =0x1e6e02f8 + ldr r1, [r5, #ASTMMC_REGIDX_2F8] + str r1, [r0] + + ldr r0, =0x1e6e0290 + ldr r1, =0x00100008 + str r1, [r0] + + ldr r0, =0x1e6e02c4 + ldr r1, =0x3C183C3C + str r1, [r0] + + ldr r0, =0x1e6e02c8 + ldr r1, =0x00631E0E + str r1, [r0] + + ldr r0, =0x1e6e0034 + ldr r1, =0x0001A991 + str r1, [r0] + +/* Debug - UART console message */ + ldr r0, =0x1e784000 + mov r1, #0x30 @ '0' + str r1, [r0] +/* Debug - UART console message */ + + /******************************************** + PHY Vref Scan + r6 : recorded vref value + r7 : max read eye pass window + r8 : passcnt + r9 : CBRtest result + r10: loopcnt + r11: free + ********************************************/ + ldr r0, =0x1e720000 @ retry count + mov r1, #0x5 + str r1, [r0] +ddr4_vref_phy_cal_start: + mov r7, #0x0 + mov r8, #0x0 + mov r10, #0x3F + + ldr r0, =0x1e720000 + ldr r1, [r0] + subs r1, r1, #0x01 + beq ddr_test_fail + str r1, [r0] + + ldr r0, =0x1e6e0120 + ldr r1, =0x00000001 + str r1, [r0] + +/* Debug - UART console message */ + ldr r0, =0x1e784000 + mov r1, #0x61 @ 'a' + str r1, [r0] +/* Debug - UART console message */ + + ldr r0, =0x1e6e02c0 + ldr r1, =0x00001C06 + str r1, [r0] + +ddr4_vref_phy_loop: + ldr r0, =0x1e6e0060 + ldr r1, =0x00000000 + str r1, [r0] + + add r10, r10, #0x01 + cmp r10, #0x80 + beq ddr4_vref_phy_test_fail @ no valid margin and retry + + ldr r0, =0x1e6e02cc + orr r1, r10, r10, lsl #8 + str r1, [r0] + + ldr r0, =0x1e6e0060 + ldr r1, =0x00000005 + str r1, [r0] + b ddr_phy_init_process + +ddr4_vref_phy_phyinit_done: + + b cbr_test_start + +ddr4_vref_phy_cbrtest_done: + cmp r9, #0x01 + bne ddr4_vref_phy_test_fail + add r8, r8, #0x01 + ldr r0, =0x1e6e03d0 @ read eye pass window + ldr r1, [r0] + mov r2, r1, lsr #8 @ r2 = DQH + and r1, r1, #0xFF @ r1 = DQL + cmp r1, r2 + movgt r1, r2 @ r1 = smaller one + cmp r1, r7 + movgt r6, r10 + movgt r7, r1 + b ddr4_vref_phy_loop + +ddr4_vref_phy_test_fail: + cmp r8, #0x0 + bne ddr4_vref_phy_loop_end + cmp r10, #0x80 + beq ddr4_vref_phy_cal_start + b ddr4_vref_phy_loop + +ddr4_vref_phy_loop_end: + ldr r0, =0x1e6e02cc + orr r1, r6, r6, lsl #8 + str r1, [r0] + + /******************************************** + DDR Vref Scan + r6 : min + r7 : max + r8 : passcnt + r9 : CBRtest result + r10: loopcnt + r11: free + ********************************************/ + ldr r0, =0x1e720000 @ retry count + mov r1, #0x5 + str r1, [r0] +ddr4_vref_ddr_cal_start: + mov r6, #0xFF + mov r7, #0x0 + mov r8, #0x0 + mov r10, #0x0 + + ldr r0, =0x1e720000 + ldr r1, [r0] + subs r1, r1, #0x01 + beq ddr_test_fail + str r1, [r0] + + ldr r0, =0x1e6e0120 + ldr r1, =0x00000002 + str r1, [r0] + +/* Debug - UART console message */ + ldr r0, =0x1e784000 + mov r1, #0x62 @ 'b' + str r1, [r0] +/* Debug - UART console message */ + +ddr4_vref_ddr_loop: + ldr r0, =0x1e6e0060 + ldr r1, =0x00000000 + str r1, [r0] + + add r10, r10, #0x01 + cmp r10, #0x40 + beq ddr4_vref_ddr_test_fail @ no valid margin and retry + + ldr r0, =0x1e6e02c0 + mov r1, #0x06 + orr r1, r1, r10, lsl #8 + str r1, [r0] + + ldr r0, =0x1e6e0060 + ldr r1, =0x00000005 + str r1, [r0] + b ddr_phy_init_process + +ddr4_vref_ddr_phyinit_done: + + b cbr_test_start + +ddr4_vref_ddr_cbrtest_done: + cmp r9, #0x01 + bne ddr4_vref_ddr_test_fail + add r8, r8, #0x01 + cmp r6, r10 + movgt r6, r10 + cmp r7, r10 + movlt r7, r10 + b ddr4_vref_ddr_loop + +ddr4_vref_ddr_test_fail: + cmp r8, #0x0 + bne ddr4_vref_ddr_loop_end + cmp r10, #0x40 + beq ddr4_vref_ddr_cal_start + b ddr4_vref_ddr_loop + +ddr4_vref_ddr_loop_end: + ldr r0, =0x1e6e0060 + ldr r1, =0x00000000 + str r1, [r0] + + ldr r0, =0x1e6e02c0 + add r1, r6, r7 + add r1, r1, #0x01 + mov r2, r1, lsr #1 + mov r1, r2, lsl #8 + orr r1, r1, #0x06 + str r1, [r0] + +/* Debug - UART console message */ + ldr r0, =0x1e784000 + mov r1, #0x63 @ 'c' + str r1, [r0] +/* Debug - UART console message */ + + ldr r0, =0x1e6e0120 + ldr r1, =0x00000003 + str r1, [r0] + + ldr r0, =0x1e6e0060 @ Fire DDRPHY Init + ldr r1, =0x00000005 + str r1, [r0] + b ddr_phy_init_process + +ddr4_phyinit_done: + /*******************************************/ +/* Debug - UART console message */ + ldr r0, =0x1e784000 + mov r1, #0x31 @ '1' + str r1, [r0] +/* Debug - UART console message */ + + ldr r0, =0x1e6e000c +#ifdef CONFIG_DRAM_EXT_TEMP + ldr r1, =0x42AA2F81 +#else + ldr r1, =0x42AA5C81 +#endif + str r1, [r0] + + ldr r0, =0x1e6e0034 + ldr r1, =0x0001AF93 + str r1, [r0] + + ldr r0, =0x1e6e0120 @ VGA Compatible Mode + ldr r1, [r5, #ASTMMC_REGIDX_PLL] + str r1, [r0] + + b Calibration_End + +.LTORG +/****************************************************************************** + End DDR4 Init + ******************************************************************************/ +/****************************************************************************** + Global Process + ******************************************************************************/ + /******************************************** + DDRPHY Init Process + ********************************************/ +ddr_phy_init_process: + clear_delay_timer + /* Wait DDR PHY init done - timeout 300 ms */ + ldr r2, =0x000493E0 @ Set Timer3 Reload = 300 ms + init_delay_timer + ldr r3, =0x1e6e0060 +ddr_phy_init: + check_delay_timer + beq ddr_phy_init_timeout + ldr r1, [r3] + tst r1, #0x01 + bne ddr_phy_init + + /* Check DDR PHY init status */ + ldr r0, =0x1e6e0300 + ldr r2, =0x000A0000 + ldr r1, [r0] + tst r1, r2 + beq ddr_phy_init_success + +ddr_phy_init_timeout: + ldr r0, =0x1e6e0060 @ Reset PHY + mov r1, #0x00 + str r1, [r0] + +/* Debug - UART console message */ + ldr r0, =0x1e784000 + mov r1, #0x2E @ '.' + str r1, [r0] +/* Debug - UART console message */ + + clear_delay_timer + /* Delay about 10us */ + ldr r2, =0x0000000A @ Set Timer3 Reload = 10 us + init_delay_timer +ddr_phy_init_delay_0: + check_delay_timer + bne ddr_phy_init_delay_0 + clear_delay_timer + /* end delay 10us */ + + ldr r0, =0x1e6e0060 @ Fire PHY Init + mov r1, #0x05 + str r1, [r0] + b ddr_phy_init_process + +ddr_phy_init_success: + clear_delay_timer + ldr r0, =0x1e6e0060 + mov r1, #0x06 + str r1, [r0] + + ldr r0, =0x1e6e0120 + ldr r1, [r0] + cmp r1, #0 + beq ddr3_phyinit_done + cmp r1, #1 + beq ddr4_vref_phy_phyinit_done + cmp r1, #2 + beq ddr4_vref_ddr_phyinit_done + b ddr4_phyinit_done + + /******************************************** + CBRTest + ********************************************/ +cbr_test_start: + ldr r0, =0x1e6e000c + ldr r1, =0x00005C01 + str r1, [r0] + ldr r0, =0x1e6e0074 + ldr r1, =0x0000FFFF @ test size = 64KB + str r1, [r0] + ldr r0, =0x1e6e007c + ldr r1, =0xFF00FF00 + str r1, [r0] + +cbr_test_single: + ldr r0, =0x1e6e0070 + ldr r1, =0x00000000 + str r1, [r0] + ldr r1, =0x00000085 + str r1, [r0] + ldr r3, =0x3000 + ldr r11, =0x50000 +cbr_wait_engine_idle_0: + subs r11, r11, #1 + beq cbr_test_fail + ldr r2, [r0] + tst r2, r3 @ D[12] = idle bit + beq cbr_wait_engine_idle_0 + + ldr r0, =0x1e6e0070 @ read fail bit status + ldr r3, =0x2000 + ldr r2, [r0] + tst r2, r3 @ D[13] = fail bit + bne cbr_test_fail + +cbr_test_burst: + mov r1, #0x00 @ initialize loop index, r1 is loop index +cbr_test_burst_loop: + ldr r0, =0x1e6e0070 + ldr r2, =0x00000000 + str r2, [r0] + mov r2, r1, lsl #3 + orr r2, r2, #0xC1 @ test command = 0xC1 | (datagen << 3) + str r2, [r0] + ldr r3, =0x3000 + ldr r11, =0x20000 +cbr_wait_engine_idle_1: + subs r11, r11, #1 + beq cbr_test_fail + ldr r2, [r0] + tst r2, r3 @ D[12] = idle bit + beq cbr_wait_engine_idle_1 + + ldr r0, =0x1e6e0070 @ read fail bit status + ldr r3, =0x2000 + ldr r2, [r0] + tst r2, r3 @ D[13] = fail bit + bne cbr_test_fail + + add r1, r1, #1 @ increase the test mode index + cmp r1, #0x04 @ test 4 modes + bne cbr_test_burst_loop + + ldr r0, =0x1e6e0070 + ldr r1, =0x00000000 + str r1, [r0] + mov r9, #0x1 + b cbr_test_pattern_end @ CBRTest() return(1) + +cbr_test_fail: + ldr r0, =0x1e6e0070 + ldr r1, =0x00000000 + str r1, [r0] + mov r9, #0x0 @ CBRTest() return(0) + +cbr_test_pattern_end: + ldr r0, =0x1e6e000c + ldr r1, =0x00000000 + str r1, [r0] + ldr r0, =0x1e6e0120 + ldr r1, [r0] + cmp r1, #1 + beq ddr4_vref_phy_cbrtest_done + b ddr4_vref_ddr_cbrtest_done + +.LTORG +/****************************************************************************** + Other features configuration + *****************************************************************************/ +Calibration_End: + /******************************* + Check DRAM Size + 1Gb : 0x80000000 ~ 0x87FFFFFF + 2Gb : 0x80000000 ~ 0x8FFFFFFF + 4Gb : 0x80000000 ~ 0x9FFFFFFF + 8Gb : 0x80000000 ~ 0xBFFFFFFF + *******************************/ + ldr r0, =0x1e6e0004 + ldr r6, [r0] + bic r6, r6, #0x00000003 @ record MCR04 + ldr r7, [r5, #ASTMMC_REGIDX_RFC] + +check_dram_size: + ldr r0, =0xA0100000 + ldr r1, =0x41424344 + str r1, [r0] + ldr r0, =0x90100000 + ldr r1, =0x35363738 + str r1, [r0] + ldr r0, =0x88100000 + ldr r1, =0x292A2B2C + str r1, [r0] + ldr r0, =0x80100000 + ldr r1, =0x1D1E1F10 + str r1, [r0] + ldr r0, =0xA0100000 + ldr r1, =0x41424344 + ldr r2, [r0] + cmp r2, r1 @ == 8Gbit + orreq r6, r6, #0x03 + moveq r7, r7, lsr #24 + mov r3, #0x38 @ '8' + beq check_dram_size_end + ldr r0, =0x90100000 + ldr r1, =0x35363738 + ldr r2, [r0] + cmp r2, r1 @ == 4Gbit + orreq r6, r6, #0x02 + moveq r7, r7, lsr #16 + mov r3, #0x34 @ '4' + beq check_dram_size_end + ldr r0, =0x88100000 + ldr r1, =0x292A2B2C + ldr r2, [r0] + cmp r2, r1 @ == 2Gbit + orreq r6, r6, #0x01 + moveq r7, r7, lsr #8 + mov r3, #0x32 @ '2' + beq check_dram_size_end + mov r3, #0x31 @ '1' + +check_dram_size_end: + ldr r0, =0x1e6e0004 + str r6, [r0] + ldr r0, =0x1e6e0014 + ldr r1, [r0] + bic r1, r1, #0x000000FF + and r7, r7, #0xFF + orr r1, r1, r7 + str r1, [r0] + + /* Version Number */ + ldr r0, =0x1e6e0004 + ldr r1, [r0] + mov r2, #ASTMMC_INIT_VER + orr r1, r1, r2, lsl #20 + str r1, [r0] + + ldr r0, =0x1e6e0088 + ldr r1, =ASTMMC_INIT_DATE + str r1, [r0] + +/* Debug - UART console message */ + ldr r0, =0x1e784000 + mov r1, #0x2D @ '-' + str r1, [r0] + str r3, [r0] + mov r1, #0x47 @ 'G' + str r1, [r0] + mov r1, #0x62 @ 'b' + str r1, [r0] + mov r1, #0x2D @ '-' + str r1, [r0] +/* Debug - UART console message */ + + /* Enable DRAM Cache */ + ldr r0, =0x1e6e0004 + ldr r1, [r0] + mov r2, #1 + orr r2, r1, r2, lsl #12 + str r2, [r0] + ldr r3, =0x00080000 +dram_cache_init: + ldr r2, [r0] + tst r2, r3 + beq dram_cache_init + mov r2, #1 + orr r1, r1, r2, lsl #10 + str r1, [r0] + + /* Set DRAM requests threshold */ + ldr r0, =0x1e6e001c + ldr r1, =0x00000008 + str r1, [r0] + ldr r0, =0x1e6e0038 + ldr r1, =0xFFFFFF00 + str r1, [r0] + + /******************************************** + DDRTest + ********************************************/ +ddr_test_start: + ldr r0, =0x1e6e0074 + ldr r1, =0x0000FFFF @ test size = 64KB + str r1, [r0] + ldr r0, =0x1e6e007c + ldr r1, =0xFF00FF00 + str r1, [r0] + +ddr_test_burst: + mov r1, #0x00 @ initialize loop index, r1 is loop index +ddr_test_burst_loop: + ldr r0, =0x1e6e0070 + ldr r2, =0x00000000 + str r2, [r0] + mov r2, r1, lsl #3 + orr r2, r2, #0xC1 @ test command = 0xC1 | (datagen << 3) + str r2, [r0] + ldr r3, =0x3000 + ldr r11, =0x20000 +ddr_wait_engine_idle_1: + subs r11, r11, #1 + beq ddr_test_fail + ldr r2, [r0] + tst r2, r3 @ D[12] = idle bit + beq ddr_wait_engine_idle_1 + + ldr r0, =0x1e6e0070 @ read fail bit status + ldr r3, =0x2000 + ldr r2, [r0] + tst r2, r3 @ D[13] = fail bit + bne ddr_test_fail + + add r1, r1, #1 @ increase the test mode index + cmp r1, #0x01 @ test 1 modes + bne ddr_test_burst_loop + + ldr r0, =0x1e6e0070 + ldr r1, =0x00000000 + str r1, [r0] + b set_scratch @ CBRTest() return(1) + +ddr_test_fail: +/* Debug - UART console message */ + ldr r0, =0x1e784000 + mov r1, #0x46 @ 'F' + str r1, [r0] + mov r1, #0x61 @ 'a' + str r1, [r0] + mov r1, #0x69 @ 'i' + str r1, [r0] + mov r1, #0x6C @ 'l' + str r1, [r0] + mov r1, #0x0D @ '\r' + str r1, [r0] + mov r1, #0x0A @ '\n' + str r1, [r0] + ldr r0, =0x1e784014 +wait_print_0: + ldr r1, [r0] + tst r1, #0x40 + beq wait_print_0 +/* Debug - UART console message */ + b reset_mmc + +set_scratch: + /*Set Scratch register Bit 6 after ddr initial finished */ + ldr r0, =0x1e6e2040 + ldr r1, [r0] + orr r1, r1, #0x41 + str r1, [r0] + +/* Debug - UART console message */ + ldr r0, =0x1e784000 + mov r1, #0x44 @ 'D' + str r1, [r0] + mov r1, #0x6F @ 'o' + str r1, [r0] + mov r1, #0x6E @ 'n' + str r1, [r0] + mov r1, #0x65 @ 'e' + str r1, [r0] + mov r1, #0x0D @ '\r' + str r1, [r0] + mov r1, #0x0A @ '\n' + str r1, [r0] +/* Debug - UART console message */ + + /* Enable VGA display */ + ldr r0, =0x1e6e202c + ldr r1, [r0] + bic r1, r1, #0x40 + str r1, [r0] + +/* Debug - UART console message */ + /* Print PHY timing information */ + ldr r0, =0x1e784014 +wait_print_1: + ldr r1, [r0] + tst r1, #0x40 + beq wait_print_1 + + ldr r0, =0x1e784000 + mov r1, #0x52 @ 'R' + str r1, [r0] + mov r1, #0x65 @ 'e' + str r1, [r0] + mov r1, #0x61 @ 'a' + str r1, [r0] + mov r1, #0x64 @ 'd' + str r1, [r0] + mov r1, #0x20 @ ' ' + str r1, [r0] + mov r1, #0x6D @ 'm' + str r1, [r0] + mov r1, #0x61 @ 'a' + str r1, [r0] + mov r1, #0x72 @ 'r' + str r1, [r0] + mov r1, #0x67 @ 'g' + str r1, [r0] + mov r1, #0x69 @ 'i' + str r1, [r0] + mov r1, #0x6E @ 'n' + str r1, [r0] + mov r1, #0x2D @ '-' + str r1, [r0] + mov r1, #0x44 @ 'D' + str r1, [r0] + mov r1, #0x4C @ 'L' + str r1, [r0] + mov r1, #0x3A @ ':' + str r1, [r0] + + ldr r0, =0x1e784014 +wait_print_2: + ldr r1, [r0] + tst r1, #0x40 + beq wait_print_2 + + ldr r7, =0x000001FE @ divide by 510 + mov r8, #10 @ multiply by 10 +print_DQL_eye_margin: + ldr r0, =0x1e6e03d0 + ldr r2, [r0] + and r2, r2, #0xFF + ldr r0, =0x1e784000 + mov r1, #0x30 @ '0' + str r1, [r0] + mov r1, #0x2E @ '.' + str r1, [r0] + mov r3, #0x4 @ print 4 digits +print_DQL_div_loop: + mul r2, r8, r2 + cmp r2, r7 + blt print_DQL_div_0 + mov r6, #0x0 +print_DQL_div_digit: + sub r2, r2, r7 + add r6, r6, #0x1 + cmp r2, r7 + bge print_DQL_div_digit + b print_DQL_div_n + +print_DQL_div_0: + mov r1, #0x30 @ '0' + str r1, [r0] + b print_DQL_next +print_DQL_div_n: + add r1, r6, #0x30 @ print n + str r1, [r0] +print_DQL_next: + subs r3, r3, #1 + beq print_DQH_eye_margin + cmp r2, #0x0 + beq print_DQH_eye_margin + b print_DQL_div_loop + +print_DQH_eye_margin: + mov r1, #0x2F @ '/' + str r1, [r0] + mov r1, #0x44 @ 'D' + str r1, [r0] + mov r1, #0x48 @ 'H' + str r1, [r0] + mov r1, #0x3A @ ':' + str r1, [r0] + + ldr r0, =0x1e784014 +wait_print_3: + ldr r1, [r0] + tst r1, #0x40 + beq wait_print_3 + + ldr r0, =0x1e6e03d0 + ldr r2, [r0] + mov r2, r2, lsr #8 + and r2, r2, #0xFF + ldr r0, =0x1e784000 + mov r1, #0x30 @ '0' + str r1, [r0] + mov r1, #0x2E @ '.' + str r1, [r0] + mov r3, #0x4 @ print 4 digits +print_DQH_div_loop: + mul r2, r8, r2 + cmp r2, r7 + blt print_DQH_div_0 + mov r6, #0x0 +print_DQH_div_digit: + sub r2, r2, r7 + add r6, r6, #0x1 + cmp r2, r7 + bge print_DQH_div_digit + b print_DQH_div_n + +print_DQH_div_0: + mov r1, #0x30 @ '0' + str r1, [r0] + b print_DQH_next +print_DQH_div_n: + add r1, r6, #0x30 @ print n + str r1, [r0] +print_DQH_next: + subs r3, r3, #1 + beq print_DQ_eye_margin_last + cmp r2, #0x0 + beq print_DQ_eye_margin_last + b print_DQH_div_loop + +print_DQ_eye_margin_last: + mov r1, #0x20 @ ' ' + str r1, [r0] + mov r1, #0x43 @ 'C' + str r1, [r0] + mov r1, #0x4B @ 'K' + str r1, [r0] + + ldr r0, =0x1e784014 +wait_print_4: + ldr r1, [r0] + tst r1, #0x40 + beq wait_print_4 + + ldr r0, =0x1e784000 + mov r1, #0x20 @ ' ' + str r1, [r0] + mov r1, #0x28 @ '(' + str r1, [r0] + mov r1, #0x6D @ 'm' + str r1, [r0] + mov r1, #0x69 @ 'i' + str r1, [r0] + mov r1, #0x6E @ 'n' + str r1, [r0] + mov r1, #0x3A @ ':' + str r1, [r0] + mov r1, #0x30 @ '0' + str r1, [r0] + mov r1, #0x2E @ '.' + str r1, [r0] + mov r1, #0x33 @ '3' + str r1, [r0] + mov r1, #0x35 @ '5' + str r1, [r0] + mov r1, #0x29 @ ')' + str r1, [r0] + mov r1, #0x0D @ '\r' + str r1, [r0] + mov r1, #0x0A @ '\n' + str r1, [r0] +/* Debug - UART console message */ + +platform_exit: +#ifdef CONFIG_DRAM_ECC + ldr r0, =0x1e6e0004 + ldr r1, [r0] + orr r1, r1, #0x80 + str r1, [r0] + + ldr r0, =0x1e6e0054 + ldr r1, =CONFIG_DRAM_ECC_SIZE /* ECC protected memory size */ + str r1, [r0] + + ldr r0, =0x1e6e007C + ldr r1, =0x00000000 + str r1, [r0] + ldr r0, =0x1e6e0074 + str r1, [r0] + + ldr r0, =0x1e6e0070 + ldr r1, =0x00000221 + str r1, [r0] + + ldr r2, =0x00001000 +ECC_Init_Flag: + ldr r1, [r0] + tst r1, r2 @ D[12] = 1, Done + beq ECC_Init_Flag + + ldr r1, =0x00000000 + str r1, [r0] + + ldr r0, =0x1e6e0050 + ldr r1, =0x80000000 + str r1, [r0] + + ldr r0, =0x1e6e0050 + ldr r1, =0x00000000 + str r1, [r0] + + ldr r0, =0x1e6e0070 + ldr r1, =0x00000400 @ Enable ECC auto-scrubbing + str r1, [r0] +#endif + +/****************************************************************************** + SPI Timing Calibration + ******************************************************************************/ + mov r2, #0x0 + mov r6, #0x0 + mov r7, #0x0 + init_spi_checksum +spi_checksum_wait_0: + ldr r1, [r0] + tst r1, r2 + beq spi_checksum_wait_0 + ldr r0, =0x1e620090 + ldr r5, [r0] @ record golden checksum + ldr r0, =0x1e620080 + mov r1, #0x0 + str r1, [r0] + + ldr r0, =0x1e620010 @ set to fast read mode + ldr r1, =0x000B0041 + str r1, [r0] + + ldr r6, =0x00F7E6D0 @ Init spiclk loop + mov r8, #0x0 @ Init delay record + +spi_cbr_next_clkrate: + mov r6, r6, lsr #0x4 + cmp r6, #0x0 + beq spi_cbr_end + + mov r7, #0x0 @ Init delay loop + mov r8, r8, lsl #4 + +spi_cbr_next_delay_s: + mov r2, #0x8 + init_spi_checksum +spi_checksum_wait_1: + ldr r1, [r0] + tst r1, r2 + beq spi_checksum_wait_1 + ldr r0, =0x1e620090 + ldr r2, [r0] @ read checksum + ldr r0, =0x1e620080 + mov r1, #0x0 + str r1, [r0] + cmp r2, r5 + bne spi_cbr_next_delay_e + + mov r2, #0x0 + init_spi_checksum +spi_checksum_wait_2: + ldr r1, [r0] + tst r1, r2 + beq spi_checksum_wait_2 + ldr r0, =0x1e620090 + ldr r2, [r0] @ read checksum + ldr r0, =0x1e620080 + mov r1, #0x0 + str r1, [r0] + cmp r2, r5 + bne spi_cbr_next_delay_e + + orr r8, r8, r7 @ record passed delay + b spi_cbr_next_clkrate + +spi_cbr_next_delay_e: + add r7, r7, #0x1 + cmp r7, #0x6 + blt spi_cbr_next_delay_s + b spi_cbr_next_clkrate + +spi_cbr_end: + ldr r0, =0x1e620094 + str r8, [r0] + ldr r0, =0x1e620010 + mov r1, #0x0 + str r1, [r0] + +/****************************************************************************** + Miscellaneous Setting + ******************************************************************************/ + /* Set UART DMA as AHB high priority master */ + ldr r0, =0x1e600000 + ldr r1, =0xAEED1A03 + str r1, [r0] + + ldr r0, =0x1e600080 + ldr r2, =0x100 + ldr r1, [r0] + orr r1, r1, r2 + str r1, [r0] + + /* Enable UART3/4 clock and disable LHCLK */ + ldr r0, =0x1e6e200c + ldr r1, [r0] + ldr r2, =0xF9FFFFFF + and r1, r1, r2 + ldr r2, =0x10000000 + orr r1, r1, r2 + str r1, [r0] + + ldr r0, =0x1e6e2008 @ Set Video ECLK phase + ldr r1, [r0] + ldr r2, =0x0ffffff3 + and r1, r1, r2 + str r1, [r0] + + ldr r0, =0x1e6e2004 @ Enable JTAG Master, solve ARM stucked by JTAG issue + ldr r1, [r0] + bic r1, r1, #0x00400000 + str r1, [r0] + +/****************************************************************************** + Configure MAC timing + ******************************************************************************/ + /* Enable D2PLL and set to 250MHz */ + ldr r0, =0x1e6e213c + ldr r1, =0x00000585 @ Reset D2PLL + str r1, [r0] + + ldr r0, =0x1e6e202c + ldr r1, [r0] + bic r1, r1, #0x10 @ Enable D2PLL + ldr r2, =0x00200000 @ Set CRT = 40MHz + orr r1, r1, r2 + str r1, [r0] + + ldr r2, =0x8E00A17C @ Set to 250MHz + + ldr r0, =0x1e6e2070 @ Check CLKIN = 25MHz + ldr r1, [r0] + mov r1, r1, lsr #23 + tst r1, #0x01 + beq set_D2PLL + ldr r2, =0x8E00A177 + +set_D2PLL: + ldr r0, =0x1e6e201c + str r2, [r0] + ldr r0, =0x1e6e213c @ Enable D2PLL + ldr r1, =0x00000580 + str r1, [r0] + + ldr r0, =0x1e6e204c + ldr r1, [r0] + bic r1, r1, #0xFF0000 + ldr r2, =0x00040000 @ Set divider ratio + orr r1, r1, r2 + str r1, [r0] + + ldr r0, =0x1e6e2048 @ Set MAC interface delay timing = 1G + ldr r1, =0x80082208 @ Select internal 125MHz + str r1, [r0] + ldr r0, =0x1e6e20b8 @ Set MAC interface delay timing = 100M + str r1, [r0] + ldr r0, =0x1e6e20bc @ Set MAC interface delay timing = 10M + str r1, [r0] + + ldr r0, =0x1e6e2070 @ Set MAC AHB bus clock + ldr r1, [r0] + mov r2, #0x04 @ Default RMII, set MHCLK = HPLL/10 + tst r1, #0xC0 + movne r2, #0x02 @ if RGMII, set MHCLK = HPLL/6 + ldr r0, =0x1e6e2008 + ldr r1, [r0] + bic r1, r1, #0x00070000 + orr r1, r1, r2, lsl #16 + str r1, [r0] + + ldr r0, =0x1e6e21dc @ Set MAC duty + ldr r1, =0x00666400 + str r1, [r0] + + ldr r0, =0x1e6e2090 @ Enable MAC interface pull low + ldr r1, [r0] + bic r1, r1, #0x0000F000 + str r1, [r0] + +/* Test - DRAM initial time */ + ldr r0, =0x1e782040 + ldr r1, [r0] + ldr r0, =0xFFFFFFFF + sub r1, r0, r1 + ldr r0, =0x1e6e008c + str r1, [r0] + ldr r0, =0x1e78203c + ldr r1, =0x0000F000 + str r1, [r0] +/* Test - DRAM initial time */ + + ldr r0, =0x1e6e0000 @ disable MMC password + mov r1, #0x0 + str r1, [r0] + + /* Disable Timer separate mode */ + ldr r0, =0x1e782038 + ldr r1, =0xEA + str r1, [r0] + + /* restore lr */ + mov lr, r4 + + /* back to arch calling code */ + mov pc, lr + diff --git a/arch/arm/mach-aspeed/reset.c b/arch/arm/mach-aspeed/reset.c new file mode 100644 index 0000000000..b4d8c40623 --- /dev/null +++ b/arch/arm/mach-aspeed/reset.c @@ -0,0 +1,18 @@ +/* + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. +*/ + +#include +#include +#include + +void reset_cpu(ulong addr) +{ + __raw_writel(0x10 , AST_WDT_BASE+0x04); + __raw_writel(0x4755, AST_WDT_BASE+0x08); + __raw_writel(0x3, AST_WDT_BASE+0x0c); + + while (1) + /*nothing*/; +} diff --git a/arch/arm/mach-aspeed/timer.c b/arch/arm/mach-aspeed/timer.c new file mode 100644 index 0000000000..626f992429 --- /dev/null +++ b/arch/arm/mach-aspeed/timer.c @@ -0,0 +1,140 @@ +/* + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * Ryan Chen + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if CONFIG_ASPEED_TIMER_CLK < CONFIG_SYS_HZ +#error "CONFIG_ASPEED_TIMER_CLK must be as large as CONFIG_SYS_HZ" +#endif + +#define TIMER_LOAD_VAL 0xffffffff +#define CLK_PER_HZ (CONFIG_ASPEED_TIMER_CLK / CONFIG_SYS_HZ) + +/* macro to read the 32 bit timer */ +#define READ_CLK (*(volatile ulong *)(AST_TIMER_BASE + 0)) +#define READ_TIMER (READ_CLK / CLK_PER_HZ) + +static ulong timestamp; +static ulong lastdec; + +int timer_init (void) +{ + *(volatile ulong *)(AST_TIMER_BASE + 4) = TIMER_LOAD_VAL; + *(volatile ulong *)(AST_TIMER_BASE + 0x30) = 0x3; /* enable timer1 */ + + /* init the timestamp and lastdec value */ + reset_timer_masked(); + + return 0; +} + +/* + * timer without interrupts + */ + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +/* delay x useconds AND perserve advance timstamp value */ +void __udelay (unsigned long usec) +{ + ulong last = READ_CLK; + ulong clks; + ulong elapsed = 0; + + /* translate usec to clocks */ + clks = (usec / 1000) * CLK_PER_HZ; + clks += (usec % 1000) * CLK_PER_HZ / 1000; + + while (clks > elapsed) { + ulong now = READ_CLK; + if (now <= last) { + elapsed += last - now; + } else { + elapsed += TIMER_LOAD_VAL - (now - last); + } + last = now; + } +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastdec = READ_TIMER; /* capure current decrementer value time */ + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +ulong get_timer_masked (void) +{ + ulong now = READ_TIMER; /* current tick value */ + + if (lastdec >= now) { /* normal mode (non roll) */ + /* move stamp fordward with absolute diff ticks */ + timestamp += lastdec - now; + } else { /* we have overflow of the count down timer */ + + /* nts = ts + ld + (TLV - now) + * ts=old stamp, ld=time that passed before passing through -1 + * (TLV-now) amount of time after passing though -1 + * nts = new "advancing time stamp"... it could also roll and + * cause problems. + */ + timestamp += lastdec + (TIMER_LOAD_VAL / CLK_PER_HZ) - now; + } + lastdec = now; + + return timestamp; +} + +/* waits specified delay value and resets timestamp */ +void udelay_masked (unsigned long usec) +{ + __udelay(usec); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + return CONFIG_SYS_HZ; +} -- cgit v1.2.1