From 61d122583fb8163e0ea7c43a0fa7d5ff1241b782 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 22 Oct 2014 16:32:29 +0300 Subject: keystone2: clock: add K2L clock definitions and commands This patch adds clock definitions and commands to support Keystone II K2L SOC. Acked-by: Vitaly Andrianov Signed-off-by: Hao Zhang Signed-off-by: Ivan Khoronzhuk --- arch/arm/include/asm/arch-keystone/clock-k2l.h | 89 ++++++++++++++++++++++++++ arch/arm/include/asm/arch-keystone/clock.h | 4 ++ 2 files changed, 93 insertions(+) create mode 100644 arch/arm/include/asm/arch-keystone/clock-k2l.h (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-keystone/clock-k2l.h b/arch/arm/include/asm/arch-keystone/clock-k2l.h new file mode 100644 index 0000000000..ad2e40747a --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/clock-k2l.h @@ -0,0 +1,89 @@ +/* + * K2L: Clock management APIs + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_CLOCK_K2L_H +#define __ASM_ARCH_CLOCK_K2L_H + +enum ext_clk_e { + sys_clk, + alt_core_clk, + pa_clk, + tetris_clk, + ddr3_clk, + pcie_clk, + sgmii_clk, + usb_clk, + rp1_clk, + ext_clk_count /* number of external clocks */ +}; + +extern unsigned int external_clk[ext_clk_count]; + +#define CLK_LIST(CLK)\ + CLK(0, core_pll_clk)\ + CLK(1, pass_pll_clk)\ + CLK(2, tetris_pll_clk)\ + CLK(3, ddr3_pll_clk)\ + CLK(4, sys_clk0_clk)\ + CLK(5, sys_clk0_1_clk)\ + CLK(6, sys_clk0_2_clk)\ + CLK(7, sys_clk0_3_clk)\ + CLK(8, sys_clk0_4_clk)\ + CLK(9, sys_clk0_6_clk)\ + CLK(10, sys_clk0_8_clk)\ + CLK(11, sys_clk0_12_clk)\ + CLK(12, sys_clk0_24_clk)\ + CLK(13, sys_clk1_clk)\ + CLK(14, sys_clk1_3_clk)\ + CLK(15, sys_clk1_4_clk)\ + CLK(16, sys_clk1_6_clk)\ + CLK(17, sys_clk1_12_clk)\ + CLK(18, sys_clk2_clk)\ + CLK(19, sys_clk3_clk)\ + +#define PLLSET_CMD_LIST "" + +#define KS2_CLK1_6 sys_clk0_6_clk + +/* PLL identifiers */ +enum pll_type_e { + CORE_PLL, + PASS_PLL, + TETRIS_PLL, + DDR3_PLL, +}; + +enum { + SPD800, + SPD1000, + SPD1200, + SPD1350, + SPD1400, + SPD_RSV +}; + +#define CORE_PLL_799 {CORE_PLL, 13, 1, 2} +#define CORE_PLL_983 {CORE_PLL, 16, 1, 2} +#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2} +#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2} +#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2} +#define PASS_PLL_983 {PASS_PLL, 16, 1, 2} +#define PASS_PLL_1050 {PASS_PLL, 205, 12, 2} +#define TETRIS_PLL_491 {TETRIS_PLL, 8, 1, 2} +#define TETRIS_PLL_737 {TETRIS_PLL, 12, 1, 2} +#define TETRIS_PLL_799 {TETRIS_PLL, 13, 1, 2} +#define TETRIS_PLL_983 {TETRIS_PLL, 16, 1, 2} +#define TETRIS_PLL_1167 {TETRIS_PLL, 19, 1, 2} +#define TETRIS_PLL_1228 {TETRIS_PLL, 20, 1, 2} +#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2} +#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4} +#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2} +#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6} + +#endif diff --git a/arch/arm/include/asm/arch-keystone/clock.h b/arch/arm/include/asm/arch-keystone/clock.h index c5efc6910a..7218230c41 100644 --- a/arch/arm/include/asm/arch-keystone/clock.h +++ b/arch/arm/include/asm/arch-keystone/clock.h @@ -20,6 +20,10 @@ #include #endif +#ifdef CONFIG_SOC_K2L +#include +#endif + #define MAIN_PLL CORE_PLL #include -- cgit v1.2.1