From e3ce3aa103c9e40415673df70ee62732cdb966c3 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Sat, 5 Mar 2016 17:32:30 +0530 Subject: ARM: DRA7: emif: Check for enable bits before updating leveling output Read and write leveling can be enabled independently. Check for these enable bits before updating the read and write leveling output values. This will allow to use the combination of software and hardware leveling. Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini --- arch/arm/include/asm/emif.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/include/asm/emif.h') diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 7986e6e794..b03cf5a8c4 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -478,6 +478,12 @@ #define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK (0xFF << 4) #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12 #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK (0xFFFFF << 12) +#define EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_SHIFT 25 +#define EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK (1 << 25) +#define EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_SHIFT 26 +#define EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK (1 << 26) +#define EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_SHIFT 27 +#define EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK (1 << 27) /* DDR_PHY_CTRL_2 */ #define EMIF_REG_DDR_PHY_CTRL_2_SHIFT 0 -- cgit v1.2.1