From 722e000ccd7226c5cd071590b5361620eb0b126c Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Thu, 25 Jun 2015 09:50:44 -0700 Subject: Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc. Added PLL variables (dividers mask/shift, lock enable/detect, etc.) to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X. Used pllinfo struct in all clock functions, validated on T210. Should be equivalent to prior code on T124/114/30/20. Thanks to Marcel Ziswiler for corrections to the T20/T30 values. Signed-off-by: Marcel Ziswiler Tested-by: Marcel Ziswiler Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra210/clock-tables.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include/asm/arch-tegra210') diff --git a/arch/arm/include/asm/arch-tegra210/clock-tables.h b/arch/arm/include/asm/arch-tegra210/clock-tables.h index b62e0702a5..175040dae6 100644 --- a/arch/arm/include/asm/arch-tegra210/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra210/clock-tables.h @@ -25,6 +25,7 @@ enum clock_id { CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, CLOCK_ID_EPCI, CLOCK_ID_SFROM32KHZ, + CLOCK_ID_DP, /* These are the base clocks (inputs to the Tegra SoC) */ CLOCK_ID_32KHZ, -- cgit v1.2.1