From d612f0ab34b27be4ad50b1236fbd6c84450997f1 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Tue, 9 Dec 2014 17:38:02 +0800 Subject: arm: ls102xa: Add QSPI boot support for LS1021AQDS/TWR board This patch adds QSPI boot support for LS1021AQDS/TWR board. The QSPI boot image need to be programmed into the QSPI flash first. Then the booting will start from QSPI memory space. Signed-off-by: Alison Wang Reviewed-by: York Sun --- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h') diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index b0c267cfc2..98b268dffe 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -98,6 +98,7 @@ struct ccsr_gur { #define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f #define SCFG_ETSECCMCR_GE2_CLK125 0x04000000 #define SCFG_PIXCLKCR_PXCKEN 0x80000000 +#define SCFG_QSPI_CLKSEL 0xc0100000 /* Supplemental Configuration Unit */ struct ccsr_scfg { -- cgit v1.2.1 From 8ab967b6c6007adbd30e58dfa9ef69154a351484 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Tue, 9 Dec 2014 17:38:14 +0800 Subject: arm: ls102xa: Add NAND boot support for LS1021AQDS board This patch adds NAND boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from NAND flash to DDR, finally SPL transfer control to u-boot. Signed-off-by: Prabhakar Kushwaha Signed-off-by: Alison Wang Reviewed-by: York Sun --- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h') diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 98b268dffe..5abc3a196e 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -29,6 +29,11 @@ #define ARCH_TIMER_CTRL_ENABLE (1 << 0) #define SYS_COUNTER_CTRL_ENABLE (1 << 24) +#define DCFG_CCSR_PORSR1_RCW_MASK 0xff800000 +#define DCFG_CCSR_PORSR1_RCW_SRC_I2C 0x24800000 + +#define DCFG_DCSR_PORCR1 0 + struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; unsigned long freq_systembus; -- cgit v1.2.1 From 1a2826f6e02d0d3ec97b77b5b13c13d2ac27fb9d Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Fri, 21 Nov 2014 17:40:57 +0800 Subject: ls102xa: changing a few targets' configurations. Enable hypervisors utilizing the ARMv7 virtualization extension on the LS1021A-QDS/TWR boards with the A7 core tile, we add the required configuration variable. Signed-off-by: Xiubo Li Reviewed-by: York Sun --- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h') diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 5abc3a196e..697d4ca489 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -17,6 +17,9 @@ #define SOC_VER_LS1021 0x11 #define SOC_VER_LS1022 0x12 +#define CCSR_BRR_OFFSET 0xe4 +#define CCSR_SCRATCHRW1_OFFSET 0x200 + #define RCWSR0_SYS_PLL_RAT_SHIFT 25 #define RCWSR0_SYS_PLL_RAT_MASK 0x1f #define RCWSR0_MEM_PLL_RAT_SHIFT 16 -- cgit v1.2.1