From 6c343825dd8852843ee7426c579cb55520ad2fc8 Mon Sep 17 00:00:00 2001 From: Murali Karicheri Date: Wed, 10 Sep 2014 15:54:59 +0300 Subject: ARM: keystone: ddr3: workaround for ddr3a/3b memory issue This patch implements a workaround to fix DDR3 memory issue. The code for workaround detects PGSR0 errors and then preps for and executes a software-controlled hard reset.In board_early_init, where logic has been added to identify whether or not the previous reset was a PORz. PLL initialization is skipped in the case of a software-controlled hard reset. Signed-off-by: Murali Karicheri Signed-off-by: Keegan Garcia Signed-off-by: Ivan Khoronzhuk --- arch/arm/include/asm/arch-keystone/ddr3.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include/asm/arch-keystone/ddr3.h') diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h b/arch/arm/include/asm/arch-keystone/ddr3.h index 4d229a25fa..6bf35d3543 100644 --- a/arch/arm/include/asm/arch-keystone/ddr3.h +++ b/arch/arm/include/asm/arch-keystone/ddr3.h @@ -50,6 +50,7 @@ struct ddr3_emif_config { void ddr3_init(void); void ddr3_reset_ddrphy(void); +void ddr3_err_reset_workaround(void); void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg); void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg); -- cgit v1.2.1