From abc7d0f75c078524f713cb2d4b4efe1b1a122c60 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Thu, 28 Jan 2016 15:38:15 +0800 Subject: armv8: ls2080ardb: invert irq pins polarity for AQR405 PHY To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins polarity by setting IRQCR register, because AQR405 interrupt is low active but GIC accepts high active. Signed-off-by: Shaohui Xie Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/include/asm/arch-fsl-layerscape') diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 91f3ce843a..17c150ac8b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -98,6 +98,10 @@ #define DCFG_DCSR_BASE 0X700100000ULL #define DCFG_DCSR_PORCR1 0x000 +/* Interrupt Sampling Control */ +#define ISC_BASE 0x01F70000 +#define IRQCR_OFFSET 0x14 + /* Supplemental Configuration */ #define SCFG_BASE 0x01fc0000 #define SCFG_USB3PRM1CR 0x000 -- cgit v1.2.1