From 060c227a2861b0702e34eabe08eea9cc5bb68b45 Mon Sep 17 00:00:00 2001
From: Rajeshwari Birje <rajeshwari.s@samsung.com>
Date: Thu, 26 Dec 2013 09:44:21 +0530
Subject: Exynos5420: Add clock initialization for 5420

This patch adds code for clock initialization and clock settings
of various IP's and controllers, required for Exynos5420

Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
---
 arch/arm/include/asm/arch-exynos/clk.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'arch/arm/include/asm/arch-exynos/clk.h')

diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h
index 1d6fa9370f..cdeef324cc 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -14,6 +14,7 @@
 #define HPLL	3
 #define VPLL	4
 #define BPLL	5
+#define RPLL	6
 
 enum pll_src_bit {
 	EXYNOS_SRC_MPLL = 6,
-- 
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